CN117810211A

CN117810211A - Capacitors and integrated circuits

Info

Publication number: CN117810211A
Application number: CN202311861424.2A
Authority: CN
Inventors: 张晓宇; 岳丹诚; 胡燕萌
Original assignee: Suzhou Huatai Electronics Co Ltd
Current assignee: Suzhou Huatai Electronics Co Ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-04-02

Abstract

The embodiment of the application relates to the technical field of semiconductors and provides a capacitor, which comprises: MIM capacitor and coupling capacitor module. The coupling capacitor module comprises at least one coupling capacitor, and each coupling capacitor is respectively connected with the MIM capacitor in parallel; the plates of each coupling capacitor are at different heights in the thickness direction of the MIM capacitor. By forming a coupling capacitance and connecting the coupling capacitance in parallel with the MIM capacitance, the capacitance density of the capacitor is improved. Because each polar plate of each coupling capacitor is at different heights in the thickness direction of the MIM capacitor, the polar plates of the coupling capacitors can be manufactured by using masks used for manufacturing metal field plates of LDMOS devices, and the capacitance density can be improved on the premise of not increasing masks of the devices. The application also discloses an integrated circuit.

Description

Capacitor and integrated circuit

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a capacitor and an integrated circuit.

Background

In the existing MMIC (Monolithic Microwave Integrated Circuit ) design, MIM (Metal-Insulator-Metal) capacitors are often used as capacitors. The capacitance of the MIM capacitor is limited by the thickness and material of the insulating medium, so that the capacitance density of the MIM capacitor is difficult to increase without changing the withstand voltage and the material, and the cost is often increased to increase the capacitance density of the MIM capacitor, which limits the miniaturization of the MMIC chip area.

The above information disclosed in the background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The embodiment of the application provides a capacitor and an integrated circuit, so that the capacitor with higher capacitance density can be obtained easily at lower cost.

According to a first aspect of embodiments of the present application, there is provided a capacitor comprising: MIM capacitor; the coupling capacitor module comprises at least one coupling capacitor, and each coupling capacitor is respectively connected with the MIM capacitor in parallel; the plates of each coupling capacitor are at different heights in the thickness direction of the MIM capacitor.

In an alternative embodiment of the present application, the coupling capacitance module includes: at least one metal layer and at least one field plate layer, the at least one field plate layer and the one metal layer forming a coupling capacitance.

In an alternative embodiment of the present application, a metal layer closest to the MIM capacitor forms a coupling capacitor with the plate of the MIM capacitor.

In an alternative embodiment of the present application, adjacent field plates form a coupling capacitance in the presence of multiple field plates.

In an alternative embodiment of the present application, the coupling capacitor module further includes: and the gate metal layer, a field plate layer nearest to the gate metal layer and the gate metal layer form a coupling capacitor.

In an alternative embodiment of the present application, the coupling capacitor module includes a metal layer and a field plate layer; the metal layer and the polar plate of the MIM capacitor form a coupling capacitor; the field plate layer and the metal layer form a coupling capacitance.

In an alternative embodiment of the present application, the coupling capacitor module includes a metal layer, two field plate layers, and a gate metal layer; the metal layer and the polar plate of the MIM capacitor form a coupling capacitor; the field plate layer nearest to the metal layer and the metal layer form a coupling capacitor; the two field plate layers form a coupling capacitor; the field plate layer closest to the gate metal layer and the gate metal layer form a coupling capacitance.

In an alternative embodiment of the present application, the coupling capacitance module includes two field plate layers and one gate metal layer; the two field plate layers form a coupling capacitor; the field plate layer closest to the gate metal layer and the gate metal layer form a coupling capacitance.

In an alternative embodiment of the present application, the coupling capacitor module includes a metal layer, two field plate layers, and a gate metal layer; the metal layer and the polar plate of the MIM capacitor form a coupling capacitor; the field plate layer nearest to the metal layer and the metal layer form a coupling capacitor; two adjacent field plate layers respectively form coupling capacitors; the field plate layer closest to the gate metal layer and the gate metal layer form a coupling capacitance.

In an alternative embodiment of the present application, the coupling capacitance module includes: the first top metal layer is positioned above the MIM capacitor and is connected with the upper polar plate of the MIM capacitor through the first conductive through hole; the first metal layer is positioned below the MIM capacitor; a second metal layer is arranged in the first metal layer, the second metal layer is positioned in an area of the first metal layer hollowed out in the thickness direction, and the second metal layer is separated from the first metal layer by a gap; the second metal layer is connected with the lower polar plate of the MIM capacitor through a second conductive through hole; the first metal layer is connected with the first top metal layer through a first conductive structure, and a capacitance medium is arranged between the first metal layer and the lower polar plate of the MIM capacitor, so that the first metal layer, the lower polar plate and the capacitance medium between the first metal layer and the lower polar plate form a first coupling capacitor; the first field plate layer is positioned below the first metal layer; the first field plate layer is connected with the second metal layer through a third conductive through hole; a capacitive medium is arranged between the first field plate layer and the first metal layer, so that the first field plate layer, the first metal layer and the capacitive medium between the first field plate layer and the first metal layer form a second coupling capacitor; the second field plate layer is positioned below the first field plate layer; the second field plate layer is connected with the first metal layer through a fourth conductive through hole; a capacitance medium is arranged between the second field plate layer and the first field plate layer, so that the first field plate layer, the second field plate layer and the capacitance medium between the first field plate layer and the second field plate layer form a third coupling capacitance; a first gate metal layer located below the second field plate layer; the first field plate layer and the second field plate layer are hollowed in the thickness direction to form a first cavity and a second cavity respectively, and the fifth conductive through hole penetrates through the first cavity and the second cavity to connect the first grid metal layer and the second metal layer; a capacitive medium is disposed between the first gate metal layer and the second field plate layer, such that the first gate metal layer, the second field plate layer, and the capacitive medium therebetween form a fourth coupling capacitance.

In an alternative embodiment of the present application, the coupling capacitance module includes: the second top metal layer is positioned above the MIM capacitor and is connected with the upper polar plate of the MIM capacitor through a sixth conductive through hole; the third metal layer is positioned below the MIM capacitor; the third metal layer is connected with the lower polar plate of the MIM capacitor through a seventh conductive through hole; a third field plate layer located below the third metal layer; the third field plate layer is connected with the third metal layer through an eighth conductive through hole; the fourth field plate layer is positioned below the third field plate layer; the fourth field plate layer is connected with the second top metal layer through the second conductive structure; a capacitance medium is arranged between the fourth field plate layer and the third field plate layer, so that the third field plate layer, the fourth field plate layer and the capacitance medium between the third field plate layer and the fourth field plate layer form a fifth coupling capacitance; a second gate metal layer located below the second field plate layer; the third field plate layer and the fourth field plate layer are hollowed in the thickness direction to form a third cavity and a fourth cavity respectively, and the ninth conductive through hole penetrates through the third cavity and the fourth cavity to connect the second grid metal layer and the third metal layer; and a capacitive medium is arranged between the second gate metal layer and the fourth field plate layer, so that the second gate metal layer, the fourth field plate layer and the capacitive medium between the second gate metal layer and the fourth field plate layer form a sixth coupling capacitance.

In an alternative embodiment of the present application, the coupling capacitance module includes: the third top metal layer is positioned above the MIM capacitor and is connected with the upper polar plate of the MIM capacitor through a tenth conductive through hole; the fourth metal layer is positioned below the MIM capacitor; a fifth metal layer is arranged in the fourth metal layer, the fifth metal layer is positioned in an area of the fourth metal layer hollowed out along the thickness direction, and the fifth metal layer and the fourth metal layer are separated by a gap; the fifth metal layer is connected with the lower polar plate of the MIM capacitor through an eleventh conductive through hole; the fourth metal layer is connected with the third top metal layer through a third conductive structure, and a capacitance medium is arranged between the fourth metal layer and the lower polar plate of the MIM capacitor, so that the seventh coupling capacitor is formed by the fourth metal layer, the lower polar plate and the capacitance medium between the fourth metal layer and the lower polar plate; a fifth field plate layer located below the fourth metal layer; the fifth field plate layer is connected with the fourth metal layer through a twelfth conductive through hole; the sixth field plate layer is positioned below the fifth field plate layer; the sixth field plate layer is connected with the fifth metal layer through a thirteenth conductive through hole; a capacitive medium is arranged between the sixth field plate layer and the fifth field plate layer, so that the fifth field plate layer, the sixth field plate layer and the capacitive medium between the fifth field plate layer and the sixth field plate layer form an eighth coupling capacitor; a seventh field plate layer positioned below the sixth field plate layer; the seventh field plate layer is connected with the fourth metal layer through a fourteenth conductive through hole; a capacitive medium is arranged between the seventh field plate layer and the sixth field plate layer, so that the sixth field plate layer, the seventh field plate layer and the capacitive medium between the sixth field plate layer and the seventh field plate layer form a ninth coupling capacitor; a third gate metal layer located below the seventh field plate layer; the sixth field plate layer and the seventh field plate layer are hollowed in the thickness direction to form a sixth cavity and a seventh cavity respectively, and a fifteenth conductive through hole penetrates through the sixth cavity and the seventh cavity to connect the third grid metal layer and the fifth metal layer; a capacitive medium is disposed between the third gate metal layer and the seventh field plate layer, such that the third gate metal layer, the seventh field plate layer, and the capacitive medium therebetween form a tenth coupling capacitance.

In an alternative embodiment of the present application, the coupling capacitance module includes:

the fourth top metal layer is positioned above the MIM capacitor and is connected with the upper polar plate of the MIM capacitor through a sixteenth conductive through hole; the sixth metal layer is positioned below the MIM capacitor; a seventh metal layer is arranged in the sixth metal layer, the seventh metal layer is positioned in an area of the sixth metal layer hollowed out in the thickness direction, and the seventh metal layer is separated from the sixth metal layer by a gap; the seventh metal layer is connected with the lower polar plate of the MIM capacitor through a seventeenth conductive through hole; the sixth metal layer is connected with the fourth top metal layer through a fourth conductive structure, and a capacitance medium is arranged between the sixth metal layer and the lower polar plate of the MIM capacitor, so that the eleventh coupling capacitor is formed by the sixth metal layer, the lower polar plate and the capacitance medium between the sixth metal layer and the lower polar plate; an eighth field plate layer located below the sixth metal layer; the eighth field plate layer is connected with the seventh metal layer through an eighteenth conductive through hole; and a capacitive medium is arranged between the eighth field plate layer and the sixth metal layer, so that the eighth field plate layer, the sixth metal layer and the capacitive medium between the eighth field plate layer and the sixth metal layer form a twelfth coupling capacitance.

According to a second aspect of embodiments of the present application, there is provided an integrated circuit comprising a substrate; an epitaxial layer disposed on the substrate; the capacitor is arranged on the epitaxial layer.

In an alternative embodiment of the present application, a field oxide layer is also provided between the capacitor and the epitaxial layer.

In an alternative embodiment of the present application, the integrated circuit further comprises: an LDMOS device; the LDMOS device comprises at least one metal field plate; at least one polar plate in the coupling capacitance module of the capacitor is made by using a mask for manufacturing a metal field plate.

By adopting the technical scheme, the embodiment of the application has the following technical effects:

by forming a coupling capacitance and connecting the coupling capacitance in parallel with the MIM capacitance, the capacitance density of the capacitor is improved. The multi-layer metal field plate is a general design of a plurality of LDMOS devices, and because each polar plate of each coupling capacitor is positioned at different heights in the thickness direction of the MIM capacitor, the polar plate of the coupling capacitor can be manufactured by using a mask used for manufacturing the metal field plate of the LDMOS device, and the capacitance density can be improved on the premise of not increasing the mask of the device. Thus, the present application is easy to obtain a capacitor with a higher capacitance density at a lower cost.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 is a schematic diagram of a capacitor in a conventional MMIC;

FIG. 2 is a schematic diagram of a first capacitor applied in MMIC according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a second capacitor applied in MMIC according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a third capacitor applied in MMIC according to an embodiment of the present application;

fig. 5 is a schematic diagram of a fourth capacitor applied in MMIC according to an embodiment of the present application;

FIG. 6 is a schematic diagram of conductive vias at a third field plate layer and a fourth field plate layer provided in an embodiment of the present application;

FIG. 7 is a flow chart of a method for fabricating a capacitor according to an embodiment of the present disclosure;

FIG. 8 is a flow chart of another method for fabricating a capacitor according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a structure obtained by executing step S201 in the method corresponding to fig. 8 according to the embodiment of the present application;

fig. 10 is a schematic diagram of a structure obtained by executing step S202 in the method corresponding to fig. 8 according to the embodiment of the present application;

fig. 11 is a schematic diagram of a structure obtained by executing step S203 in the method corresponding to fig. 8 according to the embodiment of the present application.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is given with reference to the accompanying drawings, and it is apparent that the described embodiments are only some of the embodiments of the present application and not exhaustive of all the embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.

A conventional MIM capacitor is typically formed of two layers of metal plates and an insulating medium between the metal plates, and when the MMIC chip integrates the MIM capacitor, as shown in fig. 1, a first metal plate 1034 of the MIM capacitor is connected to a top metal 1036 through a top metal via 1035. A SiN dielectric layer 1033 is between the first metal plate 1034 and the second metal plate 1032 of the MIM capacitor. The second metal plate 1032 of the MIM capacitor is connected to metal layer 1031 by a conductive via. The metal layer 1031 is connected to the low-resistance substrate 1039 through a connection via 1037, wherein the connection via 1037 is connected to the low-resistance substrate 1039 through an epitaxial layer 1038 on the low-resistance substrate 1039. The capacitance of the MIM capacitor is limited by the thickness and material of the insulating medium, so that the capacitance density of the MIM capacitor is difficult to be increased without changing the withstand voltage and the material, and the cost is often increased to increase the capacitance density of the MIM capacitor. How to realize low cost and increase capacitance density of the capacitor, thereby reducing the area of the MMIC chip is a difficult problem in the field of semiconductors.

Based on this, the present application improves the capacitor to easily obtain a capacitor having a higher capacitance density at a lower cost.

Embodiment one:

a capacitor of an embodiment of the present application includes: MIM capacitor and coupling capacitor module. The coupling capacitor module comprises at least one coupling capacitor, and each coupling capacitor is respectively connected with the MIM capacitor in parallel; the plates of each coupling capacitor are at different heights in the thickness direction of the MIM capacitor.

By adopting the capacitor provided by the embodiment of the application, the capacitance density of the capacitor is improved by forming the coupling capacitor and enabling the coupling capacitor to be connected with the MIM capacitor in parallel. The multi-layer metal field plate is a general design of a plurality of LDMOS devices, and because each polar plate of each coupling capacitor is positioned at different heights in the thickness direction of the MIM capacitor, the polar plate of the coupling capacitor can be manufactured by using a mask used for manufacturing the metal field plate of the LDMOS device, and the capacitance density can be improved on the premise of not increasing the mask of the device. Thus, the embodiments of the present application facilitate obtaining capacitors with higher capacitance densities at lower cost.

Further, each of the coupling capacitor and the MIM capacitor is at a different height in a MIM capacitor thickness direction, respectively. Because the coupling capacitor and the MIM capacitor are in different layers, when the capacitor is arranged on the MMIC, the coupling capacitor is easy to be arranged below the MIM capacitor. The more the coupling capacitance is concentrated below the MIM capacitance, the more the MMIC chip area is not enlarged, so that the capacitance density of the capacitance is improved, and the MMIC chip area is convenient to have smaller design space.

Further, the coupling capacitance module includes: at least one metal layer and at least one field plate layer, the at least one field plate layer and the one metal layer forming a coupling capacitance.

Further, a metal layer closest to the MIM capacitor forms a coupling capacitor with a plate of the MIM capacitor.

Further, in the case of a multilayer field plate layer, adjacent field plate layers form a coupling capacitance.

Further, the coupling capacitance module further includes: and the gate metal layer, a field plate layer nearest to the gate metal layer and the gate metal layer form a coupling capacitor.

Optionally, the coupling capacitor module comprises a metal layer and a field plate layer; the metal layer and the polar plate of the MIM capacitor form a coupling capacitor; the field plate layer and the metal layer form a coupling capacitance.

Optionally, the coupling capacitor module includes a metal layer, two field plate layers and a gate metal layer; the metal layer and the polar plate of the MIM capacitor form a coupling capacitor; the field plate layer nearest to the metal layer and the metal layer form a coupling capacitor; the two field plate layers form a coupling capacitor; the field plate layer closest to the gate metal layer and the gate metal layer form a coupling capacitance.

Optionally, the coupling capacitor module comprises two field plate layers and a gate metal layer; the two field plate layers form a coupling capacitor; the field plate layer closest to the gate metal layer and the gate metal layer form a coupling capacitance.

Optionally, the coupling capacitor module includes a metal layer, three field plate layers and a gate metal layer; the metal layer and the polar plate of the MIM capacitor form a coupling capacitor; the field plate layer nearest to the metal layer and the metal layer form a coupling capacitor; two adjacent field plate layers respectively form coupling capacitors; the field plate layer closest to the gate metal layer and the gate metal layer form a coupling capacitance.

In order to save the cost and to match the manufacturing process of the MMIC devices of different types, the coupling capacitor module can have various embodiments.

The first embodiment of the coupling capacitor module is as follows:

in some embodiments, the coupling capacitance module comprises: the first top metal layer, the first metal layer, the second metal layer, the first field plate layer, the second field plate layer and the first gate metal layer. The first metal layer and the lower polar plate of the MIM capacitor form a pair of polar plates of a first coupling capacitor, the first field plate layer and the first metal layer form a pair of polar plates of a second coupling capacitor, the first field plate layer and the second field plate layer form a pair of polar plates of a third coupling capacitor, and the first gate metal layer and the second field plate layer form a pair of polar plates of a fourth coupling capacitor. The four pairs of polar plates are respectively provided with capacitance mediums, and the four pairs of polar plates and the capacitance mediums in the polar plates form four pairs of coupling capacitances. As shown in fig. 2, the capacitors provided on the MMIC are formed on the first substrate 210, and the capacitors are sequentially provided with a MIM capacitor, a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, and a fourth coupling capacitor from top to bottom. The MIM capacitor includes an upper plate 219, a dielectric layer 218, and a lower plate 217, which are stacked from top to bottom. The first top metal layer 201 is located above the MIM capacitor, and the first top metal layer 201 is connected to the top plate 219 of the MIM capacitor through the first conductive via 220. The first metal layer 205 is located under the MIM capacitor. The second metal layer 221 is disposed in the first metal layer 205, the second metal layer 221 is disposed in a region hollowed out in the thickness direction of the first metal layer 205, and the second metal layer 221 is separated from the first metal layer 205 by a gap. The second metal layer 221 is connected to the bottom plate 217 of the MIM capacitor through a second conductive via 216. The first metal layer 205 is connected to the first top metal layer 201 through a first conductive structure, and a capacitance medium is disposed between the first metal layer 205 and the lower plate 217 of the MIM capacitor, so that the first metal layer 205, the lower plate 217, and the capacitance medium therebetween form a first coupling capacitor. The first field plate layer 215 is located below the first metal layer 205; the first field plate layer 215 is connected to the second metal layer 221 through the third conductive via 211; a capacitive medium is disposed between the first field plate layer 215 and the first metal layer 205 such that the first field plate layer 215, the first metal layer 205, and the capacitive medium therebetween form a second coupling capacitance. The second field plate layer 207 is located below the first field plate layer 215; the second field plate layer 207 is connected to the first metal layer 205 through a fourth conductive via 206. A capacitive medium is arranged between the second field plate layer 207 and the first field plate layer 215 such that the first field plate layer 215, the second field plate layer 207 and the capacitive medium therebetween form a third coupling capacitance. A first gate metal layer 208 is located below the second field plate layer 207. The first field plate layer 215 and the second field plate layer 207 are hollowed out in the thickness direction to form a first cavity and a second cavity, respectively, and the fifth conductive via 212 passes through the first cavity and the second cavity to connect the first gate metal layer 208 and the second metal layer 221. A capacitive medium is arranged between the first gate metal layer 208 and the second field plate layer 207, such that the first gate metal layer 208, the second field plate layer 207 and the capacitive medium therebetween form a fourth coupling capacitance. The first conductive structure includes a first metal via 204, a first metal connection layer 203, and a second metal via 202. The first metal layer 205 is connected to the first metal connection layer 203 through the first metal via 204, and the first metal connection layer 203 is connected to the first top metal layer 201 through the second metal via 202. One side of the first gate metal layer 208, which faces away from the MIM capacitor, is disposed on the first substrate 210 through the first field oxide layer 209 and the first epitaxial layer 213 in sequence. These capacitor dielectric, conductive vias, conductor structures and metal vias also serve as connection supports in the capacitor, such that the MIM capacitor and the respective coupling capacitors form an integral capacitor. Alternatively, the second metal layer 221 is connected to the first substrate 210 through the first through-ground via 214. Optionally, the first substrate 210 is a low resistance substrate. Optionally, the upper plate 219 of the MIM capacitor is connected to high voltage via the first top metal layer 201 and the lower plate 217 of the MIM capacitor is connected to low voltage. Alternatively, there are a plurality of areas hollowed out in the thickness direction in the first metal layer 205, and second metal layers 221 are respectively disposed in these areas, and any one or more of the second metal layers 221 is connected to the first substrate through a first through-hole 214, and the first through-hole 214 protrudes into the first substrate 210. The first metal connection layer 203 and the lower plate 217 of the MIM capacitor are formed by the same mask, and the first metal layer 205 and the second metal layer 221 are formed by the same mask.

Alternatively, the structure shown in fig. 2 may be a repeatedly stackable periodic structure, for example, a structure in which the structure shown in fig. 2 is horizontally rotated leftward along the first through-holes to the ground is provided on the left side of the structure shown in fig. 2, or a structure in which the structure shown in fig. 2 is horizontally rotated rightward along the first conductor is provided on the right side of the structure shown in fig. 2.

Multilayer metal field plates are a common design for many LDMOS devices, optionally with the plates of the coupling capacitor being fabricated using masks used to fabricate the metal field plates in the LDMOS device. The capacitor of the embodiment is suitable for being applied to MMICs integrated with LDMOS devices of double-layer field plate structures. When the capacitor is manufactured on the MMIC, a Mask (Mask) for manufacturing a metal field plate in the double-layer field plate structure LDMOS device is conveniently used for manufacturing a field plate layer of the coupling capacitor, and the field plate layer is used as a polar plate of the coupling capacitor, namely the first field plate layer and the second field plate layer of the embodiment. Therefore, the capacitance density can be effectively improved on the premise of not increasing the Mask and the area of the MMIC device. The above embodiments utilize field plate-gate metal layers, field plate-field plate, field plate-metal layers, and metal layer-metal layer coupling capacitances to greatly increase capacitance per unit area. The second metal layer is downwards perforated, so that the junction resistance of the thin metal first field plate layer and the grid metal layer is reduced, and the Q value of the capacitor is improved. And because the first field plate layer is raised by the field oxide layer, the first field plate layer is closer to the first metal layer, and the capacitance density is further improved.

Table 1 is a simulated comparison of a capacitor having a three-layer metal two-layer field plate structure with MIM capacitance, as shown in table 1, having a capacitance density of 981pF/mm2 and a capacitance density of 225.9pF/mm2, the capacitance density of the capacitor having a three-layer metal two-layer field plate structure being significantly higher than that of the MIM capacitance.

	Capacitance Density @2GHz (pF/mm 2)
		MIM capacitor	225.9
Three-layer metal two-layer field plate capacitor	981

Table 1 simulation comparing capacitor with MIM capacitor with three-layer metal two-layer field plate structure coupling capacitor module embodiment two:

in some embodiments, the coupling capacitance module comprises: a second top metal layer, a third field plate layer, a fourth field plate layer, and a second gate metal layer. Wherein the third field plate layer and the fourth field plate layer form a pair of plates of a fifth coupling capacitance, and the second gate metal layer and the fourth field plate layer form a pair of plates of a sixth coupling capacitance. Capacitive media are respectively arranged in the two pairs of polar plates, and the two pairs of polar plates and the capacitive media in the polar plates form two pairs of coupling capacitors. As shown in fig. 3, a capacitor provided on the MMIC is formed on the second substrate 310, and the capacitor is provided with a MIM capacitor, a fifth coupling capacitor, and a sixth coupling capacitor in this order from top to bottom. The MIM capacitor includes an upper plate 319, a dielectric layer 318, and a lower plate 317, arranged in a top-to-bottom stack. The second top metal layer 301 is located over the MIM capacitor, and the second top metal layer 301 is connected to the top plate 319 of the MIM capacitor by a sixth conductive via 320. Third metal layer 316 is located under the MIM capacitor. The third metal layer 316 is connected to the bottom plate 317 of the MIM capacitor by a seventh conductive via 321. The third field plate layer 315 is located below the third metal layer 316, and the third field plate layer 315 is connected to the third metal layer 316 through an eighth conductive via 311. The fourth field plate layer 307 is located below the third field plate layer 315. The fourth field plate layer 307 is connected to the second top metal layer 301 by a second conductive structure. A capacitive medium is arranged between the fourth field plate layer 307 and the third field plate layer 315, such that the third field plate layer 315, the fourth field plate 307 layer and the capacitive medium therebetween form a fifth coupling capacitance. The second gate metal layer 308 is located below the fourth field plate layer 307. The third field plate layer 315 and the fourth field plate layer 307 are hollowed out in the thickness direction to form a third cavity and a fourth cavity, respectively, and the ninth conductive via 312 passes through the third cavity and the fourth cavity to connect the second gate metal layer 308 and the third metal layer 316. A capacitive medium is arranged between the second gate metal layer 308 and the fourth field plate layer 307 such that the second gate metal layer 308, the fourth field plate layer 307 and the capacitive medium therebetween form a sixth coupling capacitance. The second conductive structure includes a third metal via 306, a second metal connection layer 305, a fourth metal via 304, a third metal connection layer 303, and a fifth metal via 302. The fourth field plate layer 307 is connected to the second metal connection layer 305 through a third metal via 306, the second metal connection layer 305 is connected to the third metal connection layer 303 through a fourth metal via 304, and the third metal connection layer 303 is connected to the second top metal layer 301 through a fifth metal via 302. One side of the second gate metal layer 308 facing away from the MIM capacitor is disposed on the second substrate 310 sequentially through the second field oxide layer 309 and the second epitaxial layer 313. These capacitor dielectric, conductive vias, conductor structures and metal vias also serve as connection supports in the capacitor, such that the MIM capacitor and the respective coupling capacitors form an integral capacitor. Optionally, the third metal layer 316 is connected to the second substrate 310 through a second through-to-ground via 314. Optionally, the second substrate 310 is a low resistance substrate. Optionally, the upper plate 319 of the MIM capacitor is connected to high voltage via the second top metal layer 301 and the lower plate 317 of the MIM capacitor is connected to low voltage. The third metal connection layer 303 and the bottom plate 317 of the MIM capacitor are formed by the same mask, and the second metal connection layer 305 and the third metal layer 316 are formed by the same mask.

Alternatively, the structure shown in fig. 3 may be a repeatedly stackable periodic structure, such as a structure in which the structure shown in fig. 3 is horizontally rotated leftward along the second through hole to the ground on the left side of the structure shown in fig. 3, or a structure in which the structure shown in fig. 3 is horizontally rotated rightward along the second conductor structure on the right side of the structure shown in fig. 3.

Multilayer metal field plates are a common design for many LDMOS devices, optionally with the plates of the coupling capacitor being fabricated using masks used to fabricate the metal field plates in the LDMOS device. The capacitor of the embodiment is suitable for being applied to MMICs integrated with LDMOS devices of double-layer field plate structures. When the capacitor is manufactured on the MMIC, a Mask (Mask) for manufacturing a metal field plate in the double-layer field plate structure LDMOS device is conveniently used for manufacturing a field plate layer of the coupling capacitor, and the field plate layer is used as a polar plate of the coupling capacitor, namely a third field plate layer and a fourth field plate layer in the embodiment. Therefore, the capacitance density can be effectively improved on the premise of not increasing the Mask and the area of the MMIC device. In the embodiment, the capacitance density is improved by using the field plate-gate metal layer and the field plate-field plate coupling capacitance, compared with the coupling capacitance module embodiment, the field plate-metal layer and the metal layer-metal layer coupling capacitance are sacrificed, but the third metal layer is not hollowed out, so that the area is larger, more connecting through holes can be arranged to the third field plate layer, the contact resistance of the thin metal third field plate layer can be reduced, and the capacitance Q value is further improved.

The third metal layer is connected with the third field plate layer through the eighth conductive through hole, and the third metal layer is connected with the second grid metal layer through the ninth conductive through hole to strengthen the connection of thin-layer metal, so that the Q value of the device is improved on the basis of slightly sacrificing the capacitance density. As shown in fig. 6, a hollowed structure is designed in the layout structure of the third field plate layer 315 and the fourth field plate layer 307, and in one contact structure, the connection and disconnection of the gate metal layer and the third field plate layer can be simultaneously realized, the eighth conductive through hole 311 is formed on the third field plate layer 315, four ninth conductive through holes 312 enclosed by the eighth conductive through hole 311 are formed on the second gate metal layer 308, and the ninth conductive through holes 312 are not connected with the fourth field plate layer 307 and the third field plate layer 315.

Coupling capacitor module embodiment III:

in some embodiments, the coupling capacitance module comprises: a third top metal layer, a fourth metal layer, a fifth field plate layer, a sixth field plate layer, a seventh field plate layer, and a third gate metal layer. The fourth metal layer and the lower polar plate of the MIM capacitor form a pair of polar plates of a seventh coupling capacitor, the fifth field plate layer and the sixth field plate layer form a pair of polar plates of an eighth coupling capacitor, the sixth field plate layer and the seventh field plate layer form a pair of polar plates of a ninth coupling capacitor, and the third gate metal layer and the seventh field plate layer form a pair of polar plates of the tenth coupling capacitor. The four pairs of polar plates are respectively provided with capacitance mediums, and the four pairs of polar plates and the capacitance mediums in the polar plates form four pairs of coupling capacitances. As shown in fig. 4, a capacitor provided on the MMIC is formed on the third substrate 411, and the capacitor is provided with a MIM capacitor, a seventh coupling capacitor, an eighth coupling capacitor, a ninth coupling capacitor, and a tenth coupling capacitor in this order from top to bottom. The MIM capacitor includes an upper plate 420, a dielectric layer 419, and a lower plate 423 in a top-down stack arrangement. The third top metal layer 401 is located above the MIM capacitor, and the third top metal layer 401 is connected to the top plate 420 of the MIM capacitor through a tenth conductive via 421. A fourth metal layer 405 is located under the MIM capacitor. A fifth metal layer 418 is disposed in the fourth metal layer 405, the fifth metal layer 418 is located in a region hollowed out in the thickness direction of the fourth metal layer 405, and the fifth metal layer 418 and the fourth metal layer 405 are separated by a gap. The fifth metal layer 418 is connected to the lower plate 423 of the MIM capacitor through an eleventh conductive via 422. The fourth metal layer 405 is connected to the third top metal layer 401 through a third conductive structure, and a capacitance medium is disposed between the fourth metal layer 405 and the lower plate 423 of the MIM capacitor, so that the fourth metal layer 405, the lower plate 423, and the capacitance medium therebetween form a seventh coupling capacitor. A fifth field plate layer 417 is located below the fourth metal layer 405, the fifth field plate layer 417 being connected to the fourth metal layer 405 by a twelfth conductive via 412. A sixth field plate layer 416 is located below the fifth field plate layer 417, the sixth field plate layer 416 being connected to the fifth metal layer by a thirteenth conductive via 413. A capacitive medium is disposed between the sixth field plate layer 416 and the fifth field plate layer 417 such that the fifth field plate layer 417, the sixth field plate layer 416, and the capacitive medium therebetween form an eighth coupling capacitance. Seventh field plate layer 407 is located below sixth field plate layer 416. The seventh field plate layer 407 is connected to the fourth metal layer 405 through a fourteenth conductive via 406. A capacitive medium is disposed between seventh field plate layer 407 and sixth field plate layer 416 such that sixth field plate layer 416, seventh field plate layer 407, and the capacitive medium therebetween form a ninth coupling capacitance. A third gate metal layer 408 is located under the seventh field plate layer 407. The sixth field plate layer 416 and the seventh field plate layer 407 are hollowed out in the thickness direction to form a sixth cavity and a seventh cavity, respectively, and the fifteenth conductive via 414 passes through the sixth cavity and the seventh cavity to connect the third gate metal layer 408 and the fifth metal layer 418. A capacitive medium is disposed between the third gate metal layer 408 and the seventh field plate layer 407 such that the third gate metal layer 408, the seventh field plate layer 407, and the capacitive medium therebetween form a tenth coupling capacitance. Wherein the third conductive structure includes a sixth metal via 404, a fourth metal connection layer 403, and a seventh metal via 402. The fourth metal layer 405 is connected to the fourth metal connection layer 403 through a sixth metal via 404, and the fourth metal connection layer 403 is connected to the third top metal layer 401 through a seventh metal via 402. The third gate metal layer 408 is disposed on the third substrate 411, opposite to the MIM capacitor, sequentially through the third field oxide layer 409 and the third epitaxial layer 410. These capacitor dielectric, conductive vias, conductor structures and metal vias also serve as connection supports in the capacitor, such that the MIM capacitor and the respective coupling capacitors form an integral capacitor. Alternatively, the fifth metal layer 418 is connected to the third substrate 411 through a third through-ground via 415. Alternatively, the third substrate 411 is a low-resistance substrate. Optionally, the upper plate of the MIM capacitor is connected to high voltage via the third top metal layer 401 and the lower plate 423 of the MIM capacitor is connected to low voltage. Optionally, there are a plurality of areas hollowed out in the thickness direction in the fourth metal layer 405, in which fifth metal layers 418 are respectively provided, and any one or more of the fifth metal layers 418 are connected to the third substrate 411 through third through-holes 415, and the third through-holes 415 protrude into the third substrate 411. The fourth metal connection layer 403 and the lower plate 423 of the MIM capacitor are formed by the same mask, and the fourth metal layer 405 and the fifth metal layer 418 are formed by the same mask.

Alternatively, the structure shown in fig. 4 may be a repeatedly stackable periodic structure, such as a structure in which the structure shown in fig. 4 is horizontally rotated leftward along the third through-hole to the ground on the left side of the structure shown in fig. 4, or a structure in which the structure shown in fig. 4 is horizontally rotated rightward along the third conductor structure on the right side of the structure shown in fig. 2.

The capacitor of the embodiment is suitable for being applied to MMICs integrated with three-layer field plate structure LDMOS devices. When the capacitor is manufactured on the MMIC, a Mask (Mask) for manufacturing a metal field plate in the three-layer field plate structure LDMOS device is conveniently used for manufacturing a field plate layer of the coupling capacitor, and the field plate layer is used as a polar plate of the coupling capacitor, namely a fifth field plate layer, a sixth field plate layer and a seventh field plate layer. Therefore, the capacitance density can be effectively improved on the premise of not increasing the Mask and the area of the MMIC device. In the above embodiment, the thickness of the dielectric layer between the fifth field plate layer and the sixth field plate layer is thinner, which is far greater than the capacitance density of the distance between the fourth metal layer and the sixth field plate layer, so the capacitance density of the embodiment is higher than that of the first and second embodiments of the coupling capacitor module, but the Q value is reduced than that of the first embodiment because the fifth field plate layer also belongs to the thin metal layer and has a larger resistance.

A coupling capacitance module embodiment IV:

in some embodiments, the coupling capacitance module comprises: a fourth top metal layer, a sixth metal layer, a seventh metal layer and an eighth field plate layer. The sixth metal layer and the lower electrode plate of the MIM capacitor form a pair of electrode plates of an eleventh coupling capacitor, and the eighth field plate layer and the sixth metal layer form a pair of electrode plates of a twelfth coupling capacitor. Capacitive media are respectively arranged in the two pairs of polar plates, and the two pairs of polar plates and the capacitive media in the polar plates form two pairs of coupling capacitors. As shown in fig. 5, a capacitor provided on the MMIC is formed on the fourth substrate 509, and the capacitor is provided with a MIM capacitor, an eleventh coupling capacitor, and a twelfth coupling capacitor in this order from top to bottom. The MIM capacitor includes an upper plate 515, a dielectric layer 514, and a lower plate 513, stacked from top to bottom. The fourth top metal layer 501 is located over the MIM capacitor, and the fourth top metal layer 501 is connected to the top plate 515 of the MIM capacitor by a sixteenth conductive via 516. The sixth metal layer 505 is located under the MIM capacitor. A seventh metal layer 512 is provided in the sixth metal layer 505, the seventh metal layer 512 is located in a region where the sixth metal layer 505 is hollowed out in the thickness direction, and a gap is formed between the seventh metal layer 512 and the sixth metal layer 505. The seventh metal layer 512 is connected to the bottom plate 513 of the MIM capacitor through a seventeenth conductive via 517. The sixth metal layer 505 is connected to the fourth top metal layer 501 through a fourth conductive structure. A capacitance medium is disposed between the sixth metal layer 505 and the lower plate 513 of the MIM capacitor, such that the sixth metal layer 505, the lower plate 513, and the capacitance medium therebetween form an eleventh coupling capacitance. An eighth field plate layer 511 is located below the sixth metal layer 505. The eighth field plate layer 511 is connected to the seventh metal layer 512 through an eighteenth conductive via 506. A capacitive medium is disposed between the eighth field plate layer 511 and the sixth metal layer 505, such that the eighth field plate layer 511, the sixth metal layer 505, and the capacitive medium therebetween form a twelfth coupling capacitance. Wherein the fourth conductive structure includes an eighth metal via 504, a fifth metal connection layer 503, and a ninth metal via 502. The sixth metal layer 505 connects the fifth metal connection layer 503 through the eighth metal via 504, and the fifth metal connection layer 503 connects the fourth top metal layer 501 through the ninth metal via 502. The side of the fourth gate metal layer 501 facing away from the MIM capacitor is disposed on a fourth substrate 509 sequentially through a fourth field oxide layer 507 and a fourth epitaxial layer 508. These capacitor dielectric, conductive vias, conductor structures and metal vias also serve as connection supports in the capacitor, such that the MIM capacitor and the respective coupling capacitors form an integral capacitor. Optionally, the seventh metal layer 512 is connected to the fourth substrate 509 through a fourth to ground via 510. Optionally, the fourth substrate 509 is a low-resistance substrate. Optionally, the upper plate 515 of the MIM capacitor is connected to high voltage via the fourth top metal layer 501 and the lower plate 513 of the MIM capacitor is connected to low voltage. Optionally, there are a plurality of areas hollowed out in the thickness direction in the sixth metal layer 505, in which seventh metal layers 512 are respectively provided, and any one or more of the seventh metal layers 512 are connected to the fourth substrate 509 through fourth through-holes 510, and the fourth through-holes 510 extend into the fourth substrate 509. The fifth metal connection layer 503 and the lower electrode 513 of the MIM capacitor are formed by the same mask, and the sixth metal layer 505 and the seventh metal layer 512 are formed by the same mask.

Alternatively, the structure shown in fig. 5 may be a repeatedly stackable periodic structure, such as a structure in which the structure shown in fig. 5 is horizontally rotated leftward along the fourth through-hole to the ground on the left side of the structure shown in fig. 5, or a structure in which the structure shown in fig. 5 is horizontally rotated rightward along the fourth conductor structure on the right side of the structure shown in fig. 5.

The capacitor of the embodiment is suitable for being applied to MMICs integrated with single-layer field plate structure LDMOS devices. When the capacitor is manufactured on the MMIC, a Mask (Mask) for manufacturing a metal field plate in the single-layer field plate structure LDMOS device is conveniently used for manufacturing a field plate layer of the coupling capacitor, and the field plate layer is used as a polar plate of the coupling capacitor, namely the eighth field plate layer in the embodiment. Therefore, the capacitance density can be effectively improved on the premise of not increasing the Mask and the area of the MMIC device. Compared with the first, second and third embodiments of the coupling capacitor module, the capacitance density of the embodiment of the coupling capacitor module is slightly lower, but the embodiment of the invention can be compatible with the LDMOS technology only with a single-layer field plate to improve the capacitance density of the capacitor.

In some embodiments, the dielectric layer of the MIM capacitor is a SiN dielectric layer.

In some embodiments, each capacitive medium in the coupling capacitance module is an oxide layer. For example, siO ₂ 。

In some embodiments, each gate metal layer in the coupling capacitance module is a metal silicide formed on the gate.

In some embodiments, the plates of the coupling capacitance are fabricated using a mask used to fabricate the metal plates or gate metal layers in the LDMOS device.

Illustratively, for a MIM capacitance of 1700A SiN dielectric, the theoretical capacitance density can be calculated by the parallel plate capacitor equation: about 400pF/mm2, a gate metal silicide-field plate coupling capacitance of 800A thickness of oxide dielectric (SiO 2) can reach about 400pF/mm2, and a field plate 1-field plate 2 coupling capacitance of 1300A thickness of oxide dielectric (SiO 2) can reach about 270pF/mm2, so that the capacitance density can be doubled by using a metal field plate as a polar plate. Besides the capacitance of the field plate-field plate, the capacitance between the field plate-metal, the metal-metal and the field plate-metal silicide can be further increased in capacitance density.

Embodiment two:

the embodiment of the application provides an integrated circuit, which comprises a substrate, an epitaxial layer and the capacitor. An epitaxial layer is disposed on the substrate, and a capacitor is disposed on the epitaxial layer.

Further, a field oxide layer is also arranged between the capacitor and the epitaxial layer. The use of field oxide layer LOCOS can raise the overall structure of the field plate layer, thereby increasing the capacitance density.

Further, the integrated circuit further comprises an LDMOS device. The LDMOS device comprises at least one metal field plate. At least one polar plate in the coupling capacitance module of the capacitor is made by using a mask for manufacturing a metal field plate.

Illustratively, the integrated circuit is a monolithic microwave integrated circuit having the LDMOS device, MIM capacitor and coupling capacitor module integrated thereon.

Embodiment III:

as shown in fig. 7, an embodiment of the present application provides a method for manufacturing a capacitor, including the steps of:

and S101, forming a coupling capacitor module comprising at least one coupling capacitor.

S102, forming MIM capacitors on the coupling capacitor modules, so that each coupling capacitor is respectively connected with the MIM capacitors in parallel; the plates of each coupling capacitor are at different heights in the thickness direction of the MIM capacitor.

Illustratively, the coupling capacitor module corresponding to the first embodiment of the coupling capacitor module, as shown in fig. 8, is manufactured by the following steps:

and S201, forming a first field oxide layer on the first epitaxial layer on the first substrate, depositing and etching a grid electrode on the first field oxide layer, and depositing and etching a metal silicide on the grid electrode. The structure obtained in step S201 includes, as shown in fig. 9, a first gate metal layer 208, a first field oxide layer 209, a first epitaxial layer 213, and a first substrate 210, which are stacked in this order from top to bottom.

S202, forming a first field plate layer and a second field plate layer on the metal silicide, wherein capacitance media are arranged between the first field plate layer and the second field plate layer and between the second field plate layer and the metal silicide, and the capacitance media are silicon oxide. The structure obtained in step S202 is shown in fig. 10, where a second field plate layer 207 is disposed over the first gate metal layer 208 and a first field plate layer 215 is disposed over the second field plate layer 207. A silicon oxide dielectric is disposed between the second field plate layer 207 and the first gate metal layer 208, and a silicon oxide dielectric is also disposed between the first field plate layer 215 and the second field plate layer 207.

Step S203, forming a third conductive through hole, a fourth conductive through hole, a fifth conductive through hole and a first through hole to ground on the structure formed in step S202. The structure obtained in step S203 is as shown in fig. 11, the third conductive via 211 is disposed on the first field plate layer 215, the fourth conductive via 206 is disposed on the second field plate layer 207, the first field plate layer 215 and the second field plate layer 207 are hollowed out in the thickness direction to form a first cavity and a second cavity, and the fifth conductive via 212 is disposed on the first gate metal layer 208 through the first cavity and the second cavity.

Step S204, forming a metal layer and an MIM capacitor on the structure formed in step S203 to obtain the capacitor shown in FIG. 2.

Specifically, step S204 includes:

and forming a first metal layer and a second metal layer on the third conductive through hole, the fourth conductive through hole, the fifth conductive through hole and the first through hole to the ground, wherein the second metal layer is arranged in the first metal layer, and is positioned in a hollowed-out area of the first metal layer along the thickness direction, and the second metal layer is separated from the first metal layer by a gap. The first field plate layer is connected with the second metal layer through a third conductive through hole; the second field plate layer is connected with the first metal layer through a fourth conductive through hole. A fifth conductive via connects the first gate metal layer and the second metal layer through the first cavity and the second cavity. A second conductive via is disposed on the second metal layer, and a first metal via is disposed on the first metal layer. And setting MIM capacitor above the second conductive through hole and setting the first metal connecting layer above the first metal through hole. The second conductive through hole is connected with the lower polar plate of the MIM capacitor. And a first conductive through hole is arranged on the upper polar plate of the MIM capacitor, and a second metal through hole is arranged above the first metal connecting layer. And a first top metal layer is arranged above the first conductive through hole and is connected with the first metal connecting layer through the second metal through hole.

In the description of the present application and its embodiments, it should be understood that the terms "top," "bottom," "height," and the like indicate an orientation or positional relationship based on that shown in the drawings, and are merely for convenience of description and to simplify the description, rather than to indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application.

In this application and in its embodiments, the terms "disposed," "mounted," "connected," "secured," and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed, unless otherwise explicitly stated and defined as such; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

In this application and in its embodiments, unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different structures of the present application. The components and arrangements of specific examples are described above in order to simplify the disclosure of this application. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. A capacitor, comprising:

MIM capacitor;

the coupling capacitor module comprises at least one coupling capacitor, and each coupling capacitor is respectively connected with the MIM capacitor in parallel; the plates of each coupling capacitor are at different heights in the thickness direction of the MIM capacitor.

2. The capacitor of claim 1, wherein the coupling capacitance module comprises:

at least one metal layer and at least one field plate layer, the at least one field plate layer and the one metal layer forming a coupling capacitance.

3. The capacitor of claim 2, wherein a metal layer nearest to the MIM capacitor forms a coupling capacitance with a plate of the MIM capacitor.

4. A capacitor according to claim 2 or 3, wherein adjacent field plates, in the presence of multiple field plates, form a coupling capacitance.

5. The capacitor of claim 4, wherein the coupling capacitance module further comprises:

and the gate metal layer, a field plate layer nearest to the gate metal layer and the gate metal layer form a coupling capacitor.

6. A capacitor according to claim 3, wherein the coupling capacitance module comprises a metal layer and a field plate layer;

The metal layer and the polar plate of the MIM capacitor form a coupling capacitor; the field plate layer and the metal layer form a coupling capacitance.

7. The capacitor of claim 5, wherein the coupling capacitance module comprises a metal layer, two field plate layers, and a gate metal layer;

the metal layer and the polar plate of the MIM capacitor form a coupling capacitor;

the field plate layer nearest to the metal layer and the metal layer form a coupling capacitor;

the two field plate layers form a coupling capacitor;

the field plate layer closest to the gate metal layer and the gate metal layer form a coupling capacitance.

8. The capacitor of claim 5, wherein the coupling capacitance module comprises two field plate layers and one gate metal layer;

the two field plate layers form a coupling capacitor;

9. The capacitor of claim 5, wherein the coupling capacitance module comprises a metal layer, three field plate layers, and a gate metal layer;

Two adjacent field plate layers respectively form coupling capacitors;

10. The capacitor of claim 6, wherein the coupling capacitance module comprises:

the fourth top metal layer is positioned above the MIM capacitor and is connected with the upper polar plate of the MIM capacitor through a sixteenth conductive through hole;

a sixth metal layer positioned below the MIM capacitor; a seventh metal layer is arranged in the sixth metal layer, the seventh metal layer is positioned in a hollowed-out area of the sixth metal layer along the thickness direction, and the seventh metal layer and the sixth metal layer are separated by a gap; the seventh metal layer is connected with the lower polar plate of the MIM capacitor through a seventeenth conductive through hole; the sixth metal layer is connected with the fourth top metal layer through a fourth conductive structure, and a capacitance medium is arranged between the sixth metal layer and the lower polar plate of the MIM capacitor, so that the sixth metal layer, the lower polar plate and the capacitance medium between the sixth metal layer and the lower polar plate form an eleventh coupling capacitance;

an eighth field plate layer located below the sixth metal layer; the eighth field plate layer is connected with the seventh metal layer through an eighteenth conductive through hole; and a capacitive medium is arranged between the eighth field plate layer and the sixth metal layer, so that a twelfth coupling capacitance is formed by the eighth field plate layer, the sixth metal layer and the capacitive medium therebetween.

11. The capacitor of claim 7, wherein the coupling capacitance module comprises:

the first top metal layer is positioned above the MIM capacitor and is connected with the upper polar plate of the MIM capacitor through a first conductive through hole;

the first metal layer is positioned below the MIM capacitor; a second metal layer is arranged in the first metal layer, the second metal layer is positioned in an area of the first metal layer hollowed out in the thickness direction, and the second metal layer is separated from the first metal layer by a gap; the second metal layer is connected with the lower polar plate of the MIM capacitor through a second conductive through hole; the first metal layer is connected with the first top metal layer through a first conductive structure, and a capacitance medium is arranged between the first metal layer and the lower polar plate of the MIM capacitor, so that the first metal layer, the lower polar plate and the capacitance medium between the first metal layer and the lower polar plate form a first coupling capacitance;

a first field plate layer located below the first metal layer; the first field plate layer is connected with the second metal layer through a third conductive through hole; a capacitive medium is arranged between the first field plate layer and the first metal layer, so that the first field plate layer, the first metal layer and the capacitive medium between the first field plate layer and the first metal layer form a second coupling capacitor;

A second field plate layer located below the first field plate layer; the second field plate layer is connected with the first metal layer through a fourth conductive through hole; a capacitive medium is arranged between the second field plate layer and the first field plate layer, so that the first field plate layer, the second field plate layer and the capacitive medium between the first field plate layer and the second field plate layer form a third coupling capacitor;

a first gate metal layer located below the second field plate layer; the first field plate layer and the second field plate layer are hollowed in the thickness direction to form a first cavity and a second cavity respectively, and a fifth conductive through hole penetrates through the first cavity and the second cavity to connect the first grid metal layer and the second metal layer; and a capacitance medium is arranged between the first gate metal layer and the second field plate layer, so that the first gate metal layer, the second field plate layer and the capacitance medium between the first gate metal layer and the second field plate layer form a fourth coupling capacitance.

12. The capacitor of claim 8, wherein the coupling capacitance module comprises:

the second top metal layer is positioned above the MIM capacitor and is connected with the upper polar plate of the MIM capacitor through a sixth conductive through hole;

The third metal layer is positioned below the MIM capacitor; the third metal layer is connected with the lower polar plate of the MIM capacitor through a seventh conductive through hole;

a third field plate layer located below the third metal layer; the third field plate layer is connected with the third metal layer through an eighth conductive through hole;

a fourth field plate layer located below the third field plate layer; the fourth field plate layer is connected with the second top metal layer through a second conductive structure; a capacitive medium is arranged between the fourth field plate layer and the third field plate layer, so that a fifth coupling capacitor is formed by the third field plate layer, the fourth field plate layer and the capacitive medium between the third field plate layer and the fourth field plate layer;

a second gate metal layer located below the second field plate layer; the third field plate layer and the fourth field plate layer are hollowed in the thickness direction to form a third cavity and a fourth cavity respectively, and a ninth conductive through hole penetrates through the third cavity and the fourth cavity to connect the second grid metal layer and the third metal layer; and a capacitive medium is arranged between the second gate metal layer and the fourth field plate layer, so that a sixth coupling capacitor is formed by the second gate metal layer, the fourth field plate layer and the capacitive medium therebetween.

13. The capacitor of claim 9, wherein the coupling capacitance module comprises:

the third top metal layer is positioned above the MIM capacitor and is connected with the upper polar plate of the MIM capacitor through a tenth conductive through hole;

a fourth metal layer positioned below the MIM capacitor; a fifth metal layer is arranged in the fourth metal layer, the fifth metal layer is positioned in an area of the fourth metal layer hollowed out in the thickness direction, and the fifth metal layer and the fourth metal layer are separated by a gap; the fifth metal layer is connected with the lower polar plate of the MIM capacitor through an eleventh conductive through hole; the fourth metal layer is connected with the third top metal layer through a third conductive structure, and a capacitance medium is arranged between the fourth metal layer and the lower polar plate of the MIM capacitor, so that the fourth metal layer, the lower polar plate and the capacitance medium between the fourth metal layer and the lower polar plate form a seventh coupling capacitance;

a fifth field plate layer located below the fourth metal layer; the fifth field plate layer is connected with the fourth metal layer through a twelfth conductive through hole;

a sixth field plate layer located below the fifth field plate layer; the sixth field plate layer is connected with the fifth metal layer through a thirteenth conductive through hole; a capacitive medium is arranged between the sixth field plate layer and the fifth field plate layer, so that the fifth field plate layer, the sixth field plate layer and the capacitive medium between the fifth field plate layer and the sixth field plate layer form an eighth coupling capacitor;

A seventh field plate layer located below the sixth field plate layer; the seventh field plate layer is connected with the fourth metal layer through a fourteenth conductive through hole; a capacitive medium is arranged between the seventh field plate layer and the sixth field plate layer, so that a ninth coupling capacitor is formed by the sixth field plate layer, the seventh field plate layer and the capacitive medium therebetween;

a third gate metal layer located below the seventh field plate layer; the sixth field plate layer and the seventh field plate layer are hollowed in the thickness direction to form a sixth cavity and a seventh cavity respectively, and a fifteenth conductive through hole penetrates through the sixth cavity and the seventh cavity to connect the third grid metal layer and the fifth metal layer; and a capacitive medium is arranged between the third gate metal layer and the seventh field plate layer, so that a tenth coupling capacitance is formed by the third gate metal layer, the seventh field plate layer and the capacitive medium therebetween.

14. An integrated circuit, comprising:

a substrate;

an epitaxial layer disposed on the substrate;

a capacitor as claimed in any one of claims 1 to 13, disposed on the epitaxial layer.

15. The integrated circuit of claim 14, wherein a field oxide layer is further disposed between the capacitor and the epitaxial layer.

16. The integrated circuit of claim 14, wherein the integrated circuit further comprises:

an LDMOS device; the LDMOS device comprises at least one metal field plate;

at least one polar plate in the coupling capacitance module of the capacitor is manufactured by using a mask for manufacturing the metal field plate.