CN117708028B - SATA RAID bridging chip - Google Patents

Abstract

The invention discloses a SATA RAID bridging chip. In order to solve the problem that the existing bridging chip has single interface type and can not select a proper interface according to the application requirement of a user, a RAID processor in the bridging chip comprises a first bus interface unit which is used for converting AMBA protocol data into FIFO data, and a RAID data processing core which is used for processing the received FIFO data and outputting the FIFO data; the FIFO data received by the RAID data processing core is FIFO data received by the SATA RAID bridge chip from the host apparatus, or FIFO data obtained by converting AMBA protocol data through the first bus interface unit. The invention solves the technical problems of the existing bridge chip, such as narrow application range and scene, by technical means of bus interface units, and the like, can be applied to equipment with different interfaces of different manufacturers, and also allows users to use the bridge chip in different modes, thereby widening the application range and application scene of the chip. The invention is suitable for the field of chip design.

Description

SATA RAID bridge chip

Technical Field

The invention relates to a SATA RAID bridge chip, in particular to a SATA RAID bridge chip which supports users to select a FIFO interface or an AMBA interface.

Background technique

As the connection component between the host and the hard disk, the hard disk interface undertakes all data transmission functions. It is the interface for data transmission between the hard disk cache and the host memory, and it is also the bottleneck of the data transmission speed between the hard disk and the system. In other words, the performance and speed of the hard disk interface play a great role in restricting the speed and efficiency of the entire computer system.

A common hard disk interface is the Serial Advanced Technology Attachment (SATA) interface. The SATA interface uses a serial connection method and has stronger error correction capabilities. The serial interface also has the advantages of simple structure, hot plug support, and fast transmission speed. The SATA-2 interface is developed on the basis of SATA, and its main feature is that the external transmission rate is further increased from 1.5 Gbps of SATA-1 to 3 Gbps of SATA-2.

Compared with the traditional parallel port transmission mode of Integrated Drive Electronics (IDE) hard disk, SATA interface hard disk has obvious advantages such as high transmission rate, more reliable data, simpler connection, etc., so IDE hard disks have been replaced by SATA hard disks in the market. The data transmission mode of devices using SATA interface is generally: hard disk → memory → CPU → memory → hard disk. Refer to Figure 1, which shows the logic block diagram of a conventional SATA interface, which mainly includes the physical layer, link layer, transmission layer, etc.

As the main storage device of computer systems, the access speed of disk storage lags behind the computing speed of the central processing unit (CPU), resulting in an input/output (I/O) bottleneck problem. In order to increase the data storage capacity of computers and reduce the speed difference between the CPU and I/O systems, Patterson Gibson and Katz of the University of California, Berkeley proposed the concept of Redundant Array of Inexpensive Disks (RAID) technology in 1988.

RAID technology has three main functions: 1. Improve data storage speed by striping data and reading and writing multiple hard disks in parallel; 2. Increase system capacity by expanding the number of hard disks in the array; 3. Realize redundant protection of data by mirroring or storing parity information.

In order to solve the speed difference between the CPU and I/O system, the market uses SATA RAID bridge chips to achieve data transmission between the hard disk. If the RAID function is to be implemented, a RAID processor needs to be integrated in the bridge chip. However, the RAID processors on the market often use a First In First Out (FIFO) interface and cannot be directly used with host devices and SATA cores that use the Advanced Microcontroller Bus Architecture (AMBA) interface.

In view of the existing SATA RAID bridge chips on the market, the commonly used internal RAID processor interface is extremely single, and it is impossible to select a suitable interface according to the actual application needs of users. In order to solve the shortcomings of the prior art, the present invention provides a SATA RAID bridge chip with optional interface, which can select the corresponding interface mode according to the actual needs of users, and can be flexibly integrated into devices with different interfaces from different manufacturers, shortening the development cycle of the SATA RAID bridge chip.

Summary of the invention

In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

A SATA RAID bridge chip comprises a RAID processor, a SATA core and a PHY layer, wherein data output by the SATA core is transmitted to a SATA storage device end via the PHY layer, and the RAID processor comprises a first bus interface unit and a RAID data processing core; the SATA RAID bridge chip supports receiving AMBA protocol data from a host device, and supports receiving FIFO data from the host device; the first bus interface unit is used for converting the AMBA protocol data into FIFO data, and the RAID data processing core is used for processing the received FIFO data and outputting the FIFO data; and the FIFO data received by the RAID data processing core is the FIFO data received by the SATA RAID bridge chip from the host device, or is the FIFO data obtained by converting the AMBA protocol data through the first bus interface unit.

In a certain embodiment, the SATA RAID bridge chip supports RAID mode and non-RAID mode; in RAID mode, the RAID processor receives AMBA protocol data or FIFO data from the host device; in non-RAID mode, the SATA core receives AMBA protocol data or FIFO data from the host device, and the RAID processor is bypassed.

In one embodiment, if the SATA core includes a FIFO interface, the RAID data processing core outputs FIFO data and transmits the data to the SATA core via the FIFO interface of the SATA core.

In a certain embodiment, the RAID processor also includes a second bus interface unit, which is used to convert FIFO data into AMBA protocol data; if the SATA core includes an AMBA interface and a third bus interface unit for data conversion, and the third bus interface unit for data conversion does not support a bypass function, the second bus interface unit of the RAID processor is enabled.

In one embodiment, if the SATA core includes an AMBA interface and a third bus interface unit for data conversion, the third bus interface unit for data conversion is bypassed.

In one embodiment, the RAID processor is used to implement RAID-0, RAID-1, RAID-5 and RAID-10 functions.

In one embodiment, the SATA RAID bridge chip is a dedicated integrated circuit.

In one embodiment, the SATA core and the PHY layer are connected via a PIPE interface.

In one embodiment, the SATA storage device is a disk.

In one embodiment, the SATA RAID bridge chip is used for a host device to access data in a SATA storage device.

The technical solution of the present invention has one or more of the following beneficial technical effects:

1) The present invention provides a SATA RAID bridge chip with flexible interface selection, and can flexibly select a FIFO interface or an AMBA interface according to user needs, thereby broadening the application scope of the bridge chip of the present invention.

2) When the RAID function does not need to be run, the RAID processor can be bypassed to directly interact with the SATA core for data, providing RAID mode and non-RAID mode. The chip provides users with a variety of data transmission modes, broadening the application scenarios of the bridge chip of the present invention.

In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a conventional SATA interface logic block diagram in the prior art;

FIG2 is a logic block diagram of a bridge chip according to the present invention;

FIG3 is a logic block diagram of a RAID processor;

FIG4 is a flow chart of bridge chip data transmission and processing in RAID mode;

FIG5 is a flow chart of bridge chip data transmission and processing in non-RAID mode.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In the description of the present invention, unless otherwise specified, “/” indicates that the objects associated with each other are in an “or” relationship, for example, A/B can represent A or B; “and/or” in the present invention is only a description of the association relationship between associated objects, indicating that there can be three relationships, for example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

In the description of the present invention, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can be represented by: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

In addition, in order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art can understand that the words "first", "second", etc. do not limit the quantity and execution order, and the words "first", "second", etc. do not necessarily limit the difference.

In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" and "for example" is intended to present related concepts in a specific way for easy understanding.

Referring to Fig. 2, a logic block diagram of the bridge chip of the present invention is shown. The bridge chip of the present invention is specifically a SATA RAID bridge chip, hereinafter referred to as a bridge chip, which is a special integrated circuit.

The bridge chip and the host device can establish a data connection with the upstream host device through an AMBA interface or a FIFO interface.

The bridge chip includes a RAID processor, a SATA core and a physical (PHYsical, PHY) layer. The RAID processor is used to implement the RAID function, and can access data in a corresponding mode according to the configured RAID mode. Optionally, the RAID function specifically refers to RAID-0, RAID-1, RAID-5 and RAID-10 functions.

After being processed by the RAID processor, the data passes through the SATA core and PHY layer and is sent to the SATA storage device end, such as several disks. The data can also be read from the SATA storage device end and transmitted to an upstream host device.

AMBA interface and FIFO interface are set between SATA core and RAID processor for data transmission of corresponding protocol types. In addition, SATA core and PHY layer are connected through standard PCIe physical layer interface (Physical Interface for PCI Express, PIPE), which is mainly used to implement SATA storage interface of physical storage devices (such as disk 1, disk 2, ... and disk n), where n is a positive integer.

If the data sent by the upstream host device is based on the AMBA protocol, the data exchange is carried out by connecting to the bridge chip through the AMBA interface during integration. If the data interface sent by the upstream host device is through the FIFO interface, it needs to be connected to the FIFO interface of the bridge chip of the present invention.

On the one hand, the bridge chip of the present invention can establish a data connection with the host device through an AMBA or FIFO interface, thereby realizing the RAID function. This allows the user to flexibly select the FIFO interface or the AMBA interface according to the needs, and can be applicable to the integration of devices with different interfaces from different manufacturers, thus broadening the application scope of the bridge chip of the present invention.

On the other hand, the bridge chip of the present invention also has two different application modes: RAID mode and non-RAID mode. The main difference between the two modes is whether the aforementioned RAID processor is bypassed, which expands the application scenarios of the bridge chip.

Specifically, referring to Fig. 3, it shows the main functional modules of the RAID processor in the present invention. Preferably, the RAID processor in the bridge chip of the present invention is designed with a first bus interface unit and a second bus interface unit. The RAID processor can receive and send AMBA protocol data and FIFO data.

The first bus interface unit is configured to send and receive AMBA protocol data. If the upstream host device sends data via the AMBA protocol, the data is converted into FIFO data via the first bus interface unit and sent to the RAID data processing core.

For the SATA core, in different embodiments, it may have different interface types or configurations.

In certain embodiments, if the downstream SATA core includes a FIFO interface, the FIFO data output by the RAID data processing core can be directly sent to the SATA core.

In certain embodiments, if the downstream SATA core includes an AMBA interface and the internal third bus interface unit is the same as or similar to the first/second bus interface unit in the RAID processor, the third bus interface unit in the downstream SATA core is bypassed. This embodiment helps to reduce chip power consumption.

Furthermore, if it is impossible/not allowed to bypass the third bus interface unit in the SATA core, the second bus interface unit of the RAID processor output port is enabled to convert the data protocol, that is, the second bus interface unit converts the FIFO data into AMBA protocol data.

Refer to Figure 4, which shows the data transmission and processing flow chart of the bridge chip in RAID mode. In this mode, the data of the upstream host device is transmitted to the RAID processor through the AMBA/FIFO interface, and the RAID processor transmits the data to the SATA core through the AMBA/FIFO interface, and finally sends the data to the SATA storage device through the PHY layer.

Refer to Figure 5, which shows the data transmission and processing flow chart of the bridge chip in non-RAID mode. In this mode, the RAID processor is bypassed, and the data output by the host device is directly connected to the SATA core through the AMBA/FIFO interface to execute and complete the data transmission between the SATA storage device ends.

In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (9)

1. The SATA RAID bridging chip comprises a RAID processor, a SATA core and a PHY layer, wherein data output by the SATA core is transmitted to a SATA storage device end through the PHY layer, and the SATA bridging chip is characterized in that:

the RAID processor comprises a first bus interface unit and a RAID data processing core; the SATA RAID bridging chip supports receiving AMBA protocol data from the host equipment and supporting receiving FIFO data from the host equipment;

the first bus interface unit is used for converting AMBA protocol data into FIFO data, and the RAID data processing core is used for processing the received FIFO data and outputting the FIFO data; and

The FIFO data received by the RAID data processing core is the FIFO data received by the SATA RAID bridge chip from the host equipment or the FIFO data obtained by converting AMBA protocol data through the first bus interface unit;

the RAID processor further comprises a second bus interface unit for converting the FIFO data into AMBA protocol data;

The SATA RAID bridging chip supports a RAID mode and a non-RAID mode; in RAID mode, the RAID processor receives AMBA protocol data or FIFO data from a host device; in a non-RAID mode, the SATA core receives AMBA protocol data or FIFO data from a host device, and the RAID processor is bypassed.

2. The SATA RAID bridge chip of claim 1 wherein:

the SATA RAID bridging chip is used for the data access of the host equipment to the SATA storage equipment end.

3. The SATA RAID bridge chip of claim 1 wherein: if the SATA core comprises a FIFO interface, the RAID data processing core outputs FIFO data, and the FIFO data is transmitted to the SATA core through the FIFO interface of the SATA core.

4. The SATA RAID bridge chip of claim 1 wherein:

If the SATA core includes an AMBA interface and a third bus interface unit for data conversion and the third bus interface unit for data conversion does not support bypass functionality, the second bus interface unit of the RAID processor is enabled.

5. The SATA RAID bridge chip of claim 1 wherein: if the SATA core includes an AMBA interface and a third bus interface unit for data conversion, bypassing the third bus interface unit for data conversion.

6. The SATA RAID bridge chip of any one of claims 1-5 wherein: the RAID processor is configured to implement RAID-0, RAID-1, RAID-5, and RAID-10 functions.

7. The SATA RAID bridge chip of any one of claims 1-5 wherein: the SATA RAID bridge chip is an application specific integrated circuit.

8. The SATA RAID bridge chip of any one of claims 1-5 wherein: the SATA core and the PHY layer are connected through a PIPE interface.

9. The SATA RAID bridge chip of any one of claims 1-5 wherein: the SATA storage equipment end is a magnetic disk.