CN117708028A - SATA RAID bridging chip - Google Patents

Abstract

The invention discloses a SATA RAID bridging chip. In order to solve the problem that the existing bridging chip has single interface type and can not select a proper interface according to the application requirement of a user, a RAID processor in the bridging chip comprises a first bus interface unit which is used for converting AMBA protocol data into FIFO data, and a RAID data processing core which is used for processing the received FIFO data and outputting the FIFO data; the FIFO data received by the RAID data processing core is FIFO data received by the SATA RAID bridge chip from the host apparatus, or FIFO data obtained by converting AMBA protocol data through the first bus interface unit. The invention solves the technical problems of the existing bridge chip, such as narrow application range and scene, by technical means of bus interface units, and the like, can be applied to equipment with different interfaces of different manufacturers, and also allows users to use the bridge chip in different modes, thereby widening the application range and application scene of the chip. The invention is suitable for the field of chip design.

Description

SATA RAID bridge chip

Technical field

The invention relates to a SATA RAID bridge chip, and in particular to a SATA RAID bridge chip that supports a user to select a FIFO interface or an AMBA interface.

Background technique

The hard disk interface serves as the connection component between the host and the hard disk and undertakes all data transmission functions. It is the interface for data transmission between the hard disk cache and the host memory. It is also the bottleneck of the data transmission speed between the hard disk and the system. In other words, the performance and speed of the hard disk interface greatly restrict the speed and efficiency of the entire computer system.

A common hard disk interface is the Serial Advanced Technology Attachment (SATA) interface. The SATA interface adopts a serial connection method and has stronger error correction capabilities. The serial interface also has the advantages of simple structure, hot-swappable support, and fast transmission speed. The SATA-2 interface was developed on the basis of SATA. Its main feature is that the external transmission rate has been further increased from the 1.5 Gbps rate of SATA-1 to the 3 Gbps rate of SATA-2.

Compared with the traditional parallel port transmission mode Integrated Drive Electronics (IDE) hard drive, the SATA interface hard drive has obvious advantages such as high transmission rate, more reliable data, and simpler wiring. Therefore, IDE hard drives on the market have been Replaced by SATA hard drive. For devices using the SATA interface, the data transmission method is generally: hard disk → memory → central processing unit → memory → hard disk. Referring to Figure 1, it shows the logical block diagram of a conventional SATA interface, which mainly includes the physical layer, link layer, transport layer, etc.

As the main storage device of the computer system, the growth of disk storage's access speed lags behind the computing speed of the Central Processing Unit (CPU), so there is an input/output (I/O) bottleneck problem. In order to increase the data storage capacity of computers and reduce the speed difference between the CPU and I/O systems, Patterson Gibson and Katz of the University of California, Berkeley, proposed the Redundant Array of Inexpensive Disks (RAID) technology in 1988. concept.

RAID technology has three main functions: 1. Improve data storage speed by striping data and reading and writing multiple hard disks in parallel; 2. Increase system capacity by expanding the number of hard disks in the array; 3. Mirror or store parity Verify information to achieve redundant protection of data.

In order to solve the speed difference between the CPU and the I/O system, the SATA RAID bridge chip is used on the market to realize data transmission with the hard disk. If you want to implement the RAID function, the RAID processor needs to be integrated in the bridge chip. However, RAID processors on the market often use First In First Out (FIFO) interfaces and cannot be directly used with host devices and SATA cores that use Advanced Microcontroller Bus Architecture (AMBA) interfaces.

In view of the existing SATA RAID bridge chips on the market, the commonly used internal RAID processor interfaces are extremely single, and it is impossible to select the appropriate interface according to the user's actual application needs. In order to solve the deficiencies of the existing technology, the present invention provides a SATA RAID bridge chip with optional interfaces. The chip can select the corresponding interface mode according to the actual needs of the user, and can be flexibly integrated into devices with different interfaces from different manufacturers, shortening the Improved the development cycle of SATA RAID bridge chips.

Contents of the invention

In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

A SATA RAID bridge chip includes a RAID processor, a SATA core and a PHY layer. The data output by the SATA core is transmitted to the SATA storage device through the PHY layer. The RAID processor includes a first bus interface unit and a RAID data processing Core; the SATA RAID bridge chip supports receiving AMBA protocol data from the host device, and supports receiving FIFO data from the host device; the first bus interface unit is used to convert AMBA protocol data into FIFO data, and the RAID data The processing core is used to process the received FIFO data and output the FIFO data; and the FIFO data received by the RAID data processing core is the FIFO data received by the SATA RAID bridge chip from the host device, or through the The first bus interface unit converts AMBA protocol data to FIFO data.

In a certain embodiment, the SATA RAID bridge chip supports RAID mode and non-RAID mode; in RAID mode, the RAID processor receives AMBA protocol data or FIFO data from the host device; in non-RAID mode, the The SATA core receives AMBA protocol data or FIFO data from the host device and the RAID processor is bypassed.

In a certain embodiment, if the SATA core includes a FIFO interface, the RAID data processing core outputs FIFO data and transmits it to the SATA core through the FIFO interface of the SATA core.

In a certain embodiment, the RAID processor further includes a second bus interface unit, the second bus interface unit is used to convert FIFO data into AMBA protocol data; if the SATA core includes an AMBA interface and is used for data conversion and the third bus interface unit used for data conversion does not support the bypass function, then the second bus interface unit of the RAID processor is enabled.

In a certain embodiment, if the SATA core includes an AMBA interface and a third bus interface unit for data conversion, the third bus interface unit for data conversion is bypassed.

In a certain embodiment, the RAID processor is used to implement RAID-0, RAID-1, RAID-5 and RAID-10 functions.

In a certain embodiment, the SATA RAID bridge chip is an application specific integrated circuit.

In a certain embodiment, the SATA core and the PHY layer are connected through a PIPE interface.

In a certain embodiment, the SATA storage device is a disk.

In a certain embodiment, the SATA RAID bridge chip is used for the host device to access data in the SATA storage device.

The technical solution of the present invention has one or more of the following beneficial technical effects:

1) The present invention provides a SATA RAID bridge chip with flexible interface selection. The FIFO interface or AMBA interface can be flexibly selected according to user needs, which broadens the application scope of the bridge chip of the present invention.

2) When there is no need to run the RAID function, the RAID processor can be bypassed to directly interact with the SATA core. RAID mode and non-RAID mode are provided. The chip provides users with a variety of data transmission modes, broadening the scope of the bridge chip of the present invention. application scenarios.

In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments.

Description of the drawings

Figure 1 is a logical block diagram of a conventional SATA interface in the prior art;

Figure 2 is a logical block diagram of the bridge chip of the present invention;

Figure 3 is the logical block diagram of the RAID processor;

Figure 4 is the data transmission and processing flow chart of the bridge chip in RAID mode;

Figure 5 is the data transmission and processing flow chart of the bridge chip in non-RAID mode.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention more clear, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention. , not all examples. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

Among them, in the description of the present invention, unless otherwise stated, "/" means that the related objects are an "or" relationship. For example, A/B can mean A or B; in the present invention, "and/or" "It is just an association relationship that describes related objects. It means that there can be three relationships. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. Among them, A , B can be singular or plural.

In the description of the present invention, "plurality" means two or more than two unless otherwise stated. "At least one of the following" or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items). For example, at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .

In addition, in order to facilitate a clear description of the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with basically the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the number and execution order, and words such as "first" and "second" do not limit the number and execution order.

In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to represent examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present invention shall not be construed as being preferred or advantageous over other embodiments or designs. To be precise, the use of words such as "for example" and "for example" is intended to present relevant concepts in a concrete manner and facilitate understanding.

Referring to Figure 2, a logical block diagram of the bridge chip of the present invention is shown. The bridge chip of the present invention is specifically a SATA RAID bridge chip, which will be referred to as a bridge chip in the following text, and is a dedicated integrated circuit.

The bridge chip and the host device can establish a data connection with the upstream host device through the AMBA interface or FIFO interface.

The bridge chip includes a RAID processor, SATA core and physical (PHYsical, PHY) layer. Among them, the RAID processor is used to implement the RAID function and can perform data access in the corresponding mode according to the configured RAID mode. Optionally, the RAID function specifically refers to RAID-0, RAID-1, RAID-5 and RAID-10 functions.

After the data is processed by the RAID processor, it passes through the SATA core and PHY layer and is sent to the SATA storage device, such as several disks. The data can also be read from the SATA storage device and transmitted to the upstream host device.

There are AMBA interfaces and FIFO interfaces between the SATA core and the RAID processor for data transmission of corresponding protocol types. In addition, the SATA core and PHY layer are connected through the standard PCIe physical layer interface (Physical Interface for Pci Express, PIPE), which is mainly used to implement the SATA storage interface of physical storage devices (such as disk 1, disk 2,... and disk n). where n is a positive integer.

If the data sent by the upstream host device is data based on the AMBA protocol, the AMBA interface is connected to the bridge chip for data interaction during integration. If the data interface sent by the upstream host device is through the FIFO interface, it needs to be connected to the FIFO interface of the bridge chip of the present invention.

On the one hand, a data connection can be established between the bridge chip of the present invention and the host device through an AMBA or FIFO interface, thereby realizing the RAID function. This allows the user to flexibly select the FIFO interface or the AMBA interface according to needs, can be suitable for the integration of devices with different interfaces from different manufacturers, and broadens the application scope of the bridge chip of the present invention.

On the other hand, the bridge chip of the present invention also has two different application modes: RAID mode and non-RAID mode. The main difference between the two modes is whether to bypass the aforementioned RAID processor, which expands the application scenarios of the bridge chip.

Specifically, refer to Figure 3, which shows the main functional modules of the RAID processor in the present invention. Preferably, the RAID processor in the bridge chip of the present invention is designed with a first bus interface unit and a second bus interface unit. The RAID processor can receive and send AMBA protocol data and FIFO data.

The first bus interface unit is configured to send and receive AMBA protocol data. If the upstream host device sends data through the AMBA protocol, the data is converted into FIFO data through the first bus interface unit and sent to the RAID data processing core.

For the SATA core, it may have different interface types or configurations in different embodiments.

In certain embodiments, if the downstream SATA core includes a FIFO interface, the FIFO data output by the RAID data processing core can be directly sent to the SATA core.

In certain embodiments, if the downstream SATA core includes an AMBA interface, and the internal third bus interface unit is the same as or similar to the first/second bus interface unit inside the RAID processor, the downstream SATA core is bypassed The third bus interface unit in This embodiment helps reduce chip power consumption.

Further, if the third bus interface unit in the SATA core cannot/is not allowed to be bypassed, then the second bus interface unit of the RAID processor output port is enabled to convert the data protocol, that is, the second bus interface unit converts the FIFO data Convert to AMBA protocol data.

Refer to Figure 4, which shows the data transmission and processing flow chart of the bridge chip in RAID mode. In this mode, the data of the upstream host device transmits data to the RAID processor through the AMBA/FIFO interface, and the RAID processor transmits the data to the SATA core through the AMBA/FIFO interface, and finally sends the data to the SATA storage device through the PHY layer. end.

Refer to Figure 5, which shows the data transmission and processing flow chart of the bridge chip in non-RAID mode. In this mode, the RAID processor is bypassed, and the data output by the host device is directly connected to the SATA core through the AMBA/FIFO interface to perform and complete data transmission between the SATA storage devices.

In order to better explain the present invention, numerous specific details are given in the above specific embodiments. It will be understood by those skilled in the art that the present invention may be practiced without certain specific details. In some instances, methods, means, components and circuits that are well known to those skilled in the art are not described in detail in order to emphasize the gist of the present invention.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention. should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (10)

1. The SATA RAID bridging chip comprises a RAID processor, a SATA core and a PHY layer, wherein data output by the SATA core is transmitted to a SATA storage device end through the PHY layer, and the SATA bridging chip is characterized in that:

the RAID processor comprises a first bus interface unit and a RAID data processing core;

the SATA RAID bridging chip supports receiving AMBA protocol data from the host equipment and supporting receiving FIFO data from the host equipment;

the first bus interface unit is used for converting AMBA protocol data into FIFO data, and the RAID data processing core is used for processing the received FIFO data and outputting the FIFO data; and, in addition, the processing unit,

the FIFO data received by the RAID data processing core is FIFO data received by the SATA RAID bridge chip from the host apparatus, or FIFO data obtained by converting AMBA protocol data through the first bus interface unit.

2. The SATA RAID bridge chip of claim 1 wherein:

the SATA RAID bridging chip supports a RAID mode and a non-RAID mode;

in RAID mode, the RAID processor receives AMBA protocol data or FIFO data from a host device;

in a non-RAID mode, the SATA core receives AMBA protocol data or FIFO data from a host device, and the RAID processor is bypassed.

3. The SATA RAID bridge chip of claim 2 wherein:

if the SATA core comprises a FIFO interface, the RAID data processing core outputs FIFO data, and the FIFO data is transmitted to the SATA core through the FIFO interface of the SATA core.

4. The SATA RAID bridge chip of claim 2 wherein:

the RAID processor further comprises a second bus interface unit for converting the FIFO data into AMBA protocol data;

if the SATA core includes an AMBA interface and a third bus interface unit for data conversion and the third bus interface unit for data conversion does not support bypass functionality, the second bus interface unit of the RAID processor is enabled.

5. The SATA RAID bridge chip of claim 2 wherein:

if the SATA core includes an AMBA interface and a third bus interface unit for data conversion, bypassing the third bus interface unit for data conversion.

6. The SATA RAID bridge chip of any one of claims 1-5 wherein:

the RAID processor is configured to implement RAID-0, RAID-1, RAID-5, and RAID-10 functions.

7. The SATA RAID bridge chip of any one of claims 1-5 wherein:

the SATA RAID bridge chip is an application specific integrated circuit.

8. The SATA RAID bridge chip of any one of claims 1-5 wherein:

the SATA core and the PHY layer are connected through a PIPE interface.

9. The SATA RAID bridge chip of any one of claims 1-5 wherein:

the SATA storage equipment end is a magnetic disk.

10. The SATA RAID bridge chip of any one of claims 1-5 wherein:

the SATA RAID bridging chip is used for the data access of the host equipment to the SATA storage equipment end.