CN1173399C - Semiconductor package with glue overflow preventing device - Google Patents
Semiconductor package with glue overflow preventing device Download PDFInfo
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Abstract
Description
技术领域technical field
本发明是关于一种半导体封装件,尤指关于一种作为多媒体卡(Multi-Media Card,MMC)的半导体封装件。The present invention relates to a semiconductor package, in particular to a semiconductor package used as a Multi-Media Card (MMC).
背景技术Background technique
目前作为多媒体卡(MMC)用的半导体封装件,为适应使用MMC的电子产品在薄型化上的要求,如美国专利第6,040,622号案已揭示出一种如图9所示的结构。这种MMC半导体封装件,是在一基板10的正面100上黏设有至少一记忆体芯片11及至少一被动组件12(为简化起见,于图示中仅各绘示一个),并使两者与该基板10形成电性连接关系;在该基板10的背面101上则形成有多个电性连结端102,以供该记忆体芯片11及被动组件12借之与外界装置电性连接。该MMC半导体封装件1并具有一封装胶体13,以将该芯片11、被动组件12及基板10包覆,但该基板10的背面101及其上的电性连结端102则外露出该封装胶体13而与大气直接接触。Currently used as a semiconductor package for multimedia cards (MMC), in order to meet the thinning requirements of electronic products using MMC, for example, US Patent No. 6,040,622 has disclosed a structure as shown in FIG. 9 . This MMC semiconductor package is that at least one memory chip 11 and at least one
该种MMC半导体封装件1的模压作业(Molding Process)是将已黏设有记忆体芯片11及被动组件12的基板10夹置于模具14的上模140与下模141间,如图10所示。由于基板10欲为封装胶体13包覆的部分并未为上模140与下模141所夹固,为防止模压作业进行中,用以形成该封装胶体13的封装树脂会溢胶至基板10的背面101上而造成制成品外观上的不良,或甚而污染欲外露的电性连结端102,便须于该下模141上开设一孔道141a,以在模压作业进行前,经过该孔道141a使该基板10真空吸附于下模141上,以使基板10的背面101吻合的贴合于该下模141上,以避免模压作业进行时封装树脂得进入该基板10的背面101与下模141间而造成溢胶(Flash)现象。The molding operation (Molding Process) of this kind of MMC semiconductor package 1 is to sandwich the
然而,利用真空吸附方式以解决溢胶形成的问题,将使模压作业无法将用现有的封装用模具,且具真空吸附功能的模具的成本亦较现有模具为高,操作上更为复杂而令制造成本增加。因此,如何使用既有的封装用模具以降低制造成本及简化制造流程乃成业界亟待解决的一大课题。同时,由于前述的MMC半导体封装件包覆有较多的电子及半导体组件,于其运作时产生的热量自较仅包覆有单一半导体芯片者为多,故如何提升散热效率以确保制成品的信赖性亦成亟须因应的课题。此外,当一半导体封装件内包覆有多个电子及半导体组件时,往往易受外界的电磁干扰(Electro Magnetic Interference,EMI)而影响半导体封装件的电子性能,此亦为产业界所欲解决的疑难的问题。However, the use of vacuum adsorption to solve the problem of overflowing glue will make the molding operation unable to use the existing packaging molds, and the cost of the mold with vacuum adsorption function is also higher than the existing molds, and the operation is more complicated. This increases the manufacturing cost. Therefore, how to use the existing packaging molds to reduce the manufacturing cost and simplify the manufacturing process has become a major issue to be solved in the industry. At the same time, since the above-mentioned MMC semiconductor package is covered with more electronic and semiconductor components, the heat generated during its operation is naturally more than that of a single semiconductor chip, so how to improve the heat dissipation efficiency to ensure that the finished product Reliability has also become an urgent issue. In addition, when a semiconductor package is covered with multiple electronic and semiconductor components, it is often susceptible to external electromagnetic interference (Electro Magnetic Interference, EMI) and affects the electronic performance of the semiconductor package. This is also what the industry wants to solve. difficult questions.
发明内容Contents of the invention
本发明的目的即在提供一种具溢胶防止装置的半导体封装件,利用该溢胶防止装置的设置,可使用既有的封装用模具而毋须真空吸附模具,并有效避免基板背面发生溢胶。The object of the present invention is to provide a semiconductor package with a glue overflow prevention device. By using the glue overflow prevention device, the existing packaging mold can be used without vacuum suction mold, and the glue overflow on the back of the substrate can be effectively avoided. .
本发明的目的可以通过以下措施来达到:The object of the present invention can be achieved through the following measures:
一种具溢胶防止装置的半导体封装件,包括:A semiconductor package with a glue overflow prevention device, comprising:
一基板,其具有一正面与一相对的背面,于该正面上是布设有多个导电迹线,而该背面上形成有多个与该导电迹线电性连通的电性连结端;A substrate, which has a front surface and an opposite back surface, on which a plurality of conductive traces are arranged, and a plurality of electrical connection terminals electrically connected to the conductive traces are formed on the back surface;
至少一芯片,其黏设至该基板的正面上并与该导电迹线电性连接;at least one chip bonded to the front side of the substrate and electrically connected to the conductive trace;
至少一被动组件,其黏设至该基板的正面上并与该导电迹线电性连接;at least one passive component adhered to the front surface of the substrate and electrically connected to the conductive trace;
一溢胶防止装置,其黏置于该基板的正面上,并形成有一收纳空间以将该芯片与被动组件收纳其中以及多个通孔,且该溢胶防止结构的顶端至该基板的正面间的高度是微高于一在模压作业中使用的封装模具的模穴深度;以及A glue overflow prevention device, which is glued on the front surface of the substrate, and forms a storage space for storing the chip and passive components therein and a plurality of through holes, and the top of the glue overflow prevention structure is between the front surface of the substrate is slightly higher than the cavity depth of a packaging tool used in the molding operation; and
一封装胶体,用以包覆该芯片、被动组件、溢胶防止装置及基板,但该基板的背面则外露出该封装胶体。An encapsulation compound is used to cover the chip, the passive component, the glue overflow prevention device and the substrate, but the encapsulation compound is exposed on the back of the substrate.
该溢胶防止装置借一弹性胶黏剂与该基板黏接。The glue overflow preventing device is bonded to the substrate by an elastic adhesive.
该溢胶防止装置借一导热性胶黏剂与该基板黏接。The glue overflow prevention device is bonded to the substrate by a thermally conductive adhesive.
该溢胶防止装置的通孔是供用以形成该封装胶体的树脂化合物流通。The through hole of the overflow prevention device is used for the circulation of the resin compound used to form the encapsulation.
该溢胶防止装置的顶端边缘上复形成有阶梯状凹部。A stepped recess is formed on the edge of the top end of the glue overflow preventing device.
该溢胶防止装置的外侧壁接近于该基板的侧边。The outer wall of the glue overflow preventing device is close to the side of the substrate.
该溢胶防止装置的外侧壁宜与该基板的侧边对齐。The outer wall of the glue overflow prevention device is preferably aligned with the side of the substrate.
该溢胶防止装置的顶端是外露出该封装胶体。The top of the glue overflow preventing device exposes the encapsulation glue.
该导电迹线于对应该溢胶防止装置处是形成有接地迹线,以供该溢胶防止装置与该接地迹线借一导电性胶黏剂黏接,而提高该半导体封装件的电性。The conductive trace is formed with a grounding trace corresponding to the glue overflow prevention device, so that the glue overflow prevention device and the ground trace are bonded by a conductive adhesive to improve the electrical performance of the semiconductor package. .
本发明相比现有技术具有如下优点:Compared with the prior art, the present invention has the following advantages:
为达成本发明以上及其它目的,本发明的具溢胶防止装置的半导体封装件包括:一基板,其具有一正面与一相对的背面,于该正面上布设有多个导电迹线,且该背面上形成有多个电性连结端(Electrical-Connection Terminals)以与该导电迹线电性藕接;至少一芯片,黏设于该基板的正面上并与该基板电性藕接;至少一被动组件,黏设于该基板的正面上并与该基板电性藕接;一溢胶防止装置,其黏设于基板的正面上,以使该芯片与被动组件收纳于一由该溢胶防止装置所形成的收纳空间中,且令该溢胶防止装置的顶面至基板的正面间的高度是略高于一用以形成包覆该芯片、被动组件、溢胶防止装置及基板的封装胶体的模具的模穴深度;以及一封装胶体,以将该芯片、被动组件、溢胶防止装置及基板包覆,并使该溢胶防止装置的顶部外露出。In order to achieve the above and other objects of the present invention, the semiconductor package with glue overflow prevention device of the present invention includes: a substrate having a front surface and an opposite back surface, a plurality of conductive traces are arranged on the front surface, and the A plurality of electrical-connection terminals (Electrical-Connection Terminals) are formed on the back side to be electrically coupled with the conductive trace; at least one chip is glued on the front side of the substrate and electrically coupled with the substrate; at least one The passive component is glued on the front surface of the substrate and is electrically coupled with the substrate; a glue overflow prevention device is glued on the front surface of the substrate so that the chip and the passive component are accommodated in a glue overflow preventing device. In the storage space formed by the device, the height between the top surface of the glue overflow prevention device and the front surface of the substrate is slightly higher than an encapsulant used to form the chip, the passive component, the glue overflow prevention device and the substrate The mold cavity depth of the mold; and an encapsulation compound to cover the chip, the passive component, the glue overflow prevention device and the substrate, and expose the top of the glue overflow prevention device.
本发明可有效避免基板背面发生溢胶,并能有效提高半导体封装件本身的散热效率以及降低电磁干扰,而使制成品的电性与可靠性改善。The invention can effectively avoid glue overflow on the back of the substrate, effectively improve the heat dissipation efficiency of the semiconductor package itself and reduce electromagnetic interference, so that the electrical properties and reliability of the finished product are improved.
附图说明Description of drawings
为使本发明的特点及功效更臻明确,以下兹以较佳实施例配合附图进一步详细说明:In order to make the characteristics and effects of the present invention more clear, the following are further detailed descriptions with preferred embodiments in conjunction with the accompanying drawings:
图1是本发明半导体封装件的第一实施例的剖视图;1 is a cross-sectional view of a first embodiment of a semiconductor package of the present invention;
图2是本发明第一实施例所使用的溢胶防止装置的立体图;2 is a perspective view of the glue overflow prevention device used in the first embodiment of the present invention;
图3是本发明第一实施例的半导体封装件于进行模压作业时的示意图;3 is a schematic diagram of the semiconductor package in the first embodiment of the present invention when performing molding operations;
图4是本发明半导体封装件的第二实施例的剖视图;4 is a cross-sectional view of a second embodiment of the semiconductor package of the present invention;
图5是本发明第二实施例所使用的溢胶防止装置的立体图;5 is a perspective view of the glue overflow preventing device used in the second embodiment of the present invention;
图6是本发明半导体封装件的第三实施例的剖视图;6 is a cross-sectional view of a third embodiment of the semiconductor package of the present invention;
图7是本发明第三实施例所使用的溢胶防止装置的立体图;7 is a perspective view of the glue overflow preventing device used in the third embodiment of the present invention;
图8是本发明半导体封装件的第四实施例的剖视图;8 is a cross-sectional view of a fourth embodiment of a semiconductor package of the present invention;
图9是现有MMC半导体封装件的剖视图;以及9 is a cross-sectional view of an existing MMC semiconductor package; and
图10是现有MMC半导体封装件于进行模压作业时的示意图。FIG. 10 is a schematic diagram of a conventional MMC semiconductor package during molding operations.
具体实施方式Detailed ways
图1所示者为本发明半导体封装件第一实施例的剖视图。该第一实施例的半导体封装件2包括一基板20,其具有一正面200,及一相对的背面201,以于该正面200上形成多个导电迹线202及于该背面201上形成多个电性连结端203,且该导电迹线202是借导电穿孔(Conductive Vias)或连通电路(Interconnecting Wires)与该电性连结端203电性连通。由于该导电穿孔或连通电路的设置为现有技术,故在此不予图示及赘述。至于制成该基板20的材质,则现有的聚亚醯胺树脂(Polyimide Resin)、聚丁二烯(BT)树脂、环氧树脂玻璃(FR4)或陶瓷(Ceramic)材料等均适用。FIG. 1 is a cross-sectional view of a first embodiment of a semiconductor package of the present invention. The
在该基板20的正面200上的预设位置是供一芯片21及一被动组件22黏接,然而须知芯片与被动组件的设置数量得视需要增加。该芯片21黏接后是以多个现有的金线23与该基板20上的导电迹线202形成电性连接关系,该芯片21亦得以现有的覆晶(Flip Chip)或TAB(TapeAutomated Bonding)技术电性连接至导电迹线202。而该被动组件22则亦得以前述的电性连接方式与基板20上的导电迹线202形成电性连接关系。由于该导电迹线202是与基板20背面201上的电性连结端203电性连通,故该芯片21及被动组件22得借该电性连结端203与外界装置(External Devices)电性连结。The preset position on the front surface 200 of the
该基板20与芯片21及被动组件22的黏接完成后,是使一溢胶防止装置24借现有的导热性且具弹性的胶黏剂25黏接至该基板20的正面200的预设位置上。该溢胶防止装置24是成一中空的矩形框体状,如图2所示,使该中空部分形成一收纳空间240,以在该溢胶防止装置24黏接至基板20的正面200上后,该芯片21及被动组件22恰得收纳于该收纳空间240中而不会碰触至该溢胶防止装置24;同时,为使基板20的正面200上位于该收纳空间240中的面积极大化,以收纳较多数量或尺寸较大的芯片及被动组件,该溢胶防止装置24的外侧壁241宜与该基板20的侧边204对齐。After the bonding of the
该半导体封装件2并包括有一封装胶体26,以将该芯片21及被动组件22包覆而与外界气密隔离,并同时部分包覆住该基板20及溢胶防止装置24,而使该基板20的背面201及溢胶防止装置24的顶端242外露出该封装胶体26。基板20的背面201不为封装胶体26所盖覆,是在使其电性连结端203外露于大气中,以得与外界装置形成良好的电性连接关系。The
如图3所示,该封装胶体26的形成是于一封装模具27中进行。该封装模具27为现有的,是分为上模270与下模271,于该上模270上并开设有一模穴270a以供基板20上的芯片21、被动组件22及溢胶防止装置24收纳于该模穴270a中。当该上模270合模至下模271上后,与该基板20接连但不为封装胶体26所包覆的外围部分20a(即位于模穴270a外的部分)即为上模270及下模271所夹固,而使基板20定位于该封装模具27的模穴270a中。由于该溢胶防止装置24的顶端242至基板20的正面200的高度H是设为微高于模穴270a的深度h,故该溢胶防止装置24的顶端242于上模270与下模271合模后会顶抵于该模穴270a的顶壁270b,使合模的压力经该溢胶防止装置24传递至基板20,而令该基板20的背面201密合地压接于下模271上,遂使基板20与下模271间无缝隙存在,故在模压作业进行时,用以形成该封装胶体26的树脂化合物不致溢胶于基板20的背面201上,使该图1所示的半导体封装件2于封装制程完成后,该基板20的背面201得具有良好的外观,且其上的电性连结端203不会遭受树脂化合物的污染,而可与外界装置产生良好的电性连结。因而,利用该溢胶防止装置24的设置,使该封装胶体26的成型得以现有的封装模具进行,毋须具真空吸附功能的模具,故除能降低制造成本外,尚可简化封装制程。As shown in FIG. 3 , the
此外,该溢胶防止装置24须开设多个通孔243,以在模压作业时,供熔融的树脂化合物自通孔243流入该溢胶防止装置24的收纳空间240中,以包覆该芯片21及被动组件22;同时,该树脂化合物自通孔243中流通,在模压作业完成后,并能使该溢胶防止装置24与固化成型的封装胶体26间的结合性提高。In addition, the glue
为提高该半导体封装件2的散热效率,该溢胶防止装置24得以导热性佳的金属材料制成,如铜、铝、铜合金、铝合金或其它导热性佳的金属材料等,且因该溢胶防止装置24的顶端242是直接外露于大气中,故热量传递至该溢胶防止装置24后,即得由其顶端242直接逸散至大气中。In order to improve the heat dissipation efficiency of the
如图4所示者,为本发明第二实施例的半导体封装件的剖视图。该第二实施例的半导体封装件3的结构大致同于第一实施例中所述,其不同处在于该溢胶防止装置34乃成一矩形盒状结构,如图5所示。该溢胶防止装置34具有一矩形环体344以及一连设于该矩形环体344一端上的片体345,并由该矩形环体344及片体345围限出一收纳空间340,用以收纳芯片31及被动组件32。该片体345上并形成有多个凸出部342,以使该凸出部342的顶端342a至基板30的正面300的高度微高于用以形成包覆该芯片31、被动组件32及溢胶防止装置34的封装胶体36的模具(未图示)的模穴深度,以在模压作业中该凸出部342的顶端342a会顶抵至模穴的顶壁上,而避免树脂化合物溢胶于供该芯片31及被动组件32黏设的基板30的背面301上。同时,该矩形环体344亦开设有多个通孔344b,以供熔融的树脂化合物流通该通孔344b而进入收纳空间340中。此外,该基板30的正面300上的导电迹线302在对应该矩形环体344的底部344a处是形成有接地迹线302a(GroundTraces),以在该溢胶防止装置34借一导电性胶黏剂35黏接至该基板30上后,该溢胶防止装置34得与该接地迹线302a形成电性连接,故可提升半导体封装件3的电性。再者,该溢胶防止装置34因是覆盖于该芯片31与被动组件32之上,故在芯片31于高频运作时,能利用该溢胶防止装置34的遮蔽(Shielding)而减少外界的电磁干扰(EMI)对芯片31运作的影响,而得进一步提升该半导体封装件3的电性。As shown in FIG. 4 , it is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention. The structure of the
如图6所示者,为本发明第三实施例的半导体封装件的剖视图。该第三实施例的半导体封装件4的结构大致同于该第二实施例中所述,其不同处在于该溢胶防止装置44的片体445上并未形成有任何凸出部,如图7所示,亦即该片体445的顶面445a须在封装胶体46固化成型后,完全外露出该封装胶体46而直接与大气接触。因而,该片体445的顶面445a至基板40的正面400间的高度须设为微高于形成封装胶体46的封装模具(未图示)的模穴深度,以使供该溢胶防止装置44黏设的基板40的背面401与封装模具的下模(未图示)间不会产生熔融树脂化合物会流入的间隙,而得避免基板40的背面401上有溢胶的形成。同样地,该矩形环体444上亦形成有多个供熔融树脂化合物流通的通孔444b。As shown in FIG. 6 , it is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention. The structure of the
如图8所示者,为本发明第四实施例的半导体封装件的剖视图。该第四实施例的半导体封装件5的结构大致同于第三实施例中所述,其不同处在于该溢胶防止装置54的片体545的侧缘上是形成有阶梯状凹部542a,以由该阶梯状凹部542a的形成防止熔融的树脂化合物亦溢胶于片体545上。As shown in FIG. 8 , it is a cross-sectional view of a semiconductor package according to a fourth embodiment of the present invention. The structure of the semiconductor package 5 of the fourth embodiment is substantially the same as that described in the third embodiment, the difference is that a stepped recess 542a is formed on the side edge of the sheet 545 of the glue overflow preventing device 54, so as to The formation of the stepped concave portion 542 a prevents the melted resin compound from overflowing on the sheet body 545 .
须知,上述仅为本发明的具体实施例而已,其它任何未背离本发明的精神与技术下所作的等效改变或修饰,均应仍包含在本专利申请的权利要求保护范围之内。It should be noted that the above are only specific embodiments of the present invention, and any other equivalent changes or modifications made without departing from the spirit and technology of the present invention shall still be included within the protection scope of the claims of this patent application.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011003952A CN1173399C (en) | 2001-01-04 | 2001-01-04 | Semiconductor package with glue overflow preventing device |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB011003952A CN1173399C (en) | 2001-01-04 | 2001-01-04 | Semiconductor package with glue overflow preventing device |
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| CN1362737A CN1362737A (en) | 2002-08-07 |
| CN1173399C true CN1173399C (en) | 2004-10-27 |
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| CNB011003952A Expired - Lifetime CN1173399C (en) | 2001-01-04 | 2001-01-04 | Semiconductor package with glue overflow preventing device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7786603B2 (en) * | 2005-10-28 | 2010-08-31 | Freescale Semiconductor, Inc. | Electronic assembly having graded wire bonding |
| CN101702402B (en) * | 2009-11-09 | 2011-05-04 | 友达光电股份有限公司 | Anti-overflow glue device and substrate bonding method using the anti-overflow glue device |
| TWI571185B (en) * | 2014-10-15 | 2017-02-11 | 矽品精密工業股份有限公司 | Electronic package and its manufacturing method |
| US10037974B2 (en) * | 2016-03-08 | 2018-07-31 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| CN115621212B (en) * | 2022-11-07 | 2023-04-07 | 合肥矽迈微电子科技有限公司 | Anti-overflow packaging structure and chip mounting method thereof |
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2001
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