CN116247007A - A method of manufacturing a semiconductor device - Google Patents

Abstract

The invention discloses a manufacturing method of a semiconductor device, comprising: a first-type region forming process, implanting a first-type impurity into a semiconductor substrate, drain side of the first field effect transistor forming region, and a second field effect transistor The source side and the drain side of the formation region form the first type region, wherein the first field effect transistor formation region is the region where the first field effect transistor is formed, and the second field effect transistor formation region is the region where the second field effect transistor is formed. region; a gate electrode forming process; and an electrostatic discharge protection region forming process, injecting second-type impurities into a part of the first-type region of the first field-effect transistor forming region to form a second-type region, wherein the second-type impurity and the first The polarity of the type impurity is opposite, and the interface position of the second type region is shallower than that of the first type region, and the polarity of the second type region is opposite to that of the first type region, thereby forming an electrostatic discharge in the first field effect transistor formation region protected area. The invention can reduce the manufacturing cost and improve the performance of the semiconductor device.

Description

A method of manufacturing a semiconductor device

technical field

The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device.

Background technique

When an electrostatic discharge (Electro-Static Discharge, ESD) protection area is formed on the drain side of a Metal-Oxide-Semiconductor Field-Effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, Field Effect Transistor), in order only to To inject P-type impurities into a specified area, it is necessary to cover the area where the field effect transistor is to be formed with a special mask formed by photoresist. In this case, in the manufacture of the semiconductor device, a dedicated mask is required for the implantation of P-type impurities, so the manufacturing process and manufacturing cost of the semiconductor device are too high.

Contents of the invention

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of manufacturing a semiconductor device with a low voltage for starting the operation of a field effect transistor without increasing the manufacturing cost.

In order to solve the problems of the technologies described above, the present invention is achieved through the following technical solutions:

The present invention provides a method for manufacturing a semiconductor device. The semiconductor device forms a first field effect transistor and a second field effect transistor with an electrostatic discharge protection area on a semiconductor substrate. The method for manufacturing the semiconductor device includes:

The step of forming the first-type region, by implanting first-type impurities into the semiconductor substrate, the drain side of the first field effect transistor formation region and the source side and drain side of the second field effect transistor formation region are respectively , forming a first-type region, wherein the first field effect transistor forming region is a region where the first field effect transistor is formed, and the second field effect transistor forming region is a region where the second field effect transistor is formed ;

A gate electrode forming process, forming a gate electrode in the first field effect transistor formation region and the second field effect transistor formation region; and

ESD protection region forming process, implanting second-type impurities into part of the first-type region in the first field-effect transistor formation region to form a second-type region, wherein the second-type impurities and the first The polarity of the type impurity is opposite, wherein the interface position of the second type region is shallower than that of the first type region, and the polarity of the second type region is opposite to that of the first type region, so that in the second type region The field effect transistor forming region forms the electrostatic discharge protection region.

In an embodiment of the present invention, the manufacturing method of the semiconductor device includes a step of forming a silicide block, the silicide block is formed in the first field effect transistor formation region, wherein the silicide block is located in the between the gate electrode and the first-type region, and the silicide block is formed on a side away from the edge of the first-type region.

In an embodiment of the present invention, the silicide blocks are distributed along the width direction of the semiconductor substrate.

In an embodiment of the present invention, after forming the gate electrode, the sidewall of the gate electrode is oxidized to form the sidewall.

In an embodiment of the present invention, before forming the sidewall, the silicide forming process is performed.

In an embodiment of the present invention, before performing the gate electrode forming process, the first type region forming process is performed.

In an embodiment of the present invention, before performing the electrostatic discharge protection region forming process, the gate electrode forming process is performed.

In an embodiment of the present invention, in the gate electrode forming step, a gate oxide film is formed on the semiconductor substrate, and the gate electrode is formed on the gate oxide film.

In an embodiment of the present invention, before performing the step of forming the first-type region, the semiconductor substrate is annealed.

In an embodiment of the present invention, at the same depth, the impurity concentration of the first-type region is higher than the channel impurity concentration of the gate electrode.

As described above, the present invention provides a method of manufacturing a semiconductor device capable of manufacturing a semiconductor device in which the operation start voltage of a field effect transistor is lowered without increasing the manufacturing cost.

Of course, any product implementing the present invention does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that are required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a schematic diagram of the structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

4 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

5 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

7 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

9 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

10 is an enlarged view of an ESD protection region in the semiconductor device according to the first embodiment of the present invention.

11 is a graph showing the depth from the upper surface of the semiconductor substrate and the impurity concentration of each impurity within the ESD protection region of the semiconductor device according to the first embodiment of the present invention.

12 is an enlarged view of an ESD protection region in a semiconductor device according to a second embodiment of the present invention.

13 is a plan view of a semiconductor device according to a second embodiment of the present invention.

14 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

15 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 16 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 17 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 18 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 19 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 20 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 21 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

In the figure: 1. Semiconductor device; 2. Semiconductor substrate; 3. Shallow trench isolation structure; 4. Type I P-type region; 4', Type II P-type region; 5. Lightly doped drain region; 6. Source and drain 6S, source area; 6D, first-class drain area; 6D', second-class drain area; 7, gate oxide film; 8, first-class electrostatic discharge protection area; 8', second-class electrostatic discharge protection area ; 10, a first type of field effect tube; 10', a second type of first field effect tube; 10b, a formation area of a type of first field effect tube; 10b', a formation area of a second type of first field effect tube; 20, the first type Two field effect transistors; 21. Lightly doped drain region on the source side; 22. Lightly doped drain region on the drain side; 23. N-type source region; 24. N-type drain region; 30. Silicide block; G , Grid electrode.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Please refer to FIG. 1 , which is a schematic diagram of the structure of a semiconductor device according to a first embodiment of the present invention. In this embodiment, the direction perpendicular to the thickness (depth) direction X of the semiconductor substrate 2 (substrate) is referred to as the width direction Y. In addition, the cross section shown in FIG. 1 is continuously formed within a predetermined range in the depth direction perpendicular to the thickness direction X and the width direction Y, respectively, and description thereof will be omitted. In addition, in the following description, an example is given about the thickness or width, but it is not limited to this example. For example, the error range of the injection amount in the manufacturing process or the like, or the error range of the thickness and width of the finished product is allowed.

Referring to FIG. 1, in an embodiment of the present invention, a semiconductor device 1 includes a first type of field effect transistor 10, and a type of first field effect transistor 10 is an NMOS transistor (Grounded-Gate NMOS, GGNMOS) with a gate grounded. ). A type of first field effect transistor 10 includes a semiconductor substrate 2 , a shallow trench isolation structure 3 , a type of P-type region 4 , a lightly doped drain region 5 , a source-drain region 6 , a gate oxide film 7 and a gate electrode G. Wherein, the semiconductor substrate 2 includes a P-well region formed by implanting P-type impurities. The shallow trench isolation structure 3 is formed by a shallow trench isolation process (shallow trench isolation, STI). One type of P-type region 4 is the first-type region formed on the drain side. Lightly doped drain regions 5 are respectively formed on the source side and the drain side. The source-drain region 6 is a second-type region formed on the source side and the drain side respectively. In FIG. 1 , 6S represents the source-drain region on the source side, and 6D represents the source-drain region on the drain side. In this embodiment, a type of P-type region 4 and source-drain region 6D are PN-bonded to form a type of ESD protection region 8 . Wherein, when an electrostatic discharge (ESD) is applied, a type of ESD protection area 8 can be used to prevent a type of first field effect transistor 10 from malfunctioning.

Please refer to FIG. 1 , in an embodiment of the present invention, a first type of field effect transistor 10 includes a drain electrode and a gate electrode G. As shown in FIG. Wherein, the drain can be a drain in an NMOS transistor, and the drain can be formed in a P-type semiconductor substrate 2 or a P-well region, and can be used as an N-type impurity diffusion region. The gate electrode G is disposed on the semiconductor substrate 2 , and a gate oxide film 7 is interposed between the gate electrode G and the semiconductor substrate 2 . In this embodiment, one type of first field effect transistor 10 includes an N-type impurity diffusion region, and the N-type impurity diffusion region can be used as a source of an NMOS transistor. In this embodiment, the first type of field effect transistor 10 may be an NMOS device with a relatively large width. Wherein, the gate electrode, the source electrode and the body (body) are connected to the ground wire, and the drain electrode is connected to the I/O pad.

Referring to FIG. 1 , in an embodiment of the present invention, the semiconductor substrate 2 may be a P-type silicon substrate. The semiconductor substrate 2 includes a P well region and a shallow trench isolation structure 3 . Among them, by implanting P-type impurities such as boron (B) into the semiconductor substrate 2 , a region with P-type polarity, that is, a P-well region is formed. Wherein, the shallow trench isolation structure 3 is a structure for isolating various regions in the semiconductor substrate 2 . Specifically, the shallow trench isolation structure 3 may be formed by digging a trench (trench) at a preset position and filling the dug trench with a silicon oxide film. Wherein, the shallow trench isolation structure 3 is an insulator, so the shallow trench isolation structure 3 can electrically isolate various regions on the surface of the semiconductor substrate 2 .

Please refer to FIG. 1, in one embodiment of the present invention, a P-type high-concentration region can be formed in the semiconductor layer by implanting P-type impurities such as boron (B) into the drain side of the semiconductor substrate 2, thereby forming a type of P-type region 4. A type of P-type region 4 forms a PN junction with a source-drain region 6D on the drain side described later, forming a type of ESD protection region 8 .

Please refer to FIG. 1. In one embodiment of the present invention, N-type impurities such as arsenic (As) or phosphorus (P) can be injected into the source side and drain side of the semiconductor substrate 2 to form a The region is doped with a low concentration to form a lightly doped drain region 5 . By forming a low-concentration region in the semiconductor layer, the depletion layer in the P-well region under the gate electrode G is enlarged, thereby reducing the electric field intensity.

Please refer to FIG. 1 , in an embodiment of the present invention, according to the design of the integrated circuit, transistors can be formed in multiple regions on the semiconductor substrate 2 . In this embodiment, the source and drain regions 6 can be formed by implanting N-type impurities such as arsenic (As) or phosphorus (P) into the drain region where the transistor is to be installed. Wherein, the source-drain region 6D corresponds to the drain electrode, and the source-drain region 6 can be formed by polysilicon. Also, the interface position of the source-drain region 6D is shallower than that of the P-type region 4 .

Please refer to FIG. 1 , in one embodiment of the present invention, the gate oxide film 7 is located under the gate electrode G, and the gate oxide film is formed on the surface of the semiconductor substrate 2 . The channel region at the bottom of the gate electrode G in the semiconductor substrate 2 is insulated from the gate electrode G by forming the gate oxide film 7 . Accordingly, when a voltage is applied to the gate electrode G, carriers are appropriately moved between the source and the drain, and current flows in the channel region.

Please refer to FIG. 1 , in an embodiment of the present invention, the gate electrode G may be polysilicon. And the gate electrode G is formed on the gate oxide film 7 . In addition, a high dielectric constant insulating film/metal gate (Metal Gate/High-K, MGHK) may be used for the gate electrode G other than polysilicon.

Referring to FIG. 1 to FIG. 9 , the present invention provides the manufacturing process of the semiconductor device 1 in the above-mentioned embodiment. In this embodiment, the first type of field effect transistor 10 may be an NMOS transistor whose gate is grounded. The second field effect transistor 20 is specifically a medium voltage PMOS transistor. Wherein, in FIG. 2 to FIG. 9 , except for one type of first field effect transistor 10 and second field effect transistor 20 , illustrations of other PMOS transistors or NMOS transistors formed on the semiconductor substrate 2 are omitted.

Referring to FIG. 1 and FIG. 2 , in an embodiment of the present invention, in step S10 , a shallow trench isolation structure 3 is formed on the semiconductor substrate 2 . The shallow trench isolation structure 3 is a structure for isolating regions of the semiconductor substrate 2 , and the shallow trench isolation structure 3 can be formed by digging a trench (trench) at a predetermined position and filling the trench with a silicon oxide film. Wherein, the shallow trench isolation structure 3 is an insulator to electrically isolate various regions formed on the semiconductor substrate 2 . In this embodiment, an oxide film with a thickness of, for example, 8 nm can be formed on the upper surface of the semiconductor substrate 2 by a thermal oxidation method. Moreover, the oxide film is located outside the area where the shallow trench isolation structure 3 is located. However, the thermal oxidation method may be any of dry oxidation, wet oxidation, and steam oxidation.

Please refer to Fig. 1 and Fig. 2, in one embodiment of the present invention, next, P-type impurities such as boron (B) are implanted into the first type of field effect transistor forming region 10b, and the second field effect transistor forming region 20b N-type impurities such as arsenic (As) or phosphorus (P) are implanted. Then, annealing is performed on the semiconductor substrate 2 to form a P-well region in a type of first FET forming region 10b, and form an N-well region in a second FET forming region 20b.

Please refer to FIG. 3, in one embodiment of the present invention, then, in step S12 shown in FIG. Impurities form a type of P-type region 4 in a type of first field effect transistor formation region 10b, and form a source side lightly doped drain region 21 and a drain side lightly doped region 21 in a second field effect transistor formation region 20b Drain area 22. In the present embodiment, in the semiconductor substrate 2 , the upper surface of the semiconductor substrate 2 is masked with a photoresist. Moreover, the shielded surface of the semiconductor substrate 2 does not include a type of P-type region 4 , source side lightly doped drain region 21 and drain side lightly doped drain region 22 . Wherein, a type of P-type region 4 is formed on the drain side of a type of first field effect transistor forming region 10b. The source side lightly doped drain region 21 and the drain side lightly doped drain region 22 are formed in the second field effect transistor forming region 20b. Moreover, the lightly doped drain region 21 on the source side and the lightly doped drain region 22 on the drain side are the first type regions.

Please refer to Fig. 3, in one embodiment of the present invention, then, in the state where the upper surface of the semiconductor substrate 2 is shielded, impurities are implanted into the semiconductor substrate 2, and a type of first field effect transistor is formed in the region A type of P-type region 4 is formed in 10b, and a source side lightly doped drain region 21 and a drain side lightly doped drain region 22 are formed in the second field effect transistor forming region 20b. In this embodiment, the ion implantation energy for forming a type of P-type region 4 , the source side lightly doped drain region 21 and the drain side lightly doped drain region 22 is, for example, 60 keV, and the ion implantation dose is, for example, on the order of 3e+13/ cm ² . And a type of P-type region 4 , source-side lightly doped drain region 21 and drain-side lightly doped drain region 22 can be formed by implanting P-type impurities such as boron (B) into the P-well region.

Please refer to FIG. 4 to FIG. 9, in an embodiment of the present invention, next, in step S14 shown in FIG. The masking of the drain region 22 is removed. A mask is formed on the surface of the semiconductor substrate 2 except the region where the gate electrode G is to be provided in each of the first field effect transistor formation region 10b and the second field effect transistor formation region 20b. And a gate oxide film 7 is formed in a region where the gate electrode G is to be provided by a thermal oxidation method. However, the thermal oxidation method may be any of dry oxidation, wet oxidation, and steam oxidation. In FIGS. 4 to 9 , the illustration of the thinner oxide film on the upper surface of the semiconductor substrate 2 is omitted.

Please refer to FIG. 4. In one embodiment of the present invention, after forming the gate oxide film 7, photolithography is used to form the first field effect transistor formation region 10b and the second field effect transistor respectively. In the region 20b, the gate electrode G is patterned in a region where the gate electrode G is to be formed. Then, after removing the mask formed by the photoresist, polysilicon for the gate electrode G is deposited in the designed region on the upper surface of the semiconductor substrate 2 by chemical vapor deposition (Chemical Vapor Deposition, CVD).

Please refer to FIG. 5. In one embodiment of the present invention, next, in step S16 shown in FIG. 5, the arsenic N-type impurities such as (As) are implanted into a first type of field effect transistor forming region 10b, thereby forming a lightly doped drain region 5 on the source side and the drain side. The ion implantation energy for forming the lightly doped drain region 5 of a type of first field effect transistor forming region 10b is, for example, 10keV, and the ion implantation dose is, for example, 1e+15 order/cm ² . By making the ion implantation energy of the impurity in the lightly doped drain region 5 lower than the ion implantation energy of the impurity in the P-type region 4, the interface positions in the lightly doped drain region 5 on the source side and the drain side are formed at a ratio of one The interface position of the quasi-P-type region 4 is shallow.

4 and 6, in an embodiment of the present invention, then, in step S18 shown in FIG. , and spacer walls SW are formed at each gate electrode G, and a source region 6S and a type of drain region 6D are formed in a type of first field effect transistor forming region 10b. In this embodiment, an oxide film may be formed on each gate electrode G by chemical vapor deposition of tetraethyl orthosilicate (TEOS). And anisotropic etching is performed to form an oxide film only on the sidewall of each gate electrode G. Among them, the oxide film formed on the sidewall of each gate electrode G becomes the sidewall SW. Among them, in addition to tetraethyl silicate to form an oxide film, a silicon nitride (SiN) film formed by a chemical vapor deposition method can also be laminated during film formation.

Please refer to FIG. 1 and FIG. 6, in an embodiment of the present invention, next, except for the source region 6S in the first type of field effect transistor formation region 10b, the type of drain region 6D, and other NMOS transistors are formed The source and drain regions 6 in the region shield the upper surface of the semiconductor substrate 2 and the shallow trench isolation structure 3, and inject N-type impurities such as phosphorus (P) into the P-type region 4 and the lightly doped drain region 5 respectively. , forming an N-type source region 6S and a type-type drain region 6D. To form the lightly doped drain region 5 in the first field effect transistor forming region 10b, the ion implantation energy is, for example, 15keV, and the ion implantation dose is, for example, 7e+15 order/cm ² . In this embodiment, the position of the interface between the source region 6S and the type-1 drain region 6D is shallow, and the position of the interface between the source region 6S and the type-1 drain region 6D is relatively shallow relative to the semiconductor substrate. The upper surface of the bottom 2 has a depth of, for example, 0.1 μm.

Please refer to FIG. 1, FIG. 6 and FIG. 7, in one embodiment of the present invention, next, in step S20 shown in FIG. and the N-type drain region 24, and outside the source-drain region 6 in other PMOS transistor formation regions, shield the upper surface of the semiconductor substrate 2, and implant P-type impurities such as boron (B) into the lightly doped source side The drain region 21 and the drain side lightly doped drain region 22 form an N-type source region 23 and an N-type drain region 24 .

6 to 8, in one embodiment of the present invention, then, in step S22 shown in FIG. 8, after removing the mask formed by the photoresist, the semiconductor substrate 2 is annealed. , to activate impurities such as boron (B), arsenic (As), phosphorus (P) implanted into each region. Furthermore, on the drain side of the first type of field effect transistor forming region 10b, the connection interface between the type of P-type region 4 and the type of drain region 6D is PN-bonded to form an electrostatic discharge protection region (ESD protection region) 8 .

Please refer to FIG. 6 to FIG. 9, in an embodiment of the present invention, then, in step S24 shown in FIG. , Coating photoresist on the oxide film to form a pattern. Then, by wet etching using hydrofluoric acid (HF) and/or chemical dry etching, the oxide film is removed only in a predetermined region where the silicide region is to be formed, and an opening of the oxide film is formed. Next, nickel (Ni) is deposited on the surface of the semiconductor substrate 2 by a Physical Vapor Deposition (Physical Vapor Deposition, PVD) method such as sputtering. An annealing treatment is performed after the nickel (Ni) film is formed, so that the junction between silicon (Si) and nickel (Ni) becomes nickel silicide (NiSi). Next, the nickel (Ni) on the upper surface of the semiconductor substrate 2 except the source, drain and gate regions is removed. Among them, silicides such as nickel silicide are formed through a general silicide process flow as described above.

Please refer to FIG. 9 , in an embodiment of the present invention, then, a layer is formed on the conductive layer or each electrode and wiring in the first type of field effect transistor formation region 10b and the second field effect transistor formation region 20b. inter-insulation film. Then, dry etching is used to form contact holes, and the contact holes can be used to respectively connect the electrodes of the source, the drain, the gate and the base body. In this embodiment, a barrier metal is formed on the inner wall surface of the contact hole to prevent silicide such as nickel silicide from being exposed to the environment of fluorine-based compounds and fluorine (F) when filling the contact hole with tungsten (W). middle. Wherein, the barrier metal is, for example, a thin film made of titanium (Ti) or titanium nitride (TiN), and can be formed by sputtering or chemical vapor deposition. The film thickness of the barrier metal may be, for example, 10 nm to 15 nm. After the barrier metal is formed, the contact is formed by filling the contact hole with tungsten (W) or copper (Cu), and the source, drain, and gate are formed by laying metal wiring on the upper surface of the contact of each electrode. The semiconductor device 1 according to this embodiment is manufactured through the above process flow.

Please refer to FIG. 6 , FIG. 10 and FIG. 11 . FIG. 10 is an enlarged view of the ESD protection area in the semiconductor device according to the first embodiment. 11 is a graph showing the depth from the upper surface of the semiconductor substrate and the impurity concentration of each impurity in the ESD protection region of the semiconductor device. In the graph shown in FIG. 11 , the horizontal axis represents the depth within the ESD protection region relative to the upper surface of the semiconductor substrate 2 . The vertical axis represents the impurity concentration of each impurity in the ESD protection region. In FIG. 11 , the solid line indicates the impurity concentration of arsenic (As), the dotted line indicates the impurity concentration of phosphorus (P), and the dotted line indicates the impurity concentration of boron (B).

Referring to FIG. 6 , FIG. 10 and FIG. 11 , in an embodiment of the present invention, on the drain side of a type of first field effect transistor 10 , a contact portion of the drain electrode is formed on the semiconductor substrate 2 . A type of drain region 6D and a type of P-type region 4 are formed at the bottom of the contact portion of the drain electrode, and a PN junction is formed at the interface of each region. Among them, one type of drain region 6D and one type of P-type region 4 serve as one type of ESD protection region 8 .

Please refer to FIG. 10 and FIG. 11. According to FIG. 11, regarding the impurity concentration of each impurity, the impurity concentration in the PN junction interface between the first type of drain region 6D and the first type of P-type region 4 is, for example, 1e+18 /cm ³ , in a higher state.

Please refer to FIG. 4 and FIG. 6, and FIG. 10 and FIG. 11, in an embodiment of the present invention, in the PN junction interface between one type of P-type region 4 and one type of drain region 6D, the impurity concentration of each impurity in a higher state. In this embodiment, the impurity concentration of one type of P-type region 4 is higher than the impurity concentration under the gate electrode G at the same depth. Therefore, the depletion layer in the PN junction interface between the one-type drain region 6D and the one-type P-type region 4 is larger than the depletion layer in the PN junction interface between the one-type drain region 6D and the P-well region of the semiconductor substrate 2. As narrow as possible.

Please refer to FIG. 10 and FIG. 11, in one embodiment of the present invention, a narrow depletion layer is formed at the PN junction interface between one type of drain region 6D and one type of P-type region 4, causing avalanche breakdown Low voltage. Thus, the parasitic bipolar transistors in the P-well region of the first type of field effect transistor 10 are turned on by the low voltage. Moreover, since the parasitic bipolar transistor is turned on, a large current flows between the drain region 6D and the source region 6S, so that the ESD surge applied to the I/O pad is released to the ground (ground potential) , thereby preventing the ESD surge from being applied to the circuit connected to the first type of field effect transistor 10 .

Please refer to FIG. 1 , FIG. 12 and FIG. 13 . In another embodiment of the present invention, FIG. 12 is an enlarged view of the ESD protection area in the semiconductor device according to the second embodiment. In addition, FIG. 13 is a plan view of the semiconductor device according to the second embodiment. As shown in Figure 12 and Figure 13, the difference between the first field effect transistor 10 of this embodiment and the first embodiment is that in the manufacturing process of this embodiment, there is a gate electrode G in the width direction The process of disposing the silicide block 30 between the second-type P-type region 4 ′, wherein the silicide block 30 is an insulator. Wherein, the silicide block 30 can use the insulating layer when forming the spacer SW. And, the silicide block 30 is formed together with the sidewall SW in the designed region between the gate electrode and the edge of the P-type region by using the photolithography technique and the etching technique.

Please refer to FIG. 12 and FIG. 13 , in another embodiment of the present invention, the silicide block 30 is formed at a position away from the edge of the second-type P-type region 4'. In this embodiment, the distance between the type II P-type region 4' and the silicide block 30 is not limited to a specific value, but can be adjusted according to the impurity diffusion requirements of the thermal oxidation process. However, boron (B), which is a P-type impurity, does not diffuse under the silicide block 30 in the thermal oxidation process. In this embodiment, the distance between the type II P-type region 4' and the silicide block 30 is, for example, 50 nm.

Please refer to FIG. 1, FIG. 12 to FIG. 21, in another embodiment of the present invention, the difference between this embodiment and the first embodiment is that in the manufacturing process of the semiconductor device 1, when far away from the second type P A silicide block 30 is provided at the edge of the type region 4 ′. In this embodiment, except that the silicide block is disposed at a position away from the edge of the type II P-type region 4', the manufacturing process of this embodiment is the same as that of the semiconductor device 1 in the first embodiment. In this embodiment, each process which differs from the first embodiment will be mainly described. The same reference numerals as in the first embodiment are used for the same structures as in the first embodiment. Wherein, in FIG. 14 to FIG. 21 , illustrations of other PMOS transistors or NMOS transistors formed on the semiconductor substrate 2 except for one type of first field effect transistor 10 and second field effect transistor 20 are omitted.

Referring to FIG. 1 and FIG. 14 , in another embodiment of the present invention, in step S30 shown in FIG. 14 , a shallow trench isolation structure 3 is formed on the semiconductor substrate 2 . The shallow trench isolation structure 3 is a structure for isolating regions of the semiconductor substrate 2 , and the shallow trench isolation structure 3 can be formed by digging a trench (trench) at a predetermined position and filling the trench with a silicon oxide film. Wherein, the shallow trench isolation structure 3 is an insulator to electrically isolate various regions formed on the semiconductor substrate 2 . In this embodiment, an oxide film with a thickness of, for example, 8 nm can be formed on the upper surface of the semiconductor substrate 2 by a thermal oxidation method. Moreover, the oxide film is located outside the area where the shallow trench isolation structure 3 is located. However, the thermal oxidation method may be any of dry oxidation, wet oxidation, and steam oxidation.

Please refer to FIG. 1 and FIG. 14. In another embodiment of the present invention, P-type impurities such as boron (B) are implanted into the second-type first field effect transistor formation region 10b', and the second field effect transistor formation region 20b N-type impurities such as arsenic (As) or phosphorus (P) are implanted. Then, annealing is performed on the semiconductor substrate 2 to form a P-well region in the second-type first field-effect transistor formation region 10b', and an N-well region in the second field-effect transistor formation region 20b.

Please refer to FIG. 1, FIG. 12 and FIG. 15, in another embodiment of the present invention, then, in step S32 shown in FIG. The effect transistor formation region 20b is implanted with P-type impurities to form a second-type P-type region 4' in the second-type first field-effect transistor formation region 10b', and a lightly doped source side is formed in the second field-effect transistor formation region 20b. The drain region 21 and the drain side lightly doped drain region 22 . In the present embodiment, in the semiconductor substrate 2 , the upper surface of the semiconductor substrate 2 is masked with a photoresist. Moreover, the shielded surface of the semiconductor substrate 2 does not include the second type P-type region 4', the source side lightly doped drain region 21 and the drain side lightly doped drain region 22 in the second field effect transistor formation region 20b. Wherein, a type of P-type region 4 is formed on the drain side of a type of first field effect transistor forming region 10b. The source side lightly doped drain region 21 and the drain side lightly doped drain region 22 are formed in the second field effect transistor forming region 20b. In this embodiment, when the mask is set, the size of the mask is adjusted to ensure that the size of the process window of the mask can form a silicide block 30 between the gate electrode G and the second-type P-type region 4'.

Please refer to Fig. 1 and Fig. 15, in another embodiment of the present invention, then, in the state where the upper surface of the semiconductor substrate 2 is shielded, impurities are implanted into the semiconductor substrate 2, and in the second type first field A second-type P-type region 4' is formed in the effect transistor forming region 10b', and a source side lightly doped drain region 21 and a drain side lightly doped drain region 22 are formed in the second field effect transistor forming region 20b. In this embodiment, the ion implantation energy for forming the second-type P-type region 4', the source side lightly doped drain region 21 and the drain side lightly doped drain region 22 is, for example, 60keV, and the ion implantation dose is, for example, on the order of 3e+13 /cm ² . And a type of P-type region 4 , source-side lightly doped drain region 21 and drain-side lightly doped drain region 22 can be formed by implanting P-type impurities such as boron (B) into the P-well region.

Please refer to FIG. 1 and FIG. 12, and FIG. 16 to FIG. 21, in another embodiment of the present invention, next, in step S34 shown in FIG. 21 and the lightly doped drain region 22 on the drain side are mask removed. And form a mask on the surface of the semiconductor substrate 2 except the area where the gate electrode G is to be arranged in each area of the second type first field effect transistor formation area 10b' and the second field effect transistor formation area 20b. And a gate oxide film 7 is formed in a region where the gate electrode G is to be provided by a thermal oxidation method. However, the thermal oxidation method may be any of dry oxidation, wet oxidation, and steam oxidation. In FIGS. 16 to 21 , the illustration of the thinner oxide film on the upper surface of the semiconductor substrate 2 is omitted. In this embodiment, when the mask is set, the size of the mask is adjusted to ensure that the size of the process window of the mask can form a silicide block 30 between the gate electrode G and the second-type P-type region 4'.

Please refer to FIG. 16, in another embodiment of the present invention, next, after forming the gate oxide film 7, using photolithography technology, respectively in the second type of first field effect transistor formation region 10b' and the second field effect transistor In the tube formation region 20b, the gate electrode G is patterned in a region where the gate electrode G is to be formed. Then, after removing the photoresist mask, polysilicon for the gate electrode G is deposited in the designed region on the upper surface of the semiconductor substrate 2 by chemical vapor deposition.

Please refer to FIG. 1 and FIG. 17. In another embodiment of the present invention, next, in step S36 shown in FIG. Next, N-type impurities such as arsenic (As) are implanted into the second-type first field effect transistor formation region 10 b ′, thereby forming lightly doped drain regions 5 on the source side and the drain side. The ion implantation energy for forming the lightly doped drain region 5 of the second-type first field effect transistor forming region 10b' is, for example, 10keV, and the ion implantation dose is, for example, 1e+15 order/cm ² . By making the ion implantation energy of the impurity in the lightly doped drain region 5 lower than the ion implantation energy of the impurity in the second-type P-type region 4', the ratio of the interface positions in the lightly doped drain region 5 on the source side to the drain side is The interface position of the second type P-type region 4' is shallow.

Please refer to FIG. 12, FIG. 16 and FIG. 18, in another embodiment of the present invention, next, in step S38 shown in FIG. The side wall SW is formed in the effect transistor formation region 20b and each gate electrode G, and the source region 6S and the second type drain region 6D' are formed in the second type first field effect transistor formation region 10b'. In this embodiment, an oxide film may be formed on each gate electrode G by chemical vapor deposition of tetraethyl silicate. And anisotropic etching is performed to form an oxide film only on the sidewall of each gate electrode G. Among them, the oxide film formed on the sidewall of each gate electrode G becomes the sidewall SW. Among them, in addition to tetraethyl silicate to form an oxide film, a silicon nitride (SiN) film formed by a chemical vapor deposition method can also be laminated during film formation.

Please refer to FIG. 1 and FIG. 18, in another embodiment of the present invention, next, in addition to the source region 6S in the second type of first field effect transistor formation region 10b', the second type of drain region 6D', and other The source-drain region 6 in the NMOS transistor formation region shields the upper surface of the semiconductor substrate 2 and the shallow trench isolation structure 3, and implants phosphorus (P) into the second-type P-type region 4' and the lightly doped drain region 5, respectively. and other N-type impurities to form an N-type source region 6S and a second-type drain region 6D'. To form the lightly doped drain region 5 in the second-type first field effect transistor formation region 10b', the ion implantation energy is, for example, 15keV, and the ion implantation dose is, for example, 7e+15 order/cm ² . In this embodiment, the interface position between the source region 6S and the second-type drain region 6D' is shallow, and the interface position between the source region 6S and the second-type drain region 6D' is opposite to that of the second-type P-type region 4'. On the upper surface of the semiconductor substrate 2, the depth is, for example, 0.1 μm. In this embodiment, the upper surface of the second-type P-type region 4 ′ is PN-bonded with the lower surface portion of the second-type drain region 6D ′.

Please refer to FIG. 1 and FIG. 19, in another embodiment of the present invention, next, in step S40 shown in FIG. Type drain region 24, and outside the source and drain region 6 in other PMOS transistor formation regions, shield the upper surface of the semiconductor substrate 2, and implant P-type impurities such as boron (B) into the lightly doped drain region on the source side 21 and the drain side lightly doped drain region 22 to form an N-type source region 23 and an N-type drain region 24 .

Please refer to Fig. 1, Fig. 12 and Fig. 20, in another embodiment of the present invention, then, in step S42 shown in Fig. 20, after removing the mask formed by photoresist, the semiconductor substrate 2 Perform annealing to activate impurities such as boron (B), arsenic (As), and phosphorus (P) implanted in each region. Moreover, on the drain side of the first field effect transistor forming region 10', the connection interface between the second type P-type region 4' and the second type drain region 6D' undergoes PN bonding to form a second type ESD protection region 8'.

Please refer to Fig. 12 and Fig. 20, in another embodiment of the present invention, then, tetraethyl silicate is deposited by chemical vapor deposition, and by etching technology, the second type of first field effect transistor is formed on the region 10b' The oxide film on the surface is patterned, and a silicide block 30 is formed at a position separated by a predetermined distance from the side edge of the channel of the second-type P-type region 4 ′ in the width direction.

Please refer to FIG. 1, FIG. 12 and FIG. 21, in another embodiment of the present invention, next, in step S44 shown in FIG. Siliconization is carried out at the position, and a photoresist is coated on the oxide film to form a pattern. Then, by wet etching using hydrofluoric acid (HF) and/or chemical dry etching, the oxide film is removed only in a predetermined region where the silicide region is to be formed, and an opening of the oxide film is formed. Next, nickel (Ni) is deposited on the upper surface of the semiconductor substrate 2 by a physical vapor deposition method such as sputtering. An annealing treatment is performed after the nickel (Ni) film is formed, so that the junction between silicon (Si) and nickel (Ni) becomes nickel silicide (NiSi). Next, the nickel (Ni) on the upper surface of the semiconductor substrate 2 except the source, drain and gate regions is removed. Among them, silicides such as nickel silicide are formed through a general silicide process flow as described above.

Referring to FIG. 1 , FIG. 12 , FIG. 14 and FIG. 21 , in another embodiment of the present invention, the silicide block 30 is then removed by anisotropic etching. In this embodiment, in the second-type first field effect transistor formation region 10b', the silicided regions on the upper surface of the semiconductor substrate 2 are silicide regions, such as source, drain and gate regions. Since it is covered by the oxide film, the non-silicided region on the upper surface of the semiconductor substrate 2 is a non-silicide region. In the above-mentioned step S42, after the region with the silicide block 30 is removed, a region on the upper surface of the semiconductor substrate 2 covered by an oxide film is formed, so it is also a non-silicide region. Among them, the non-silicide region functions as a ballast resistor. Therefore, forming the silicide block 30 at a position away from the edge of the second-type P-type region 4' can suppress the diffusion of impurities in the second-type P-type region 4' to the non-silicide region.

Please refer to FIG. 18 and FIG. 21, in another embodiment of the present invention, next, the conductive layer or the electrodes in the second type first field effect transistor formation region 10b' and the second field effect transistor formation region 20b, An interlayer insulating film is formed on the wiring. Then, dry etching is used to form contact holes, and the contact holes can be used to respectively connect the electrodes of the source, the drain, the gate and the base body. In this embodiment, a barrier metal is formed on the inner wall surface of the contact hole to prevent silicide such as nickel silicide from being exposed to the environment of fluorine-based compounds and fluorine (F) when filling the contact hole with tungsten (W). middle. Wherein, the barrier metal is, for example, a thin film made of titanium (Ti) or titanium nitride (TiN), and can be formed by sputtering or chemical vapor deposition. The film thickness of the barrier metal may be, for example, 10 nm to 15 nm. After the barrier metal is formed, the contact is formed by filling the contact hole with tungsten (W) or copper (Cu), and the source, drain, and gate are formed by laying metal wiring on the upper surface of the contact of each electrode. The semiconductor device 1 according to this embodiment is manufactured through the above process flow.

Referring to FIG. 1, FIG. 12 and FIG. 21, in another embodiment of the present invention, next, in the manufacturing process, a non-silicide region is formed between the second-type P-type region 4' and the gate electrode G, And the non-silicide region can be used as a ballast resistor. Wherein, the silicide block 30 is formed at a position away from the edge of the type II P-type region 4'. Therefore, the non-silicide region is also formed at a position away from the second-type P-type region 4'. Therefore, it is possible to suppress the diffusion of impurities in the type II P-type region 4' to the non-silicide region.

Please refer to Fig. 21, in another embodiment of the present invention, then, the function of the ballast resistor in a type of first field effect transistor 10 (ESD protection circuit) will be described below, wherein a type of first field effect transistor 10 (ESD protection circuit) The tube 10 comprises a type II electrostatic discharge protection zone 8'. It is assumed that multiple ESD protection circuits (GGNMOS) are connected to the same input and output pad, and multiple ESD protection circuits (GGNMOS) are connected in parallel. When each ESD protection circuit is not provided with a non-silicide region, that is, when the ballast resistor in this embodiment is not provided, a large current may only flow through a specific ESD protection circuit. In this case, a plurality of ESD protection circuits cannot operate, and a large current flows through the ESD protection circuits capable of operating at a low voltage, thus possibly causing damage to a part of the ESD protection circuits.

Please refer to FIG. 21, in another embodiment of the present invention, in the case that each ESD protection circuit has a ballast resistor, the current flowing through the input and output pads in the semiconductor device can be evenly flowed to the parallel connected multiple An ESD protection circuit, thereby suppressing the voltage drop of the potential of the input and output pads, and enabling all the ESD protection circuits to work normally. In addition, when this embodiment is applied to an analog circuit, it can also have AC characteristics with sufficient margin for various specifications.

Please refer to FIG. 1 to FIG. 21, the manufacturing method of the semiconductor device involved in multiple embodiments of the present invention, the semiconductor device forms a first field effect transistor with an electrostatic discharge protection region and a second field effect transistor on a semiconductor substrate . In the present invention, the manufacturing method of the semiconductor device includes: a first-type region forming step, by implanting first-type impurities into the semiconductor substrate, forming the first field effect transistor in the region where the first field effect transistor is formed. A first-type region is formed on the drain side of the formation region, and first-type regions are formed on the source side and the drain side of the second field effect transistor formation region, which is the region where the second field effect transistor is formed, respectively. In the gate electrode forming process, gate electrodes G are respectively formed in the first field effect transistor formation region and the second field effect transistor formation region. and an electrostatic discharge protection region forming step, implanting a second type impurity whose polarity is opposite to that of the first type impurity into a part of the first type region of the first field effect transistor formation region, forming an interface whose position is smaller than that of the first type The first-type region is shallow and the second-type region has a polarity opposite to that of the first-type region, thereby forming the electrostatic discharge protection region in the first field effect transistor forming region.

Please refer to FIG. 1 to FIG. 21 , according to the semiconductor device manufacturing method of the present invention, in the process of forming the first-type region in the second field effect transistor formation region, the drain in the first field effect transistor formation region The first-type impurity is injected into the specified area on the side to form the first-type area in the electrostatic discharge protection area of the first field effect transistor. As a result, an electrostatic discharge protection region can be formed on the first field effect transistor without newly adding a mask or a manufacturing process. That is, an electrostatic discharge protection area can be formed in the first field effect transistor without increasing the manufacturing cost, and avalanche breakdown is easily caused in the PN junction (the interface between the first type area and the second type area) in the electrostatic discharge protection area , thereby manufacturing a semiconductor device in which the start voltage of the field effect transistor is lowered.

Please refer to FIG. 1 to FIG. 21 , the manufacturing method of the semiconductor device involved in the present invention has a silicide block forming process, in the first field effect transistor forming region, in the width direction of the semiconductor substrate A silicide block is formed between the gate electrode and the first-type region away from the edge of the first-type region.

Please refer to FIG. 1 to FIG. 21, according to the manufacturing method of the semiconductor device involved in the present invention, in the first field effect transistor formation region, between the gate electrode and the first type region in the width direction of the semiconductor substrate The silicide blocks are formed in a manner away from the edge portion of the first-type region. Accordingly, it is possible to suppress the diffusion of impurities contained in the first-type region to the lower portion of the silicide block. Therefore, the yield in the manufacture of the semiconductor device can be improved.

Referring to FIGS. 1 to 21 , in the semiconductor device and its manufacturing method according to the present invention, the first-type region forming step is a step before the gate electrode forming step. Accordingly, it is possible to form a first-type region having a deep junction without considering penetration by ion implantation of polysilicon during formation of the gate electrode.

The embodiments of the present invention disclosed above are only used to help explain the present invention. The examples do not exhaust all details nor limit the invention to the particular examples described. Obviously, many modifications and variations can be made based on the contents of this specification. This description selects and specifically describes these embodiments in order to better explain the principle and practical application of the present invention, so that those skilled in the art can well understand and utilize the present invention. The invention is to be limited only by the claims, along with their full scope and equivalents.

Claims (10)

1. A method of manufacturing a semiconductor device in which a first field-effect transistor and a second field-effect transistor having an electrostatic discharge protection region are formed over a semiconductor substrate, comprising:

a first type region forming step of forming a first type region on a drain side of a first field effect transistor forming region, which is a region where the first field effect transistor is formed, and on a source side and a drain side of a second field effect transistor forming region, which is a region where the second field effect transistor is formed, by implanting a first type impurity into the semiconductor substrate;

a gate electrode forming step of forming a gate electrode in the first field-effect transistor forming region and the second field-effect transistor forming region, respectively; and

and forming an electrostatic discharge protection region by implanting a second type impurity into a part of the first type region of the first field effect transistor forming region to form a second type region, wherein the second type impurity has opposite polarity to the first type impurity, the interface position of the second type region is shallower than that of the first type region, and the polarity of the second type region is opposite to that of the first type region so as to form the electrostatic discharge protection region in the first field effect transistor forming region.

2. The method according to claim 1, wherein the method comprises a step of forming a silicide block in the first field effect transistor formation region, wherein the silicide block is located between the gate electrode and the first type region, and the silicide block is formed on a side away from an edge portion of the first type region.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the silicide blocks are distributed in a width direction of the semiconductor substrate.

4. The method of manufacturing a semiconductor device according to claim 2, wherein after the gate electrode is formed, a sidewall of the gate electrode is oxidized to form a sidewall.

5. The method of manufacturing a semiconductor device according to claim 4, wherein the silicide formation step is performed before the formation of the side wall.

6. The method according to claim 1, wherein the first-type region forming step is performed before the gate electrode forming step is performed.

7. The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode forming step is performed before the electrostatic discharge protection region forming step is performed.

8. The method according to claim 1, wherein in the gate electrode forming step, a gate oxide film is formed over the semiconductor substrate, and the gate electrode is formed over the gate oxide film.

9. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is subjected to an annealing treatment before the first-type region forming process is performed.

10. The method for manufacturing a semiconductor device according to claim 1, wherein an impurity concentration of the first type region is higher than a channel impurity concentration of the gate electrode at the same depth.

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