CN116169027A - Manufacturing method of semiconductor device - Google Patents

Abstract

The invention provides a method for manufacturing a semiconductor device. In the manufacturing method, after the first grid electrode is formed on the surface of the first doped region of the semiconductor substrate, a first photoresist layer is covered on the semiconductor substrate, a first through hole and a first weak blocking photoresist are formed in the first photoresist layer, when the first photoresist layer is used for carrying out second doping type ion implantation, the dosage of the dopant which is implanted into the first doped region through the first through hole is larger and is used for forming a heavily doped first source drain region and a heavily doped second source drain region, the dosage of the dopant which is implanted into the first doped region through the first weak blocking photoresist is smaller and is used for forming a lightly doped first LDD region and a lightly doped second LDD region, so that the source drain region and the LDD region of the MOS device are formed only by carrying out one ion implantation, the production cost of a semiconductor device comprising the MOS device is reduced, and the production period is shortened.

Description

Manufacturing method of semiconductor device

technical field

The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device.

Background technique

With the development of semiconductor process technology, the integration level of integrated circuits increases, and the feature size of MOSFETs, that is, MOS devices, shrinks. However, as the feature size shrinks to sub-micron, the hot carrier injection effect becomes serious. To this end, the industry has added a lightly doped LDD (Lightly Doped Drain) region to the drain (also at the source) of traditional MOS devices to improve the peak electric field in the drain depletion region of the device, thus weakening the hot carrier injection effect .

In order to add an LDD region to a MOS device, in the existing process, after forming the gate of the MOS device and before forming a spacer on the sidewall of the gate, a lightly doped implant is performed through a self-aligned process to form the gate of the MOS device. A lightly doped region is formed in the substrate on both sides of the gate, and after the formation of the sidewall, a heavily doped implant is performed through a self-alignment process to form a source region and a drain region on both sides of the gate, respectively, The lightly doped region at the periphery of the source region is adjacent to the source region and extends below the gate dielectric layer to form an LDD region at the source end, and the lightly doped region at the periphery of the drain region is adjacent to the The drain region extends below the gate dielectric layer to form an LDD region at the drain end. This process uses two implants to form the source region, drain region and LDD region of the same MOS device, the process cost is high, and the production cycle is very long, especially when different types of MOS devices need to be formed on the substrate, the process cost and production The cycle problem is more prominent, so an improved process that can reduce the process cost and shorten the production cycle is required.

Contents of the invention

In order to reduce the process cost of a semiconductor device including MOS devices and shorten the production cycle, the invention provides a method for manufacturing a semiconductor device.

The manufacturing method of the semiconductor device provided by the present invention comprises:

providing a semiconductor substrate comprising a first doped region having a first doping type;

forming a first gate on the surface of the first doped region;

Cover the first photoresist layer on the semiconductor substrate, and form first through holes respectively located on both sides of the first gate in the first photoresist layer, so as to reduce the through the thickness of the first photoresist layer between the hole and the first gate to respectively form first weak blocking photoresist on both sides of the first gate;

Using the first photoresist layer as a mask, the second dopant type ion implantation is performed, wherein part of the dopant is implanted into the first doped region through the first through hole, and part of the dopant is implanted into the first doped region through the first through hole. implanting the first weakly blocking photoresist into the first doped region; and

performing annealing, forming a first source-drain region and a second source-drain region on both sides of the first gate, and forming first LDDs adjacent to the first source-drain region on both sides of the first gate region and a second LDD region adjacent to the second source and drain region.

Optionally, forming the first through hole and the first weakly blocking photoresist in the first photoresist layer includes:

A photomask is provided, the photomask has a light-shielding area, a semi-shielding area and a light-transmitting area;

Using the photomask to expose the first photoresist layer, wherein part of the first photoresist layer corresponds to the light-shielding area without being exposed to light, and part of the first photoresist layer corresponds to the semi-shield area While part of the depth is sensitive to light, part of the first photoresist layer is corresponding to the light-transmitting region and all of the depth is sensitive to light; and

Developing is performed to remove the photosensitive portion of the first photoresist layer to form the first through hole and the first weak blocking photoresist.

Optionally, the mask includes a transparent substrate and a light-shielding layer and a semi-shielding layer formed on one side of the transparent substrate, the light-shielding layer is used to prevent incident light from passing through, and the area where the light-shielding layer is formed is the The light-shielding area, the semi-shading layer allows a part of incident light to pass through, the area forming the semi-shading layer is the semi-shielding area, and the transparent substrate area not covered by the light-shielding layer and the semi-shading layer is the light-transmitting region.

Optionally, after forming the first source-drain region, the second source-drain region, the first LDD region and the second LDD region, the manufacturing method further includes: The side walls of the poles respectively form side walls.

Optionally, the first doping type is P-type, and the second doping type is N-type.

Optionally, the energy of the N-type implantation is 20KeV˜50KeV, and the implantation dose is 2E15cm ⁻² ˜8E15cm ⁻² .

Optionally, when ion implantation of the second doping type is performed, the first gate is exposed or covered by the first photoresist layer.

Optionally, the semiconductor substrate further includes a second doped region having a second doping type, and before covering the first photoresist layer on the semiconductor substrate, the manufacturing method further includes A second gate is formed on the surface of the second doping region; when the second doping type ion implantation is performed, the first photoresist layer covers the second doping region.

Optionally, after the ion implantation of the second doping type is completed, the manufacturing method further includes:

Cover the second photoresist layer on the semiconductor substrate, and form second through holes respectively located on both sides of the second gate in the second photoresist layer, so as to reduce the through the thickness of the second photoresist layer between the hole and the second grid to form second weakly blocking photoresist on both sides of the second grid; and

Using the second photoresist layer as a mask, the ion implantation of the first doping type is performed, wherein part of the dopant is implanted into the second doped region through the second through hole, and part of the dopant is implanted into the second doping region through the second through hole. implanting the second weakly blocking photoresist into the second doped region;

performing annealing, respectively forming a third source and drain region and a fourth source and drain region on both sides of the second gate, and forming a third LDD adjacent to the third source and drain region on both sides of the second gate region and a fourth LDD region adjacent to the fourth source and drain region.

Optionally, the ion implantation energy of the first doping type is 15KeV˜50KeV, and the implantation dose is 1E15cm ⁻² ˜6E15cm ⁻² .

In the manufacturing method of the semiconductor device provided by the present invention, after the first gate dielectric layer and the first gate are formed on the surface of the first doped region of the semiconductor substrate, the first photoresist layer is covered on the semiconductor substrate, and the A first through hole and a first weak blocking photoresist are formed in the first photoresist layer, and when the first photoresist layer is used for ion implantation of the second doping type, the first through hole is implanted into the first through hole. The dopant dose of the doped region is relatively large, which is used to form the heavily doped first source and drain regions and the second source and drain region, and the dopant implanted into the first doped region through the first weakly blocking photoresist The impurity dose is small, which is used to form the lightly doped first LDD region and the second LDD region. Therefore, only one ion implantation is required to form the source and drain regions and the LDD region of the MOS device, which helps to reduce the cost of the MOS device. The production cost of the semiconductor device is reduced, and the production cycle is shortened.

Description of drawings

FIG. 1 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

2 is a schematic cross-sectional structure diagram after forming a first gate in the manufacturing method of the semiconductor device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a cross-sectional structure after forming a first photoresist layer in a method for fabricating a semiconductor device according to an embodiment of the present invention.

4 is a schematic cross-sectional view of a photomask in a method for fabricating a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional structure diagram of the first photoresist layer after patterning in the manufacturing method of the semiconductor device according to an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional structure diagram of ion implantation of a second doping type in the method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a schematic cross-sectional structure diagram after removing the first photoresist layer in the manufacturing method of the semiconductor device according to an embodiment of the present invention.

8 is a schematic diagram of a cross-sectional structure after ion implantation of the first doping type in the manufacturing method of the semiconductor device according to an embodiment of the present invention.

FIG. 9 is a schematic cross-sectional structure diagram after annealing in the manufacturing method of the semiconductor device according to an embodiment of the present invention.

FIG. 10 is a schematic cross-sectional structure diagram after sidewalls are formed in the manufacturing method of the semiconductor device according to an embodiment of the present invention.

Detailed ways

The manufacturing method of the semiconductor device of the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly illustrate the embodiments of the present invention, and the embodiments of the present invention should not be considered limited to those shown in the drawings to show the specific shape of the region.

It should be noted that the terms "first", "second" and the like hereinafter are used to distinguish between similar elements, and it should be understood that these terms so used can be replaced under appropriate circumstances. If the methods described herein include a series of steps, and the order in which the steps are presented herein is not necessarily the only order in which the steps are performed, some described steps may be omitted and/or some other steps not described herein may be replaced. added to the method. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a structure in the figures is inverted or otherwise positioned differently (eg, rotated), the exemplary term "on" could also include "below" and other orientational relationships.

Embodiments of the present invention relate to a manufacturing method of a semiconductor device. The semiconductor device may be any device including a MOS device. The semiconductor device may include one or more MOS devices, and the structures and performances of the multiple MOS devices may be different. For example, the semiconductor device may include at least one of an NMOS transistor, a PMOS transistor, a ZMOS (Zero Threshold Voltage Field Effect Transistor) transistor, and a BiMOS (Bipolar Metal Oxide Semiconductor) transistor, and the MOS device may be a high voltage ( HV) devices or low voltage (LV) devices. Multiple MOS devices in the semiconductor device can be integrated on the same semiconductor substrate, and other electronic components, such as flash memory or other suitable components, can also be integrated on the same semiconductor substrate.

FIG. 1 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. 2 is a schematic cross-sectional structure diagram after forming a first gate in the manufacturing method of the semiconductor device according to an embodiment of the present invention. Referring to FIGS. 1 and 2 , in step S1 , a semiconductor substrate 100 including a first doped region 110 having a first doping type is provided.

The semiconductor substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a silicon-germanium-on-insulator substrate or a III-V compound substrate ( For example, a gallium nitride substrate or a gallium arsenide substrate), etc., or other substrates known to those skilled in the art for carrying semiconductor components. The following description will be made by taking the semiconductor substrate 100 as a silicon substrate as an example.

The semiconductor substrate 100 may have a first doping type. The first doping type is, for example, P-type doping (such as doping with boron or indium) or N-type doping (such as doping with phosphorus or arsenic). As shown in FIG. 2 , a trench isolation structure is formed in the semiconductor substrate 100 , and the trench isolation structure extends from the surface of the semiconductor substrate 100 to the inside of the semiconductor substrate 100 and defines a plurality of active regions. The trench isolation structure may be deep trench isolation (DTI) or shallow trench isolation (STI), and this embodiment is, for example, shallow trench isolation (STI). A P-type doped or N-type doped well region may be formed in the active region. Subsequently, a MOS device can be formed on the surface of the active region or the surface of the well region.

As shown in FIG. 2 , exemplary, the semiconductor substrate 100 includes at least one first doped region 110 , and the first doped region 110 is, for example, an active region or a well region formed in an active region. The first doped region 110 has, for example, P-type doping (marked as P), and NMOS transistors or other N-type devices can be formed in the surface region of the first doped region 110 . Optionally, the semiconductor substrate 100 further includes at least one second doped region 120 , the doping type of the second doped region 120 is opposite to that of the first doped region 110 , for example. The second doped region 120 has N-type doping, for example, and a PMOS transistor or other P-type devices can be formed in the surface region of the second doped region 120 . In this embodiment, the first doped region 110 is adjacent to the second doped region 120 , and the top of the second doped region 120 is isolated from the top of the first doped region 110 by shallow trench isolation (STI). However, in other embodiments, the first doped region 110 and the second doped region 120 may not be adjacent to each other.

Referring to FIG. 1 and FIG. 2 , in step S2 , a first gate NG is formed on the surface of the first doped region 110 . The first gate dielectric layer 101 is, for example, formed between the first gate NG and the semiconductor substrate 100 . In this embodiment, the second gate PG and the second gate dielectric layer 102 between the second gate PG and the semiconductor substrate 100 may also be formed on the surface of the second doped region 120 . An oxide layer may be formed on the surface of the semiconductor substrate 100 around the first gate NG and the second gate PG. The first gate dielectric layer 101 and the second gate dielectric layer 102 may include silicon oxide (SiO ₂ ), silicon oxynitride (SiON), hafnium oxide (HfO) or other suitable materials. The first gate NG and the second gate PG may include doped polysilicon, undoped polysilicon or metal, wherein the undoped polysilicon can be implanted with the first doping type ion implantation or the second doping type ion implantation is exposed to form doping. In another embodiment, a hard mask layer may be formed on top surfaces of the first gate NG and the second gate PG.

Referring to FIG. 1 and FIG. 3 , in step S3 , the first photoresist layer PR is covered on the semiconductor substrate 100 . In this embodiment, the first photoresist layer PR is, for example, a positive photoresist. The first photoresist layer PR covers the first gate NG, the second gate PG and the surrounding semiconductor substrate 100 . Step S3 also performs patterning on the first photoresist layer PR, so as to form first through holes respectively located on both sides of the first gate NG in the first photoresist layer PR, and reduce the The thickness of the first photoresist layer PR between the hole and the first grid NG is penetrated to form a first weak blocking photoresist on both sides of the first grid NG. The patterning process may specifically include the following process: First, as shown in FIG. 4 , taking a positive photoresist as an example, a photomask 200 is provided, and the photomask 200 has a light-shielding area 200a, a semi-shielding area 200b and a light-transmitting area. Region 200c. Exemplarily, the photomask 200 includes a transparent substrate and a light-shielding layer and a semi-shielding layer formed on one side of the transparent substrate. The light-shielding layer and the semi-shielding layer include chrome or other suitable material of the dark part, and the light-shielding layer is used to prevent incident light from passing through, the area where the light-shielding layer is formed is the light-shielding region 200a, the light transmittance of the semi-light-shielding layer is greater than that of the light-shielding layer, and the semi-light-shielding layer allows A part of the incident light (for example greater than 0 and less than 100% of the incident light) passes through, the area where the semi-shading layer is formed is the semi-shielding area 200b, and the area of the transparent substrate that is not covered by the light-shielding layer and the semi-shading layer is the light-transmitting region 200c; then, the first photoresist layer PR is exposed using the photomask 200, wherein the light-shielding region 200a, the semi-light-shielding region 200b and the light-transmitting region 200c respectively correspond to the differences of the first photoresist layer PR. After exposure, the part of the first photoresist layer PR corresponding to the light-shielding region 200a is basically not exposed to light, the part of the first photoresist layer PR corresponding to the semi-shielding region 200b is deeply sensitive to light, and the part of the first photoresist layer PR corresponding to the light-shielding region 200c Part of the first photoresist layer PR is photosensitive at all depths; then, developing is performed to remove the photosensitive part of the first photoresist layer PR, wherein, in the first photoresist layer PR region that is photosensitive to a partial depth, the first The thickness of a photoresist layer PR is reduced to form a first weak blocking photoresist, and the first photoresist layer PR is removed to form a through hole in the entire depth sensitive area of the first photoresist layer PR.

As shown in FIG. 5, after the above-mentioned patterning process, the first through holes 10 located on both sides of the first gate NG are formed in the first photoresist layer PR, so as to facilitate source and drain injection; and, part of the first photoresist The thickness of the layer PR is reduced to form a first weakly blocking photoresist 20. In this embodiment, the first weakly blocking photoresist 20 is located between each first through hole 10 and the first gate NG. The ability of the first photoresist layer PR and the first weakly blocking photoresist 20 to block the passage of ions is reduced, and this embodiment is used for LDD implantation.

Step S3 may also use other processes to form the first through hole 10 and the first weak blocking photoresist 20 in the first photoresist layer PR. For example, in one embodiment, step S3 includes the following process: firstly, a bottom photoresist layer (positive photoresist) is formed, and a photomask is used to expose the bottom photoresist layer to form the first through hole The bottom photoresist layer in the region is photosensitive; then, an upper photoresist layer is coated on the bottom photoresist layer, and another photomask is used to expose the upper photoresist layer, so that the first through hole The upper photoresist layer of the forming region and the first weakly blocking photoresist forming region is exposed (the bottom photoresist layer is not exposed this time); after that, developing is performed to remove the first through hole forming region. the upper photoresist layer and the bottom photoresist layer, and remove the upper photoresist layer in the region where the first weak blocking photoresist is formed, so that the bottom photoresist layer and the upper photoresist layer The first through hole and the first weak blocking photoresist are formed in the stack.

When performing the above patterning treatment, the first photoresist layer PR located on the top surface of the first grid NG may remain, or may be removed to expose the top surface of the first grid NG as required. In this embodiment, since the types of MOS devices to be formed in the second doped region 120 and the first doped region 110 are different, and the doping types of the source and drain regions are different, the first photoresist located in the first doped region 110 When the above patterning process is performed on the layer PR, the second doped region 120 is shielded by the light shielding region 200a on the mask 200, so that after the patterning process, the first photoresist layer PR located in the second doped region 120 is not Sensitive and retained.

FIG. 6 is a schematic cross-sectional structure diagram of ion implantation of a second doping type in the method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to Fig. 1 and Fig. 6, in step S4, the second doping type ion implantation 30 (for example, N-type ion implantation in this embodiment) is performed using the first photoresist layer PR after the above-mentioned patterning treatment as a mask, Wherein, part of the dopant is implanted into the first doped region 110 through the first through holes 10 on both sides of the first gate NG to respectively form the first source-drain implantation region 111 and the second source-drain implantation region 112 , and partly Dopants are implanted into the first doped region 110 through the first weakly blocking photoresist 20 on both sides of the first gate NG to form a first LDD implantation region 113 and a second LDD implantation region 114 respectively, wherein the first LDD implantation region 114 is located at the first gate The first source-drain injection region 111 on the same side of the electrode NG is adjacent to the first LDD injection region 113, the first source-drain injection region 111 is located on the side of the first LDD injection region 113 away from the first gate NG, and is located on the first gate NG. The second source-drain injection region 112 on the same side of the gate NG is adjacent to the second LDD injection region 114 , and the second source-drain injection region 112 is located on a side of the second LDD injection region 114 away from the first gate NG.

When the second doping type ion implantation 30 is performed, since the first weakly blocking photoresist 20 blocks part of the dopant from passing through, the dopant dose implanted into the first doped region 110 through the first through hole 10 greater than the dopant dose injected into the first doped region 110 through the first weak blocking photoresist 20, the doping concentration of the first source-drain implanted region 111 and the second source-drain implanted region 112 are substantially the same, and the first LDD implanted region 113 and the second LDD implantation region 114 have substantially the same doping concentration, and the doping concentration of any one of the first source-drain implantation region 111 and the second source-drain implantation region 112 is greater than that of the first LDD implantation region 113 and the second LDD implantation region 113 and the second LDD implantation region 113. The doping concentration of any one of the implanted regions 114 . According to the setting of the thickness of the first weak blocking photoresist 20 and the setting of ion implantation conditions, the doping concentration of the first LDD implantation region 113 and the second LDD implantation region 114 can be adjusted. Optionally, the dopant used for the second doping type ion implantation is, for example, phosphorus, the implantation energy is, for example, 20KeV˜50KeV, and the implantation dose is, for example, 2E15cm ⁻² ˜8E15cm ⁻² . After the ion implantation 30 of the second doping type is completed, the first photoresist layer PR is removed, and the obtained structure is shown in FIG. 7 .

Optionally, the manufacturing method may also include the process of forming a source-drain implant region and an LDD implant region of the first doping type in the second doped region 120, in order to reduce costs and shorten the production cycle, and The impurity region 110 forms the first source-drain implantation region 111, the second source-drain implantation region 112, the first LDD implantation region 113, and the second LDD implantation region 114 by one ion implantation (i.e., the second doping type ion implantation 30) similarly A source-drain implantation region and an LDD implantation region having the first doping type (for example, P-type ion implantation in this embodiment) can also be formed in the second doping region 120 by one ion implantation (implantation of the first doping type), Specifically, the following process may be included: first, cover the second photoresist layer (not shown) on the semiconductor substrate 100; second through holes, and reduce the thickness of the second photoresist layer between each of the second through holes and the second gate PG to form second weak barriers on both sides of the second gate PG. Photoresist (not shown); then, using the second photoresist layer as a mask, perform ion implantation of the first doping type (for example, P-type ion implantation, such as B implantation or BF ₂ implantation), wherein, part Dopants are implanted into the second doped region 120 through the second through holes on both sides of the second gate PG to form a third source-drain implant region 121 and a fourth source-drain implant region 122 (refer to FIG. 8 ). Part of the dopant is implanted into the second doped region 120 through the second weakly blocking photoresist on both sides of the second gate PG to form a third LDD implantation region 123 and a fourth LDD implantation region 124 respectively, wherein The third source-drain injection region 121 on the same side of the second gate PG is adjacent to the third LDD injection region 123, and the third source-drain injection region 121 is located on the side of the third LDD injection region 123 away from the second gate PG, and is located at The fourth source-drain injection region 122 on the same side of the second gate PG is adjacent to the fourth LDD injection region 124 , and the fourth source-drain injection region 122 is located on a side of the fourth LDD injection region 124 away from the second gate PG. Optionally, the ion implantation energy of the first doping type is, for example, 15KeV˜50KeV, and the implantation dose is, for example, 1E15cm ⁻² ˜6E15cm ⁻² . When performing ion implantation of the first doping type, since the second weakly blocking photoresist will block part of the dopant passing through, the dopant implanted into the second doping region 120 through the second through hole The impurity dose is greater than the dopant dose implanted into the second doped region 120 through the second weak blocking photoresist, the doping concentration of the third source-drain implanted region 121 and the fourth source-drain implanted region 122 are basically the same, and the second The doping concentration of the third LDD implantation region 123 and the fourth LDD implantation region 124 is substantially the same, and the doping concentration of any one of the third source-drain implantation region 121 and the fourth source-drain implantation region 122 is greater than that of the third LDD implantation region 123 and the doping concentration of any one of the fourth LDD implantation regions 124 . After the ion implantation of the first doping type is completed, the second photoresist layer is removed, and the obtained structure is shown in FIG. 8 .

FIG. 9 is a schematic cross-sectional structure diagram after annealing in the manufacturing method of the semiconductor device according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 9, in step S5, annealing is performed to drive in and stabilize the dopant ions implanted into the first doped region 110 and the second doped region 120, respectively on both sides of the first gate NG. A first source and drain region 111a and a second source and drain region 112a are formed, and a first LDD region 113a adjacent to the first source and drain region 111a and a first LDD region 113a adjacent to the second source and drain region are respectively formed on both sides of the first gate NG. The second LDD region 114a of 112a. In addition, in this embodiment, a third source-drain region 121a and a fourth source-drain region 122a are respectively formed on both sides of the second gate PG, and a third source-drain region adjacent to the third source-drain region is formed on both sides of the second gate PG. The third LDD region 123a of the region 121a and the fourth LDD region 124a adjacent to the fourth source and drain region 122a. In another embodiment, the first source and drain region 111a, the second source and drain region 112a, the first LDD region 113a and the second LDD region 114a can also be formed by annealing first, and then the ion implantation of the above-mentioned first doping type is performed. and annealing to form a third source and drain region 121a, a fourth source and drain region 122a, a third LDD region 123a and a fourth LDD region 124a. For example, the first source and drain region 111a is a source region, and the second source and drain region 112a is a drain region; or the first source and drain region 111a is a drain region, and the second source and drain region 112a is a source region.

FIG. 10 is a schematic cross-sectional structure diagram after sidewalls are formed in the manufacturing method of the semiconductor device according to an embodiment of the present invention. Referring to FIG. 10 , optionally, spacers 130 may be further formed on the sidewalls of the first gate NG and the second gate PG to protect the first gate NG and the second gate PG. The sidewall 130 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the sidewall 130 may be formed as a single layer or multiple layers. In this embodiment, the first LDD region 113a extends from below the spacer 130 on the same side of the first gate NG as the first LDD region 113a to below the first gate dielectric layer 101, and the second LDD region 114a extends from the side of the second gate NG. The LDD region 114a extends from under the sidewall 130 on the same side of the first gate NG to under the first gate dielectric layer 101, and the third LDD region 123a extends from the sidewall on the same side of the second gate PG as the third LDD region 123a. 130 extends below the second gate dielectric layer 102 , and the fourth LDD region 124 a extends from below the spacer 130 on the same side of the second gate PG as the fourth LDD region 124 a to below the second gate dielectric layer 102 .

In this embodiment, through the above process, the first gate NG formed on the surface of the first doped region 110 and the first source-drain region 111a, the second source-drain region 112a, the second An LDD region 113a and a second LDD region 114a form an NMOS transistor. The second gate PG formed on the surface of the second doped region 120 and the third source-drain region 121a, the fourth source-drain region 122a, the third LDD region 123a and the fourth LDD region distributed on both sides of the second gate PG 124a constitutes a PMOS transistor. In the above process, only one ion implantation is required to form the first source-drain region 111a, the second source-drain region 112a, the first LDD region 113a, and the second LDD region 114a to form the third source-drain region 121a, the fourth source-drain region 121a, and the fourth source-drain region 121a. 122a, the third LDD region 123a and the fourth LDD region 124a only need to be implanted once, which helps to reduce the production cost of semiconductor devices including MOS devices and shorten the production cycle. For example, the third source and drain region 121a is a source region, and the fourth source and drain region 122a is a drain region; or the third source and drain region 121a is a drain region, and the fourth source and drain region 122a is a source region.

The above description is only a description of the preferred embodiments of the present invention, and is not any limitation to the scope of rights of the present invention. Anyone skilled in the art can use the methods and technical contents disclosed above to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a first doping region with a first doping type;

forming a first grid electrode on the surface of the first doped region;

covering a first photoresist layer on the semiconductor substrate, forming first through holes respectively positioned at two sides of the first grid electrode in the first photoresist layer, and reducing the thickness of the first photoresist layer positioned between each first through hole and the first grid electrode so as to respectively form first weak blocking photoresist at two sides of the first grid electrode;

performing second doping type ion implantation by using the first photoresist layer as a mask, wherein part of dopants are implanted into the first doping region through the first through hole, and part of dopants are implanted into the first doping region through the first weak blocking photoresist; and

and annealing is carried out, a first source drain region and a second source drain region are respectively formed on two sides of the first grid electrode, and a first LDD region adjacent to the first source drain region and a second LDD region adjacent to the second source drain region are respectively formed on two sides of the first grid electrode.

2. The method of claim 1, wherein forming the first via and the first weak blocking photoresist in the first photoresist layer comprises:

providing a photomask, wherein the photomask is provided with a shading area, a semi-shading area and a light transmission area;

exposing the first photoresist layer by using the photomask, wherein part of the first photoresist layer corresponds to the shading area and is not sensitized, part of the first photoresist layer corresponds to the semi-shading area and is partially sensitized in depth, and part of the first photoresist layer corresponds to the light transmitting area and is sensitized in full depth; and

and developing to remove the photosensitive part of the first photoresist layer so as to form the first through hole and the first weak blocking photoresist.

3. The method of claim 2, wherein the mask comprises a transparent substrate, and a light shielding layer and a semi-light shielding layer formed on a side surface of the transparent substrate, the light shielding layer is used for preventing incident light from passing through, a region where the light shielding layer is formed is the light shielding region, the semi-light shielding layer allows a part of the incident light to pass through, a region where the semi-light shielding layer is formed is the semi-light shielding region, and a region of the transparent substrate uncovered by the light shielding layer and the semi-light shielding layer is the light transmitting region.

4. The method of manufacturing of claim 1, wherein after forming the first source drain region, the second source drain region, the first LDD region, and the second LDD region, the method further comprises:

and forming side walls on the side walls of the first grid respectively.

5. The method of claim 1, wherein the first doping type is P-type and the second doping type is N-type.

6. The method of claim 1, wherein the second doping type has an ion implantation energy of 20 KeV-50 KeV and an implantation dose of 2E15cm ^-2 ～8E15cm ^-2 。

7. The method of claim 1, wherein the first gate is exposed or covered by the first photoresist layer when the second doping type ion implantation is performed.

8. The method of any of claims 1-7, wherein the semiconductor substrate further comprises a second doped region having a second doping type, the method further comprising forming a second gate on a surface of the second doped region prior to overlaying the first photoresist layer on the semiconductor substrate; the first photoresist layer covers the second doped region when the second doping type ion implantation is performed.

9. The method of claim 8, wherein after completing the second doping type ion implantation, the method further comprises:

covering a second photoresist layer on the semiconductor substrate, forming second through holes respectively positioned at two sides of the second grid electrode in the second photoresist layer, and reducing the thickness of the second photoresist layer positioned between each second through hole and the second grid electrode so as to respectively form second weak blocking photoresist at two sides of the second grid electrode; and

performing first doping type ion implantation by using the second photoresist layer as a mask, wherein part of dopants are implanted into the second doping region through the second through hole, and part of dopants are implanted into the second doping region through the second weak blocking photoresist; and

and annealing is carried out, a third source drain region and a fourth source drain region are respectively formed on two sides of the second grid electrode, and a third LDD region adjacent to the third source drain region and a fourth LDD region adjacent to the fourth source drain region are respectively formed on two sides of the second grid electrode.

10. The method of claim 9, wherein the first doping type ion implantation has an energy of 15KeV to 50KeV and an implantation dose of 1E15cm ^-2 ～6E15cm ^-2 。

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