CN116111001B

CN116111001B - Manufacturing method of fingerprint sensing module

Info

Publication number: CN116111001B
Application number: CN202111411691.0A
Authority: CN
Inventors: 黄振明
Original assignee: Powerchip Technology Corp
Current assignee: Powerchip Technology Corp
Priority date: 2021-11-10
Filing date: 2021-11-25
Publication date: 2026-01-23
Anticipated expiration: 2041-11-25
Also published as: TWI780979B; TW202320317A; CN116111001A

Abstract

A method for fabricating fingerprint sensing module includes forming a planarization layer and a photoresist material layer sequentially on a substrate, wherein the substrate includes a pixel region including a photosensitive array and a peripheral region surrounding the pixel region, removing a portion of the photoresist material layer on the pixel region to form a photoresist pattern exposing the planarization layer, removing a portion of the planarization layer on the pixel region to form a patterned planarization layer exposing the substrate, forming an infrared cut-off layer on the photoresist pattern and the pixel region of the substrate, removing the photoresist pattern and the infrared cut-off layer on the photoresist pattern to form an infrared cut-off pattern on the pixel region of the substrate, forming a light shielding layer on the infrared cut-off pattern and on the patterned planarization layer, and patterning the light shielding layer to form a collimation structure layer including a pinhole array on the infrared cut-off pattern and to form a mark pattern on the patterned planarization layer.

Description

Manufacturing method of fingerprint sensing module

Technical Field

The present invention relates to a manufacturing method of an optical sensing element, and more particularly, to a manufacturing method of a fingerprint sensing module.

Background

In order to make the display have a narrow bezel design, the technology of under-screen fingerprint sensing has become a current trend. The fingerprint sensing technology under the screen is to configure the fingerprint sensing module under the display panel of the electronic device. After the electronic device detects that the user touches the display screen, the electronic device controls the display panel to emit light so as to illuminate the surface of the finger of the user. The sensing light is reflected by the finger of the user to enter the fingerprint sensing module below the display panel, and the reflected light is converged on the photosensitive element through the microlenses and the collimating structure, so that the optical image signal can be converted into a digital image signal to obtain the fingerprint image of the user. The collimating structure can comprise a shading material layer with pinholes, so that reflected light can be converged on the photosensitive element through the pinholes and can be absorbed by the shading material to avoid interference between different reflected lights.

However, in the patterning process of forming the light shielding material layer having pinholes, the exposure condition of the light shielding material layer is significantly affected by the thickness thereof. For example, taking an exposure wavelength of about 365nm as an example, the light transmittance of the exposure light is about 70% when the thickness of the light shielding material layer is about 1 μm, but is reduced to about 10% when the thickness of the light shielding material layer is increased to about 1.5 μm. As a result, the difference in the thickness was only 0.5. Mu.m, but the difference in the light transmittance was as high as about 7 times. Therefore, in the process of forming the light shielding material layer, some patterns to be formed may not be well exposed to some areas due to the light transmittance difference caused by the thickness difference, so that the patterns to be formed may not be well formed on the areas in the developing process.

Disclosure of Invention

The invention provides a manufacturing method of a fingerprint sensing module, which enables a shading layer to have approximately the same thickness in different areas of a substrate through the design that the shading layer is formed on an infrared cut-off pattern and a patterned flat layer, so that in the step of patterning the shading layer, a collimation structure layer comprising a pinhole array and a mark pattern can be well formed in different areas (such as a pixel area and a peripheral area) of the substrate.

An embodiment of the invention provides a method for manufacturing a fingerprint sensing module, which includes the following steps. A planarization layer and a photoresist material layer are sequentially formed on a substrate. The substrate comprises a pixel area containing a photosensitive array and a peripheral area surrounding the pixel area. And removing the part of the photoresist material layer on the pixel area to form a photoresist pattern exposing the flat layer. And removing the part of the flat layer on the pixel area to form a patterned flat layer exposing the substrate. An infrared cut-off layer is formed on the photoresist pattern and on the pixel region of the substrate. The photoresist pattern and the part of the infrared cut-off layer on the photoresist pattern are removed to form the infrared cut-off pattern on the pixel area of the substrate. And forming a shading layer on the infrared cut-off pattern and the patterned flat layer. The light shielding layer is patterned to form a collimation structure layer comprising a pinhole array on the infrared cut-off pattern, and a mark pattern is formed on the patterned flat layer.

In some embodiments, the thickness of the ir cut-off pattern is approximately equal to the thickness of the patterned planarization layer on the substrate.

In some embodiments, the infrared cut pattern is spaced apart from the patterned planarization layer by a distance in a direction parallel to the substrate.

In some embodiments, the photoresist pattern includes a bottom surface in contact with the patterned planarization layer and a top surface opposite the bottom surface, and an area of the top surface is greater than an area of the bottom surface.

In some embodiments, the photoresist pattern includes sloped sidewalls, the angle between the sloped sidewalls and the bottom surface being greater than 90 degrees.

In some embodiments, the infrared cut layer is not formed on the sloped sidewalls of the photoresist pattern such that the infrared cut layer includes discontinuous first and second portions. The first portion is formed on the pixel region of the substrate. The second portion is formed on the photoresist pattern.

In some embodiments, the infrared cut layer includes a first portion formed on the pixel region of the substrate and a second portion formed on the photoresist pattern. The first portion is separated from the second portion by a photoresist pattern.

In some embodiments, the photoresist pattern is formed by an exposure process and a first development process, and the patterned planarization layer is formed by an exposure process and a second development process different from the first development process.

In some embodiments, light used by the exposure fabrication process exposes portions of the photoresist material layer and portions of the planarization layer below portions of the photoresist material layer.

In some embodiments, the method further includes forming an additional planarization layer on the ir cut-off pattern and on the patterned planarization layer before forming the light shielding layer.

In view of the above, in the above-mentioned manufacturing method of the fingerprint sensing module, since the light shielding layer is formed on the infrared cut-off pattern and the patterned planarization layer, the thickness of the light shielding layer in different areas (e.g. the pixel area and the peripheral area) of the substrate is approximately the same. In this way, patterns to be formed in different areas of the substrate (e.g., the alignment structure layer including the pinhole array in the pixel region and the mark pattern in the peripheral region) can be well formed in the step of patterning the light shielding layer.

Drawings

Fig. 1 to 7 are schematic cross-sectional views illustrating a manufacturing method of a fingerprint sensing module according to an embodiment of the invention.

Description of the main reference signs

10 Pixel region

20 Wiring area

30 Pad area

40 Cutting track area

100 Substrate

102 Interconnect structure

104 Wiring

106 Connecting pad structure

108 Opening(s)

110 Flat layer

112 Patterning the planarization layer

120 Infrared cut-off layer

120A first part

120B second portion

122 IR cut-off pattern

130 Additional planarization layer

140 Light shielding layer

142 Alignment structure layer

144 Marking pattern

146 Pinhole array

Area A

D distance

PR photoresist pattern

S1 bottom surface

S2. top surface

SW1 sloped sidewall/sidewall

SW2 side wall

Theta is the included angle

Detailed Description

The present invention will be described more fully with reference to the accompanying drawings of this embodiment. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and the following paragraphs will not be repeated.

It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. If an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection, and "electrically connected" or "coupled" may mean that other elements are present between the elements. As used herein, "electrically connected" may include physically connected (e.g., wired) and physically disconnected (e.g., wireless).

As used herein, "about," "approximately," or "substantially" includes reference to values and mean values within an acceptable deviation of the particular values that one of skill in the art would determine, taking into account the particular number of measurements and errors associated with the measurements (i.e., limitations of the measurement system) in question. For example, "about" may mean within one or more standard deviations of the values, or within ±30%, ±20%, ±10%, ±5%. Further, "about," "approximately," or "substantially" as used herein may be used to select a range of acceptable deviations or standard deviations depending on the optical, etching, or other properties, and may be used for all properties without one standard deviation.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this case, the singular includes the plural unless the context indicates otherwise.

Fig. 1 to 7 are schematic cross-sectional views illustrating a manufacturing method of a fingerprint sensing module according to an embodiment of the invention. Fig. 4 (b) is an enlarged view of fig. 4 (a) in the region a. The manufacturing method of the fingerprint sensing module will be illustrated by fig. 1 to 7.

First, referring to fig. 1, a planarization layer 110 is formed on a substrate 100. The substrate 100 includes a pixel region 10 including a photosensitive array and a peripheral region surrounding the pixel region 10 and including a wiring region 20, a pad region 30 and a scribe line region 40.

In some embodiments, the substrate 100 may include a plurality of layers, a plurality of structures, and/or elements formed in a back end of line (BEOL). For example, the substrate 100 may include inter-metal dielectric layers, vias, wiring layers, active (e.g., transistors), and/or passive (e.g., capacitors). As shown in fig. 1, the pixel region 10 of the substrate 100 may include an interconnect structure 102 and active devices and/or passive devices (e.g., active devices and/or passive devices included in a CMOS image sensor) connected to the interconnect structure 102, and the peripheral region of the substrate 100 may include a wiring 104 disposed in the wiring region 20 and a pad structure 106 disposed in the pad region 30.

In some embodiments, the substrate 100 may include multiple layers, multiple structures, and/or elements formed in a front end of line (front end of line, FEOL). For example, the substrate 100 may include an element layer formed on a semiconductor substrate. The device layer may include various devices and an interlayer dielectric layer covering the devices. In some embodiments, the elements may include active elements, passive elements, or a combination thereof (e.g., active elements and/or passive elements included in a CMOS image sensor). For example, the elements may include transistors, capacitors, resistors, diodes, photodiodes, or the like. In some embodiments, the element layer may include gate structures, source/drain regions, isolation structures such as shallow trench isolation structures (shallow trench isolation, STI), and the like. In the element layer, various N-type metal oxide semiconductor (N-TYPE METAL-oxide semiconductor, NMOS) and/or P-type metal oxide semiconductor (P-TYPE METAL-oxide semiconductor, PMOS) elements, such as transistors and memories, etc., that are interconnected with each other may be formed to perform one or more functions. Other elements such as capacitors, resistors, diodes, photodiodes, etc. may also be formed on the semiconductor substrate. The functions of these elements may include memory (memory), processor (processor), sensor (sensor), amplifier (amplifier), power distribution (power distribution), or I/O circuitry (input/output circuit), etc.

The semiconductor substrate may be a bulk semiconductor (bulk semiconductor), a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate may be doped (e.g., doped with a dopant of the P-type or N-type) or undoped. The semiconductor substrate may be a wafer such as a silicon wafer. In general, an SOI substrate is a film layer in which a semiconductor material is formed over an insulating layer. The insulating layer may be, for example, a Buried Oxide (BOX) layer or a silicon oxide layer, or the like. The insulating layer is provided on a silicon substrate or a glass substrate, for example. In some embodiments, the semiconductor substrate may include an elemental semiconductor (element semiconductor) such as silicon or germanium, a compound semiconductor such as silicon carbide (silicon carbide), gallium arsenide (gallium arsenic), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), and indium antimonide (indium antimonide), or an alloy semiconductor such as SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, or a combination thereof.

The substrate 100 may include an opening 108 exposing the pad structure 106, and a planarization layer 110 may be formed on a top surface of the substrate 100 and filled into the opening 108. In some embodiments, the planar layer 110 may be, for example, a light sensitive material. In some embodiments, the planarization layer 110 may be formed on the pixel region 10 of the substrate 100 and the peripheral region including the wiring region 20, the pad region 30, and the scribe line region 40.

Next, referring to fig. 1 and 2, a photoresist pattern PR is formed on the planarization layer 110. In some embodiments, the photoresist pattern PR may be formed, for example, through the following steps. First, a photoresist material layer (not shown) is formed on the planarization layer 110. In some embodiments, a photoresist material layer is formed over the pixel region 10 of the substrate 100 and over the peripheral region including the wiring region 20, the pad region 30, and the scribe line region 40. In some embodiments, the layer of photoresist material may employ a negative photoresist material. Next, a portion of the photoresist material layer over the pixel region 10 of the substrate 100 is removed to form a photoresist pattern PR exposing the planarization layer 110. That is, the photoresist pattern PR is formed over the peripheral region of the substrate 100.

The photoresist pattern PR may include a bottom surface S1 contacting the planarization layer 110 and a top surface S2 opposite to the bottom surface S1. In some embodiments, the top surface S2 of the photoresist pattern PR has an area larger than that of the bottom surface S1. In other words, the photoresist pattern PR may include inclined sidewalls SW1, and an included angle θ between the inclined sidewalls SW1 and the bottom surface S1 is greater than 90 degrees. In some embodiments, in case that the photoresist material layer is a negative photoresist material, the photoresist pattern PR formed after the exposure and development process may have an inverted trapezoid pattern such that an area of the top surface S2 of the photoresist pattern PR is larger than an area of the bottom surface S1.

Then, referring to fig. 2 and 3, a portion of the planarization layer 110 on the pixel region 10 is removed to form a patterned planarization layer 112 exposing the pixel region 10 of the substrate 100. In some embodiments, the patterned planarization layer 112 may be formed, for example, via the following steps. In the exposure process and the first development process for forming the photoresist pattern PR, which are described in the example in which the photoresist material layer uses the negative photoresist material, the portions of the photoresist material layer and the planarization layer 110 over the pixel region 10 of the substrate 100 are not exposed to the light used in the exposure process, so that after the portions of the photoresist material layer over the pixel region 10 of the substrate 100 are removed in the first development process, the portions of the planarization layer 110 over the pixel region 10 may be removed through a second development process different from the first development process. That is, the photoresist pattern PR may be formed through an exposure process and a first developing process, and the patterned planarization layer 112 may be formed through the exposure process and a second developing process different from the first developing process. In other embodiments, the portion of the planarization layer 110 on the pixel region 10 may also be removed by another exposure process and development process (i.e., different from the exposure process and development process used in the process of forming the photoresist pattern PR). In other embodiments, the portion of the planarization layer 110 on the pixel region 10 may also be masked by the photoresist pattern PR, and the portion of the planarization layer 110 on the pixel region 10 is removed by an etching process.

In some embodiments, the sidewalls SW1 of the photoresist pattern PR and the sidewalls SW2 of the patterned planarization layer 112 may be non-coplanar. In other words, one end of the sidewall SW2 of the patterned planarization layer 112 contacting the photoresist pattern PR may contact the bottom surface S1 of the photoresist pattern PR.

Then, referring to fig. 3 and 4, an infrared ray cut-off layer 120 is formed on the photoresist pattern PR and the pixel region 10 of the substrate 100. The infrared ray cut-off layer 120 may be a film layer having an infrared ray filtering function, which may be a single layer or a plurality of layers. In some embodiments, since the photoresist pattern PR has the inclined sidewall SW1 having an included angle θ with respect to the bottom surface S1 thereof of more than 90 degrees, the infrared cut layer 120 is formed only on the top surface S2 of the photoresist pattern PR and the pixel region 10 of the substrate 100, but not on the inclined sidewall SW1 of the photoresist pattern PR. That is, the infrared cut layer 120 may include discontinuous first and second portions 120a and 120b. The first portion 120a of the infrared ray cut-off layer 120 may be formed on the pixel region 10 of the substrate 100, and the second portion 120b of the infrared ray cut-off layer 120 may be formed on the photoresist pattern PR. In other words, the first portion 120a of the infrared cut layer 120 and the second portion 120b of the infrared cut layer 120 may be separated (e.g., in a direction perpendicular to the top surface of the substrate 100) by the photoresist pattern PR. In some embodiments, the thickness of the ir cut-off layer 120 is approximately equal to the thickness of the patterned planarization layer 112 on the substrate 100.

In some embodiments, since the photoresist pattern PR has inclined sidewalls SW1 having an included angle θ with respect to a bottom surface S1 thereof of greater than 90 degrees, i.e., an area of a top surface S2 of the photoresist pattern PR is greater than an area of the bottom surface S1, the infrared cut layer 120 (e.g., a first portion 120a of the infrared cut layer 120) formed on the pixel region 10 of the substrate 100 is spaced apart from the patterned planarization layer 112 by a distance (e.g., a distance d).

Next, referring to fig. 4 and 5, the photoresist pattern PR and a portion of the ir cut-off layer 120 (e.g., the second portion 120b of the ir cut-off layer 120) on the photoresist pattern PR are removed to form an ir cut-off pattern 122 on the pixel region 10 of the substrate 100. In some embodiments, the infrared cut pattern 122 is spaced apart from the patterned planarization layer 112 by a distance (e.g., a distance d) in a direction parallel to the substrate 100. In some embodiments, the thickness of the ir cut-off pattern 122 is approximately equal to the thickness of the patterned planarization layer 112 on the substrate 100. That is, the top surface of the infrared cut pattern 122 is located at substantially the same level as the top surface of the patterned planarization layer 112. In other words, the film layer (e.g., the light shielding layer 140, which will be mentioned later) subsequently formed on the infrared cut pattern 122 and the patterned planarization layer 112 has a good planarization with approximately the same thickness over the pixel region 10 and over the peripheral region of the substrate 100. In this way, when the exposure process is performed on the light shielding layer 140, the light used in the exposure process can be well exposed to some areas of the light shielding layer 140, so that the pattern to be formed can be well formed in these areas.

In some embodiments, the second portion 120b of the infrared cut layer 120 may be stripped (lift off) from above the patterned planarization layer 112 by removing the photoresist pattern PR. That is, the infrared cut pattern 122 may be formed on the pixel region 10 of the substrate 100 by a self-aligned (self-aligned) manner without using an additional photomask. In some embodiments, the photoresist pattern PR may be removed using, for example, a acetone type photoresist solvent (ACE), but the present invention is not limited thereto.

Then, referring to fig. 5 and 6, a light shielding layer 140 is formed on the ir cut-off pattern 122 and the patterned planarization layer 112. The light shielding layer 140 has a good flatness with approximately the same thickness over the pixel region 10 and over the peripheral region of the substrate 100. In some embodiments, the additional planarization layer 130 may be formed on the infrared cut pattern 122 and on the patterned planarization layer 112 before the light shielding layer 140 is formed, so that the flatness of the light shielding layer 140 formed on the additional planarization layer 130 may be further improved. The light shielding layer 140 may be, for example, a material capable of blocking and/or absorbing visible light (e.g., black photoresist). The additional planarization layer 130 may be, for example, an organic material or an inorganic material.

Then, referring to fig. 6 and 7, the light shielding layer 140 is patterned to form a collimation structure layer 142 including a pinhole array (pinhole array) 146 on the infrared cut-off pattern 122, and a mark pattern 144 is formed on the patterned planarization layer 112. The light shielding layer 140 has good flatness and has substantially the same thickness over the pixel region 10 of the substrate 100 and over the wiring region 20, the pad region 30 and the scribe line region 40 in the peripheral region (e.g., the difference in thickness of the light shielding layer 140 over the regions of the substrate 100 is less than 0.5 μm or less than 0.4 μm). In this way, in the process of fabricating the patterned light shielding layer 140, some patterns to be formed, such as the alignment structure layer 142 formed on the pixel region 10 of the substrate 100 and the mark pattern 144 formed on the scribe line region 40 of the substrate 100, cannot be well exposed to some regions (such as the scribe line region 40 of the peripheral region) due to the light transmittance difference caused by the thickness difference, so that the patterns to be formed (such as the alignment structure layer 142 and the mark pattern 144) can be formed on the regions (such as the pixel region 10 and the scribe line region 40) respectively in the subsequent development process, but cannot be removed in the development process. The marker pattern 144 may include alignment markers (ALIGNMENT MARK), overlay markers (overlay markers), or a combination thereof.

In summary, in the above-mentioned manufacturing method of the fingerprint sensing module, the light shielding layer is formed on the infrared cut-off pattern and the patterned planarization layer, so that the thickness of the light shielding layer in different regions (e.g. the pixel region and the peripheral region) of the substrate is approximately the same. In this way, patterns to be formed in different areas of the substrate (e.g., the alignment structure layer including the pinhole array in the pixel region and the mark pattern in the peripheral region) can be well formed in the step of patterning the light shielding layer.

Claims

1. A method of manufacturing a fingerprint sensing module, comprising:

Sequentially forming a planarization layer and a photoresist material layer on a substrate, the substrate including a pixel region including a photosensitive array and a peripheral region surrounding the pixel region;

Removing a portion of the photoresist material layer on the pixel region to form a photoresist pattern exposing the planarization layer;

removing a part of the flat layer on the pixel area to form a patterned flat layer exposing the substrate;

Forming an infrared cut layer on the photoresist pattern and the pixel region of the substrate;

removing the photoresist pattern and a portion of the infrared cut-off layer on the photoresist pattern to form an infrared cut-off pattern on the pixel region of the substrate;

forming a light shielding layer on the infrared cut-off pattern and the patterned planarization layer, and

Patterning the light shielding layer to form a collimation structure layer comprising a pinhole array on the infrared cut-off pattern, and forming a mark pattern on the patterned flat layer.

2. The method of claim 1, wherein the thickness of the ir cut-off pattern is equal to the thickness of the patterned planarization layer on the substrate.

3. The method of manufacturing a fingerprint sensing module according to claim 1 wherein said ir cut-off pattern is spaced apart from said patterned planar layer by a distance in a direction parallel to said substrate.

4. The method of manufacturing a fingerprint sensing module according to claim 1, wherein said photoresist pattern comprises a bottom surface in contact with said patterned planar layer and a top surface opposite said bottom surface, said top surface having an area greater than an area of said bottom surface.

5. The method of manufacturing a fingerprint sensing module according to claim 4, wherein said photoresist pattern comprises sloped sidewalls, an angle between said sloped sidewalls and said bottom surface being greater than 90 degrees.

6. The method of manufacturing a fingerprint sensing module according to claim 5, wherein said infrared cut-off layer is not formed on said sloped sidewall of said photoresist pattern, such that said infrared cut-off layer comprises discontinuous first and second portions, said first portion being formed on said pixel region of said substrate and said second portion being formed on said photoresist pattern.

7. The method of manufacturing a fingerprint sensing module according to claim 1, wherein said infrared cut-off layer comprises a first portion formed on said pixel region of said substrate and a second portion formed on said photoresist pattern, said first portion being separated from said second portion by said photoresist pattern.

8. The method of manufacturing a fingerprint sensing module according to claim 1 wherein:

The photoresist pattern is formed through an exposure process and a first development process,

The patterned planarization layer is removed by the exposure process and a second development process different from the first development process.

9. The method of claim 8, wherein light used by the exposure fabrication process is not exposed to the portion of the photoresist material layer and the portion of the planarization layer under the portion of the photoresist material layer.

10. The method of manufacturing a fingerprint sensing module according to claim 1, further comprising:

an additional planarization layer is formed on the infrared cut pattern and on the patterned planarization layer before the light shielding layer is formed.