CN1158703C - Method for manufacturing nitride-free trench spacer - Google Patents

Abstract

A groove isolation method includes the following steps: forming a photoresist pattern on a semiconductor substrate, forming an organic polymer on the surface of a silicon wafer in an etching reaction chamber, etching a groove anisotropically in the same etching reaction chamber, depositing a groove filler to flatten it, forming a sacrificial oxide layer, and finally removing the sacrificial oxide layer by wet immersion. This method improves the groove edge profile through the plasma etching step, and the method has the dual advantages of simplicity and improved device performance.

Description

Method for manufacturing nitride-free groove spacer

The present invention relates to a method of isolating integrated circuit components, and more particularly to a method of fabricating an isolation structure to improve the edge profile of a recess in an integrated circuit.

With the trend of shrinking the size of semiconductor components, in terms of isolation technology, the traditional local oxidation of silicon (LOCOS) is gradually replaced by a technology called Shallow Trench Isolation (STI). replaced. To make a shallow groove isolation structure, grooves are usually dug out on the surface of the substrate to serve as the separation boundary of the active area of the device. The fabrication method of the trench isolation usually includes the following steps: first, a pad oxide (Pad oxide) layer is formed on the surface of the substrate, and a layer of nitride barrier is formed on it, and then a photoresist mask (photoresist mask) ) to form a groove area, followed by etching, which first etches through the nitride barrier layer and pad oxide layer, and then etches away the substrate to form a groove, which can be filled with dielectric (generally like filling oxide Silicon), after the groove filling is completed, the groove filling is planarized, and the step of planarization is usually completed by chemical-mechanical polishing (CMP), and finally, the nitride resist is sequentially The barrier layer and the pad oxide layer are removed, that is, the fabrication of the groove isolation structure is completed.

Although the traditional groove isolation method has matured and is widely used, the development of this method needs to be further simplified to increase the production capacity. In view of this, Park et al. proposed an improved method in US Pat. No. 5,966,614 to simplify the fabrication of groove isolation. The simplified method is to eliminate the production of the traditional nitride barrier layer. It is known that this nitride barrier layer is used to prevent grinding in the conventional process. However, in the method proposed by Parker et al., a mask without nitride is used to form and etch the groove structure on the base surface without nitride. The manufacturing method is briefly described as follows with reference to FIG. 1A to FIG. 1F . First referring to FIG. 1A, it can be seen that a mask pattern 102 (such as a photoresist pattern) is formed on a semiconductor substrate 100. Using this mask pattern 102 as an etching mask, the substrate 100 is directly etched to a predetermined depth to form a groove. As shown in Figure 1B. Next, as shown in FIG. 1C , the mask pattern 102 is removed. Then, as shown in FIG. 1D , an insulating material (such as silicon oxide) is filled into the groove, and the filling method can be chemical vapor deposition (Chemical Vapor Deposition). Next, the insulator filled in the groove is planarized by chemical mechanical polishing to form the groove filling 104 in the figure. Since the structure omits the fabrication of the polishing barrier layer (ie, nitride), the polished surface is often damaged during the polishing process. The remedial method is to use the etching step in the subsequent process (such as the sacrificial oxide process) to etch away a small part of the grinding surface material, so that the surface layer is as undamaged as possible. For example, Fig. 1E shows the formation of a sacrificial oxide layer 106 (sacrificial oxide). At the same time, a small part of the surface oxide (including the grinding damaged part) in the groove is also etched away, and an oxide etchant such as hydrogen fluoride (HF) can be selected for this removal step. However, the method of Parker et al., although it inevitably requires the above-mentioned surface layer repair step, is still simple compared with the application of the traditional nitride barrier layer (including deposition, etching and removal of the nitride layer). many. And we found that in practical application, this simplified STI process is very suitable for making high-density semiconductor elements with fine line width.

However, the edges of the grooves formed by the existing STI process (including the one proposed by Parker et al.) are mostly nearly vertical. However, the edge of the vertical shape makes vertical sharp corners appear on the upper edge of the groove, which will cause problems in the steps of making subsequent components. One of the questions is about the interaction between the upper edge of the groove and the active area. After the grooves are formed, filled and planarized, a gate oxide layer is typically deposited over the substrate, however this is more Obviously), field oxide depressions often occur at the edge of the gate and around the groove, which leads to a thinning effect in the deposited oxide layer. In this way, when the forming element is in operation, its electric field is likely to be variable, which will cause adverse effects on the performance and reliability of the element.

In view of the above problems, in order to overcome the many shortcomings of the traditional groove isolation method, the object of the present invention is to provide a groove isolation method that improves the edge profile of the groove, which is simple in process and improves the performance of the element.

In a preferred embodiment, a photoresist mask first forms a pattern of grooves on a substrate. The silicon wafer is then placed into an etching chamber where a thin layer of organic polymer is formed to cover the photoresist mask and the exposed substrate surface, and the formation of the polymer is mainly It is obtained by the reaction between the etching gas in the reaction chamber and the surface material of the silicon wafer. After the polymeric film is grown, the substrate can be grooved in the reaction chamber. Since the above-mentioned organic polymer film acts as a barrier during the groove etching process, the etched groove can present a slightly inclined edge profile and a smooth upper edge structure. Such a groove shape will facilitate the filling of the subsequent groove content and improve the contact characteristics of the content with its adjacent layer. After the etching of the groove is completed, the polymer film and the photoresist layer can be removed from the substrate surface. Next, fill the groove with insulating material and planarize it. Finally, the sacrificial oxide layer is formed and removed, and the groove isolation of the present invention is completed.

By adopting the method of the invention, a groove structure with improved profile can be formed by only one plasma etching step, so the manufacturing process is simple and the performance of the element can be improved.

In order to clearly understand the purpose, features and advantages of the present invention, a preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. The following descriptions of methods and structures do not cover the complete flow of integrated circuit fabrication. The prior art used in the present invention is only cited here to facilitate the elaboration of the present invention. Moreover, the relevant drawings in the following texts are not drawn to scale, and their function is only to show the structural features of the present invention.

1A to 1F are cross-sectional views showing a conventional fabrication process for groove isolation;

2A to 2H are cross-sectional views showing a manufacturing process of a groove isolation according to a preferred embodiment of the present invention.

The content of the present invention can be illustrated by the following embodiments and associated figures (FIG. 2A to FIG. 2H). Referring to FIG. 2A, a photoresist pattern 202 is first formed on a semiconductor substrate 200 as an etching mask. Before forming the mask pattern 202, a thin layer of oxide (not shown) may also be formed first to enhance the adhesion between the photoresist pattern and the substrate.

Then, the silicon wafer covered with the mask is put into a plasma etching reaction chamber, for example, an Electron Cyclotron Resonance chamber (Electron Cyclotron Resonance chamber) will be very suitable. Then, an etching gas is introduced into the reaction chamber to form a proper reaction chamber environment, so that organic polymers can be grown on the surface of the silicon wafer. To form polymers on the surface of silicon wafers, there are many options for etching gases, such as chlorine (Cl ₂ ), hydrogen bromide (HBr), perchloroethane (C ₂ F ₆ ), trifluoromethane (CHF ₃ ) , Carbon tetrafluoride (CF ₄ ), sulfur hexafluoride (SF ₆ ) and other gases are applicable. The selected etching gas reacts chemically with the photoresist 202 and even with the exposed substrate 200 in the controlled environment of the reaction chamber to produce a thin polymer 204 to cover the surface of the silicon wafer, especially the photoresist pattern The surface (including the sides) of 202 is shown in FIG. 2B . The thickness of the polymeric film 204 can generally be controlled in the range of 50 to 1000 angstroms. In addition, those skilled in the art can also adjust the reaction conditions in the reaction chamber so that the edge of the polymer coating is as smooth as possible to facilitate the formation of subsequent grooves.

Referring to FIG. 2C , in the same etching reaction chamber, the substrate 200 is etched to a predetermined depth by using anisotropic etching technology to obtain a groove 66 . Since the above-mentioned polymer 204 provides a barrier effect during the etching process, when etching the substrate 200, we found that the etching rate will vary with the depth of the groove etching, so the formed groove profile It tends to slope inwards, as shown in the figure, rather than the nearly vertical shape in the traditional process. And this slightly inclined profile will facilitate the filling of the subsequent groove contents and its adhesion to the groove surface. In addition, this polymer cover 204 also shields the upper edge of the groove during the groove etching step, so that it is not subjected to the brunt of the front side etching, and it even imitates a polymer film with rounded edges, so that the upper edge of the groove 66 Partially forms a smooth contour, and the smooth upper edge enables the contents of the groove 66 to be subsequently filled to obtain better contact characteristics with the substrate 200 . It is also worth noting that the present invention can produce groove structures with improved profiles in only one step of plasma etching.

After the grooves 66 are formed, the remaining polymer 204 can be removed, as shown in FIG. 2D . Afterwards, the photoresist pattern 202 can also be removed, as shown in FIG. 2E .

Next, referring to FIG. 2F, an insulating substance will be filled in the groove 66 to form a filling layer 206. In this embodiment, the filling of the insulating substance can be by means of low-pressure chemical vapor deposition, and the insulating substance can be silicon oxide. Of course Other suitable deposition steps or insulating substances may also be used. In addition, before the groove filling layer 206 is formed by the deposition method, an oxide liner (not shown) can be formed on the groove surface 66 by a thermal oxidation method to control the oxidation of the substrate silicon 200 and the filling layer 206. Interface properties between silicon. The filling layer 206 in the groove 66 is then planarized by chemical mechanical polishing technique, and the groove filling layer 206 is formed as shown in the figure. Those skilled in the art can adjust the grinding conditions according to the needs of the steps in this grinding step, and it is best to avoid damage to the grinding surface as much as possible.

Referring to FIG. 2G, a sacrificial oxide layer 208 is formed. After the ion infiltration required by the process is completed, the sacrificial oxide layer 208 is removed by wet etching. As shown in FIG. H, the etchant can be hydrogen fluoride. At this point, the groove isolation structure of the present invention is completed. After that, gate oxide layer, gate, and other components can be fabricated to complete the fabrication of an integrated circuit.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention; all other equivalent changes or replacements that do not deviate from the spirit disclosed in the present invention should be included in the scope of the application. within the scope of protection.

Claims (5)

1. A method for manufacturing a groove spacer, characterized in that the method at least comprises: forming a photoresist mask on a semiconductor substrate to form a groove; In an etching reaction chamber, an organic polymer film is formed above the semiconductor substrate to cover the surface and sides of the photoresist mask, a part of the organic polymer film passes through the photoresist The etchant mask reacts with an etching gas to produce: In the etching reaction chamber, the semiconductor substrate is etched to form a groove, and the organic polymer film provides a barrier effect during the etching step so that the upper edge of the groove is rounded, and a part of the organic polymer etched away during the etching step; forming an insulating layer in the groove; polishing the insulating layer by chemical mechanical polishing to form a groove insulating layer in the groove; forming a sacrificial oxide layer over the semiconductor substrate: and The sacrificial oxide layer is removed by etching. 2. The method of claim 1, wherein the etching reaction chamber comprises an electron cyclotron magnetic acceleration resonance reaction chamber. 3. The method according to claim 2, wherein the etching gas is one of the following: chlorine, hydrogen bromide, perchloroethane, trifluoromethane, carbon tetrafluoride and sulfur hexafluoride. 4. The method of claim 1, further comprising the step of removing the remaining organic polymer film after the groove etching step. 5. The method of claim 1, further comprising the step of removing the photoresist mask after the recess etching step.

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