CN1378264A - A Self-Aligning Contact Method with Sacrificial Packed Columns - Google Patents

Abstract

The invention provides a self-aligned contact process method with a sacrificial type filling column, which can not damage other isolation layers when a self-aligned contact step is carried out, thereby influencing the isolation effect and generating leakage current. In addition, the thickness of the insulating layer formed by the method and covering the conducting wire can be reduced, thereby reducing the aspect ratio and obtaining better gap insulating layer filling.

Description

A Self-Aligning Contact Method with Sacrificial Packed Columns

The invention relates to a method for self-alignment contact, in particular to a process method for self-alignment contact with sacrificial filled columns.

The manufacture of semiconductor integrated circuits is an extremely complex process, the purpose of which is to reduce and manufacture various electronic components and circuits required for a specific circuit on a small area substrate. Wherein, each component must be electrically connected by an appropriate interconnection wire (interconnect) in order to perform the desired function. Generally, the so-called metallization process of integrated circuits, in addition to making the wiring diagrams of each layer, also uses the contact/via structure as a connection between the contact area of the component and the wires, or between multi-layer wires. Channel. The development of deep submicron process technology highlights the importance of some specific semiconductor manufacturing technologies, such as etching lithography process (lithography process) and dry etching. The development of high-precision exposure equipment and high-photosensitive materials has made it easy to obtain submicron images on the photoresist layer. Furthermore, the application of advanced dry etching equipment and technology to the manufacture of VLSI chips has also made light Submicron images on resist layers can be traced precisely onto the material being etched. However, in order to further reduce the size of the semiconductor chip, in addition to the innovation of the above-mentioned advanced process technology, other special processes or structures must be developed.

The self-aligned contact process is widely used in the deep submicron process because it can reduce the steps of the etching lithography process and reduce the size of components in the semiconductor, thereby reducing the size of the chip. At present, since the processing of integrated circuits is developing towards ULSI, the internal circuit density is increasing. With the increasing integration of integrated circuits, there are still some technical obstacles to be overcome in the current self-alignment contact process. The traditional self-aligned contact process and its technical shortcomings will be briefly described below.

First, please refer to Fig. 1A, which shows that on the surface of the substrate 2, a wiring structure composed of a silicon oxide substrate layer 4, a polysilicon layer 6 and a tungsten silicide layer 8 is formed, and a silicon nitride layer is formed on the wiring structure. The capping layer 10 and the silicon nitride spacer layer 12 are formed on the silicon nitride capping layer and the sidewalls on both sides of the wiring structure. Next, please refer to FIG. 1B, which shows that a dielectric layer (silicon oxide layer) is formed on the entire wiring structure, and then etching lithography and etching procedures are performed to define this dielectric layer to form a dielectric layer as shown in the figure. layer 14 and contacts 16 between the dielectric layers. Next, referring to FIG. 1C, a conductive layer 18 is formed completely, which fills the contact hole 16 and is electrically connected to the semiconductor substrate 20, and then the conductive layer 18 is chemically mechanically polished to expose the dielectric layer 14, so that The conductive layer 18 forms contact plugs that are isolated by insulation.

When the above-mentioned traditional self-aligned contact process forms the contact window 16 step, and when performing etching lithography and etching the silicon oxide dielectric layer, if anisotropic reactive ion etching is used and CHF ₃ is used as an etchant, it is necessary to make silicon oxide The ratio of the etched rate of the silicon nitride layer to the silicon nitride layer is more than 20 to 1 to avoid damage to the silicon nitride capping layer 10 and the silicon nitride spacer layer 12, which cannot be achieved by the current manufacturing technology. FIG. 2A shows the contact window 16 formed by anisotropic reactive ion etching in an ideal self-aligned contact process, and FIG. 2B shows the contact window 16 actually formed after performing anisotropic reactive ion etching. It can be seen that the silicon nitride capping layer 10 and the silicon nitride spacer layer 12 have been etched. If the damage is too severe, the insulation and isolation effects will be affected, resulting in a short circuit between the wire structure and the contact plug.

The above shortcomings make it much more difficult to scale down components, especially in deep sub-micron processing, which only allows smaller line widths and high aspect ratios, and it is still difficult to greatly improve the high selectivity ratio of reactive ion etching. It is difficult, so if there is no breakthrough in new process technology, it will be difficult to improve the product qualification rate, and it will not be possible to achieve mass production on an economical scale.

The purpose of the present invention is to provide a self-aligned contact process method with sacrificial filled columns, which will not damage other isolation layers during the self-aligned contact step, but will affect the isolation effect and cause leakage current.

Another object of the present invention is to provide a self-aligned contact process method with sacrificial filled pillars, which does not need to use an etchant with a high selectivity ratio of silicon oxide to silicon nitride in the reactive ion etching process to achieve self-aligned contact step.

Still another object of the present invention is to provide a self-aligned contact process method with sacrificial filled pillars. The insulating material used in the method can greatly reduce the parasitic capacitance between wire layers.

In short, the present invention discloses a self-aligned contact method with sacrificial filled columns. First, a semiconductor substrate is provided, and a wiring structure composed of a silicon oxide substrate layer, a polysilicon layer and a tungsten silicide layer is sequentially formed on the substrate. , and then, forming an insulating upper cover layer on the wire structure, and then defining the wire structure diagram. Next, a wire insulating spacer layer is formed on the insulating upper cover layer and the sidewalls on both sides of the wire structure. Secondly, an insulating liner layer is conformally formed to cover the wire insulating spacer layer and the surface of the wire structure. Secondly, a sacrificial layer is formed on the whole, and then etching dry printing and etching procedures are performed to define the sacrificial layer to form sacrificial filling pillars and openings between the sacrificial filling pillars. Next, an insulating layer different from the material of the insulating liner layer is formed to fill the openings between the sacrificial filling columns. Then, the insulating layer is ground to expose the upper surface of the sacrificial filling column. Furthermore, the sacrificial filled column is removed to form a contact window opening. Secondly, an anisotropic reactive ion etching process is used to remove the insulating liner layer covering the semiconductor substrate and interposed between the wire insulating spacers through the opening of the contact window. Finally, a conductive layer is formed to fill the opening of the contact window and electrically connected to the semiconductor substrate, and then the conductive layer is ground to expose the insulating layer, so that the conductive layer forms a contact plug isolated by insulation.

To sum up, the present invention provides a self-aligned contact method with sacrificial filled columns, which will not damage other isolation layers when implementing the self-aligned contact process steps, thereby affecting the isolation effect and causing leakage current produced, and this method does not need to use an etchant with a high selectivity ratio of silicon oxide to silicon nitride in the reactive ion etching method to achieve self-aligned contacts. In addition, the thickness of the insulating capping layer formed on the wires formed by this method can be Therefore, the aspect ratio is reduced, and better filling of the gap insulating layer is obtained. The insulating material used in this method can greatly reduce the parasitic capacitance between the wire layers.

In order to make the above-mentioned and other purposes, features, and advantages of the present invention more obvious and understandable, the preferred embodiments are specially cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

1A to 1C are cross-sectional views of the manufacturing process of the self-aligned contact process in the prior art.

FIG. 2A shows a cross-sectional view of a contact window formed by an ideal self-aligned contact process.

FIG. 2B shows a cross-sectional view of the actually formed contact window after performing anisotropic reactive ion etching.

3A to 3F are cross-sectional views of the manufacturing process of the self-aligned contact process with sacrificial filled pillars according to Embodiment 1 of the present invention.

4A to 4F are cross-sectional views of the manufacturing process of the self-aligned contact process with sacrificial filled pillars according to Embodiment 2 of the present invention.

5A to 5F are cross-sectional views of the manufacturing process of the self-aligned contact process with sacrificial filled pillars according to Embodiment 3 of the present invention.

Symbol Description

20, 40, 60 ~ semiconductor substrate; 22, 42, 62 ~ silicon oxide substrate layer; 24, 44, 64 ~ polysilicon layer; 26, 46, 66 ~ tungsten silicide layer; 28, 48, 68 insulating upper cover layer; 30 , 52~ insulating spacer layer; 32, 50~ insulating liner layer; 70~ first insulating liner layer; 72~ second insulating liner layer; 34, 54, 74~ sacrificial filled column; 36, 56, 76 ~ opening; 37, 57, 77 ~ contact window opening; 38, 58, 78 ~ insulating layer; 39, 59, 79 ~ conductive layer.

Example 1

This embodiment illustrates a preferred embodiment of the improved method according to the present invention with reference to Figures 3A to 3F. First, as shown in FIG. 3A, a semiconductor substrate 20 is provided, such as a silicon wafer, on which any required semiconductor components, such as transistor components, can be formed. Here, for the sake of simplicity, only a flat substrate 20 is used. express it. On the surface of the substrate 20, a wiring structure composed of a silicon oxide substrate layer 22, a polysilicon layer 24 and a tungsten silicide layer 26 is sequentially formed, for example, a thin silicon oxide substrate layer 22 is first formed by a thermal oxidation process, Then form a polysilicon layer 24 and a tungsten silicide layer 26 with a plasma enhanced chemical vapor deposition (PECVD), after that, form an insulating upper cap layer 28 on the wire structure, for example, with a plasma (plasma) enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) to form a silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, aluminum oxide layer or silicon carbide layer with a thickness of 200 to 2500 Å. Next, implement etching lithography and etching procedures to define the wire structure diagram composed of silicon oxide substrate layer 22 , polysilicon layer 24 , tungsten silicide layer 26 and insulating upper cover layer 28 as shown in the figure. Next, form a wire insulation spacer layer 30 on the insulating upper cover layer and the side walls on both sides of the wire structure, and form a thickness of 100 to 600 Å by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). Silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, aluminum oxide layer or silicon carbide layer. Etching-back the film layer to form an insulating spacer layer 30 . Next, an insulating liner layer 32 is conformably formed to cover the wire insulating spacer layer and the surface of the wire structure, and a thickness of 100 to 400 Å is also formed by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). A silicon dioxide layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer or a silicon carbide layer.

Next, referring to FIG. 3B , a sacrificial layer is fully formed and then etched lithography and etching procedures are performed to define the sacrificial layer to form sacrificial filled pillars 34 and openings 36 between the sacrificial filled pillars. The sacrificial layer can be a polysilicon layer. Since the insulating spacer layer 30 and the insulating liner layer 32 have been formed before, it can prevent electrical short circuit caused by residues generated during etching the polysilicon layer.

Next, referring to FIG. 3C, an insulating layer different from the material of the insulating liner layer is formed to fill the opening 36 between the sacrificial filling columns, for example, a plasma enhanced chemical vapor deposition (PECVD) is used to form a thickness of 5000 to 8000 Å oxide layer.

Then, use a planarization process, such as chemical mechanical polishing, to polish the insulating layer, so that the upper surface of the sacrificial filled column is exposed, and the pattern of the insulating layer 38 as shown in the figure is formed. For example, the speed of the turntable in the process parameters is adjusted. Pressure, pad type and abrasive type to control the removal rate, uniformity and selectivity in the process, abrading the upper part of this insulating layer.

Furthermore, referring to FIG. 3D , an isotropic dry etching process or an isotropic wet etching process is used to etch back the sacrificial filling column to remove the sacrificial filling column to form a contact window opening 37 .

Next, please refer to FIG. 3E , anisotropic reactive ion etching process is used through the contact opening 37 to remove the insulating liner layer covering the semiconductor substrate and interposed between the wire insulating spacers.

Finally, referring to FIG. 3F, a conductive layer 39 is formed on the entire surface, fills the contact opening 37 and is electrically connected to the semiconductor substrate 20, and then chemically mechanically polishes the conductive layer 39 to expose the insulating layer 38 and make the conductive layer 39 conductive. Layer 39 forms contact plugs isolated by insulation, wherein the conductive layer is a sputtered polysilicon layer or a tungsten layer.

Example 2

This embodiment illustrates another preferred embodiment of the improved method according to the present invention with reference to FIGS. 4A to 4F. First, as shown in FIG. 4A, on the surface of the semiconductor substrate 40, a wiring structure composed of a silicon oxide substrate layer 42, a polysilicon layer 44 and a tungsten silicide layer 46 is sequentially formed, for example, using a thermal oxidation The steps form a thin silicon oxide substrate layer 42, then form a polysilicon layer 44 and a tungsten silicide layer 46 with a plasma enhanced chemical vapor deposition (PECVD), and then form an insulating upper cap layer 48 on the wire structure, for example, with A plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) forms a silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, aluminum oxide layer or silicon carbide layer with a thickness of 200 to 2500 Å. Next, implement etching lithography and etching procedures to define the wire structure diagram composed of silicon oxide substrate layer 42 , polysilicon layer 44 , tungsten silicide layer 46 and insulating upper cover layer 48 as shown in the figure. Next, conformally form an insulating liner layer 50 to cover the surface of the wire structure, and form a silicon dioxide layer with a thickness of 100 to 400 Å by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), A silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer or a silicon carbide layer. Next, a wire insulating spacer layer 52 is formed on both sides of the insulating liner layer covering the wire structure, and a thickness of 100 to 600 Å is also formed by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). Silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, aluminum oxide layer or silicon carbide layer. Etching-back the film layer to form an insulating spacer layer 52 .

Next, referring to FIG. 4B , a sacrificial layer is fully formed and then etched lithography and etching procedures are performed to define the sacrificial layer to form sacrificial filled pillars 54 and openings 56 between the sacrificial filled pillars. The sacrificial layer can be a polysilicon layer. Since the insulating spacer layer 50 and the insulating liner layer 52 have been formed before, it can prevent electrical short circuit caused by residues generated during etching the polysilicon layer.

Next, referring to FIG. 4C, an insulating layer different from the material of the insulating liner layer is formed to fill the opening 56 between the sacrificial filling columns, for example, a thickness of 5000 is formed by plasma enhanced chemical vapor deposition (PECVD). to 8000 Å oxide layer.

Then, use a planarization process, such as chemical mechanical polishing, to polish the insulating layer, so that the upper surface of the sacrificial filled column is exposed, and the pattern of the insulating layer 58 as shown in the figure is formed. Pressure, pad type and abrasive type to control the removal rate, uniformity and selectivity in the process, abrading the upper part of this insulating layer.

Furthermore, referring to FIG. 4D , an isotropic dry etching process or an isotropic wet etching process is used to etch back the sacrificial filling column to remove the sacrificial filling column to form a contact window opening 57 .

Next, referring to FIG. 4E , anisotropic reactive ion etching process is used through the contact opening 57 to remove the insulating liner layer covering the semiconductor substrate and interposed between the wire insulating spacers.

Finally, referring to FIG. 4F, a conductive layer 59 is formed comprehensively, which passes through the insulating layer 58 and is electrically connected to the semiconductor substrate 40, and then the conductive layer 59 is chemically mechanically polished to expose the insulating layer 58 and make the conductive layer 59 conductive. Layer 59 forms contact plugs that are isolated by insulation, wherein the conductive layer is a sputtered polysilicon layer or a tungsten layer.

Example 3

This embodiment illustrates another preferred embodiment of the improved method according to the present invention with reference to Figures 5A to 5F. First, as shown in FIG. 5A, on the surface of the semiconductor substrate 60, a wiring structure composed of a silicon oxide substrate layer 62, a polysilicon layer 64 and a tungsten silicide layer 66 is sequentially formed, for example, using a thermal oxidation The step is to form a thin silicon oxide substrate layer 62, then form a polysilicon layer 64 and a tungsten silicide layer 66 by a plasma enhanced chemical vapor deposition (PECVD), and then form an insulating upper cap layer 68 on the wiring structure, for example with Plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) forms a silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, aluminum oxide layer or silicon carbide layer with a thickness of 200 to 2500 Å. Next, implement etching lithography and etching procedures to define the wire structure diagram composed of silicon oxide substrate layer 62 , polysilicon layer 64 , tungsten silicide layer 66 and insulating upper cap layer 68 as shown in the figure. Next, a first insulating liner layer 70 and a second insulating liner layer 72 are conformally formed to cover the surface of the wire structure, and a plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) is also used to form a A silicon nitride layer 70 having a thickness of 100 to 600 Å and an oxide layer 72 having a thickness of 100 to 600 Å.

Next, referring to FIG. 5B , a sacrificial layer is fully formed and then etched lithography and etching procedures are performed to define the sacrificial layer to form sacrificial filled pillars 74 and openings 76 between the sacrificial filled pillars. The sacrificial layer can be a polysilicon layer. Since the insulating spacer layer 70 and the insulating liner layer 72 have been formed before, it can prevent electrical short circuit caused by residues generated during etching the polysilicon layer.

Next, referring to FIG. 5C, an insulating layer different from the material of the insulating liner layer is formed comprehensively to fill the opening 76 between the sacrificial filling columns, for example, a plasma-enhanced chemical vapor deposition (PECVD) is used to form a thickness 5000 to 8000 Å oxide layer.

Then, use a planarization process, such as chemical mechanical polishing, to grind the insulating layer, so that the upper surface of the sacrificial filled column is exposed, and the pattern of the insulating layer 78 as shown in the figure is formed, for example, the speed of the turntable in the process parameters is adjusted, and the following Pressure, pad type and abrasive type to control the removal rate, uniformity and selectivity in the process, abrading the upper part of this insulating layer.

Furthermore, referring to FIG. 5D , the sacrificial filling column is etched back by an isotropic dry etching process or an isotropic wet etching process to remove the sacrificial filling column to form a contact window opening 77 .

Next, referring to FIG. 5E , anisotropic reactive ion etching process is used through the contact opening 77 to remove the insulating liner layer covering the semiconductor substrate and interposed between the wire insulating spacers.

Finally, referring to FIG. 5F, a conductive layer 79 is formed comprehensively, which passes through the insulating layer 78 and is electrically connected to the semiconductor substrate 60, and then the conductive layer 79 is chemically mechanically polished to expose the insulating layer 78 and make the conductive layer 79 electrically conductive. Layer 79 forms contact plugs that are isolated by insulation, wherein the conductive layer is a sputtered polysilicon layer or a tungsten layer.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be determined by the scope of the appended claims and with reference to the specification and drawings.

Claims (20)

1. A self-aligned contact process method with sacrificial filled columns is applicable to a semiconductor substrate, the method comprising the following steps: (a) forming a wire structure on the semiconductor substrate; (b) forming an insulating capping layer on the lead structure; (c) forming a wire insulating spacer layer on the insulating upper cover layer and the side walls on both sides of the wire structure; (d) forming an insulating liner layer to cover the wire insulating spacer layer and the surface of the wire structure; (e) forming a sacrificial layer and defining the sacrificial layer to form sacrificial packed posts and openings between the sacrificial packed posts; (f) forming an insulating layer different from the material of the insulating liner layer to fill the opening between the sacrificial filling columns; (g) removing the sacrificial filled column to form a contact opening; (h) removing the insulating liner layer covering the semiconductor substrate and interposed between the wire insulating spacers through the contact window opening; and (i) forming a conductive layer to fill the opening of the contact window and electrically connect with the semiconductor substrate. 2. The method according to claim 1, wherein the wire structure in the step (a) is composed of a silicon oxide substrate layer, a polysilicon layer and a tungsten silicide layer. 3. The method according to claim 1, characterized in that, the insulating upper cover layer, the wire insulating spacer layer and the insulating liner layer are silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, aluminum oxide layer or SiC layer. 4. The method of claim 1, wherein the step (f) further comprises chemical mechanical polishing the insulating layer to expose the upper surface of the sacrificial filled pillar. 5. The method according to claim 1, characterized in that, in removing the sacrificial filled column in the step (g), the sacrificial filled column is regenerated by an isotropic dry etching process or an isotropic wet etching process. etch. 6. The method according to claim 1, characterized in that, in the step (h), removing the insulating liner layer covered on the semiconductor substrate and interposed between the wire insulating spacers is to utilize anisotropic reactive ions The etching process is complete. 7. The method according to claim 1, characterized in that, the conductive layer in the step (i) is a polysilicon layer or a tungsten layer, and chemical mechanical grinding is used to polish the conductive layer to expose the insulating layer and make the conductive layer The layers form contact plugs that are isolated by insulation. 8. A self-aligned contact process method with sacrificial filled columns, suitable for a semiconductor substrate, the method comprising the following steps: (a) forming a wire structure on the semiconductor substrate; (b) forming an insulating capping layer on the lead structure; (c) forming an insulating liner layer to cover the surface of the wire structure; (d) forming a wire insulating spacer layer on the side walls of both sides of the insulating liner layer covering the wire structure; (e) forming a sacrificial layer and defining the sacrificial layer to form sacrificial packed posts and openings between the sacrificial packed posts; (f) forming an insulating layer different from the material of the insulating liner layer to fill the opening between the sacrificial filling columns; (g) removing the sacrificial filled column to form a contact opening; (h) removing the insulating liner layer covering the semiconductor substrate and interposed between the wire insulating spacers through the contact window opening; and (i) forming a conductive layer to fill the opening of the contact window and electrically connect with the semiconductor substrate. 9. The method according to claim 8, characterized in that the wire structure in the step (a) is composed of a silicon oxide substrate layer, a polysilicon layer and a tungsten silicide layer. 10. The method according to claim 8, characterized in that, the insulating upper cover layer, the wire insulating spacer layer and the insulating liner layer are silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, aluminum oxide layer or SiC layer. 11 . The method of claim 8 , wherein the step (f) further comprises chemical mechanical polishing the insulating layer to expose the upper surface of the sacrificial filled pillar. 12 . 12. The method according to claim 8, characterized in that, removing the sacrificial filled column in the step (g) is to use an isotropic dry etching process or an isotropic wet etching process to carry out the sacrificial filled column etch back. 13. The method according to claim 8, characterized in that, the removal of the insulating liner layer covering the semiconductor substrate and interposed between the wire insulating spacers in the step (h) utilizes anisotropy The reactive ion etching process is completed. 14. The method according to claim 8, characterized in that, the conductive layer in the step (i) is a polysilicon layer or a tungsten layer, and the conductive layer is chemically mechanically ground to expose the insulating layer, so that the conductive layer Contact plugs isolated by insulation are formed. 15. A self-aligned contact process method with sacrificial filled columns, suitable for a semiconductor substrate, the method comprising the following steps: (a) forming a wire structure on the semiconductor substrate; (b) forming an insulating capping layer on the lead structure; (c) forming a first insulating liner layer to cover the surface of the wire structure; (d) forming a second insulating liner layer to cover the first insulating liner layer; (e) forming a sacrificial layer and defining the sacrificial layer to form sacrificial packed posts and openings between the sacrificial packed posts; (f) forming an insulating layer different from the material of the first insulating liner layer to fill the openings between the sacrificial filling columns; (g) removing the sacrificial filled column to form a contact opening; (h) removing the first insulating liner layer and the second insulating liner layer covering the semiconductor substrate and interposed between the wire structures through the contact window opening; and (i) forming a conductive layer to fill the opening of the contact window and electrically connect with the semiconductor substrate. 16. The method as described in item 15 of the scope of patent application, wherein the insulating upper cover layer, the wire insulating spacer layer and the insulating liner layer are silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, Aluminum oxide layer or silicon carbide layer. 17. The method as described in claim 15, wherein the step (f) further includes chemical mechanical polishing of the insulating layer to expose the upper surface of the sacrificial filled pillar. 18. The method as described in item 15 of the scope of patent application, wherein the removal of the sacrificial filling column in the step (g) is to use an isotropic dry etching process or an isotropic wet etching process to fill the sacrificial type The pillars are etched back. 19. The method as described in item 15 of the claimed scope of patents, wherein the removal in the step (h) is covered on the semiconductor substrate, and the insulating liner layer between the insulating spacer layers of the wires is made of non- The isotropic reactive ion etching process is completed. 20. The method as described in item 15 of the scope of patent application, wherein the conductive layer in the step (i) is a polysilicon layer or a tungsten layer, and chemical mechanical grinding is used to polish the conductive layer to expose the insulating layer, so that The conductive layer forms contact plugs that are isolated by insulation.

Images