CN115271052B - An electronic synaptic circuit and neural network circuit based on ferroelectric field effect transistor - Google Patents
An electronic synaptic circuit and neural network circuit based on ferroelectric field effect transistor Download PDFInfo
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Abstract
本申请涉及一种神经网络电路，包括多个神经元电路，以及多个电子突触电路，其中所述电子突触电路中的至少一个配置为从一个突触前神经元电路接收输入和控制信号，并接收一个突触后神经元电路的反馈信号；其中，所述电子突触电路至少包括开关单元、输入单元以及权值计算单元；本申请还涉及一种包含如前述的神经网络电路的电子系统和一种电子设备。
The present application relates to a neural network circuit, comprising a plurality of neuron circuits and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive input and control signals from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synapse circuit comprises at least a switch unit, an input unit and a weight calculation unit; the present application also relates to an electronic system and an electronic device comprising the neural network circuit as described above.
Description
Technical Field
The application relates to the field of neural network circuit design, in particular to an electronic synaptic circuit based on a ferroelectric field effect transistor and a neural network circuit.
Background
With the rapid development of information technology industries such as artificial intelligence and big data, the processing speed and performance requirements of computers in social production and daily life are higher and higher. The amount of data that a computer needs to process increases exponentially, which places unprecedented stress on both data storage and computation. The most commonly used computer architecture at present is the traditional von neumann architecture, which has the characteristic of memory and computation separation, and data needs to be frequently migrated between a storage unit and a computing unit, so that the computing speed is greatly reduced, and the computing power consumption is greatly increased.
In order to solve the problem of von neumann architecture, a method for architecture of neuromorphic computation is proposed based on bionics, and the complex computation problem that high-speed processing cannot be performed in a traditional architecture is solved by simulating the connection mode of neurons and synapses in the brain to complete the theoretical modeling of neuroscience. The LIF neuron model is one of the most basic models commonly used in neuromorphic computing architecture, and its nature abstracts neurons into capacitances, converting the way neurons communicate into action potentials and impulses. In the LIF neuron model, the electric potential of the electric signal input to the neuron and the stability of the final output pulse are all cores capable of improving the stability and processing speed of the neuron model.
As an emerging calculation paradigm, if the behavior of neurons or synapses is simulated from the physical level by hardware circuits, neuromorphic calculations with low power consumption and high computational performance are expected to be achieved. Therefore, selecting a reasonable calculation method and designing and building a hardware circuit are also important problems for realizing nerve morphology calculation.
Disclosure of Invention
In view of the technical problems existing in the prior art, the application provides a neural network circuit, which comprises a plurality of neuron circuits and a plurality of electronic synaptic circuits, wherein at least one of the electronic synaptic circuits is configured to receive input and control signals from one pre-synaptic neuron circuit and receive feedback signals from one post-synaptic neuron circuit, the electronic synaptic circuit at least comprises a switch unit, a weight calculation unit and a ferroelectric transistor, the switch unit is coupled between the switch unit and the ground, the connection state of the electronic synaptic circuit and the post-synaptic neuron circuit is controlled under the influence of the control signals from the pre-synaptic neuron circuit, the input unit is coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, the first input signal and the second input signal from the pre-synaptic neuron circuit are received under the control of the feedback signals from the post-synaptic neuron circuit, the weight calculation unit is coupled with the input unit, and the ferroelectric transistor is configured to update the ferroelectric resistor from the input unit.
In particular, the post-synaptic neuron circuit comprises a comparator having a positive input coupled to a switching unit of the electronic synaptic circuit, a negative input of the comparator being configured to receive a preset constant signal, an output of the comparator being coupled to an input unit of the electronic synaptic circuit, a resistor coupled between the positive input of the comparator and a power supply, a capacitor coupled between the positive input of the comparator and ground, the comparator being configured to output the feedback signal when the switching unit connects the post-synaptic neuron circuit to the electronic synaptic circuit and the ferroelectric transistor is turned on and the positive input of the comparator is dropped in voltage when the voltage drops below the preset constant signal.
In particular, the switching unit comprises a first transistor, the control pole of which is configured to receive the control signal, the first pole of which is coupled to the positive input of the comparator, and the second pole of which is coupled to the first pole of the ferroelectric transistor.
In particular, the input unit comprises a second transistor, the control electrode of which is configured to receive the feedback signal, the first electrode of which is configured to receive the first input signal, the second electrode of which is coupled to the control electrode of the ferroelectric transistor, a third transistor, of a type complementary to the second transistor, the control electrode of which is configured to receive the feedback signal, the first electrode of which is grounded, the second electrode of which is coupled to the control electrode of the ferroelectric transistor, a fourth transistor, the control electrode of which is configured to receive the feedback signal, the first electrode of which is configured to receive the second input signal, the second electrode of which is coupled to the second electrode of the ferroelectric transistor, a fifth transistor, of a type complementary to the fourth transistor, the control electrode of which is configured to receive the feedback signal, the first electrode of which is grounded, and the second electrode of which is coupled to the second electrode of the ferroelectric transistor.
In particular, the post-synaptic neuron circuit further comprises a delay unit coupled between the output of the comparator and the input of the input unit and configured to generate a time interval between the active levels of the control signal and the feedback signal.
In particular, the control electrode of the ferroelectric transistor is configured to receive the first input signal, the second electrode of the ferroelectric transistor is configured to receive the second input signal, the control signal and the second input signal jump to active levels simultaneously, the first input signal generates active levels when the active levels of the second input signal jump to inactive levels, the active levels of the second input signal gradually rise during one pulse, and the active levels of the first input signal gradually fall during one pulse.
In particular, the magnitude of the effective level of the feedback signal is greater than the maximum magnitude of the effective level of the first or second input signal.
The application provides an electronic synaptic circuit configured to receive input and control signals from a pre-synaptic neuron circuit and receive feedback signals from a post-synaptic neuron circuit, wherein the electronic synaptic circuit comprises at least a switch unit coupled between the pre-synaptic neuron circuit and the post-synaptic neuron circuit and configured to control a connection state of the electronic synaptic circuit and the post-synaptic neuron circuit under the influence of the control signals from the pre-synaptic neuron circuit, an input unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit and configured to receive first and second input signals from the pre-synaptic neuron circuit under the control of the feedback signals from the post-synaptic neuron circuit, and a weight calculation unit coupled between the switch unit and ground and coupled with the input unit, the weight calculation unit comprising at least a ferroelectric transistor configured to receive the first and second input signals from the input unit and update a channel resistance of the ferroelectric transistor.
In particular, the switching unit of the electronic synaptic circuit comprises a first transistor having a control electrode configured to receive the control signal, a first electrode coupled to the post-synaptic neuron circuit and a second electrode coupled to the first electrode of the ferroelectric transistor.
In particular, the input unit of the electronic synaptic circuit comprises a second transistor with a control electrode configured to receive the feedback signal, a first electrode configured to receive the first input signal, a second electrode coupled to the control electrode of the ferroelectric transistor, a third transistor of a type complementary to the second transistor with a control electrode configured to receive the feedback signal, a first electrode grounded, a second electrode coupled to the control electrode of the ferroelectric transistor, a fourth transistor with a control electrode configured to receive the feedback signal, a first electrode configured to receive the second input signal, a second electrode coupled to the second electrode of the ferroelectric transistor, a fifth transistor of a type complementary to the fourth transistor with a control electrode configured to receive the feedback signal, a first electrode grounded, and a second electrode coupled to the second electrode of the ferroelectric transistor.
In particular, the control electrode of the ferroelectric transistor in the electronic synaptic circuit is configured to receive the first input signal and the second electrode of the ferroelectric transistor is configured to receive the second input signal, the control signal and the second input signal jump to active levels simultaneously, the first input signal generates active levels when the active levels of the second input signal jump to inactive levels, the active levels of the second input signal gradually rise during a pulse, and the active levels of the first input signal gradually fall during a pulse.
In particular, the magnitude of the effective level of the feedback signal in the electronic synaptic circuit as described above is greater than the maximum magnitude of the effective level of the first or second input signal.
The application also provides an electronic system comprising the neural network circuit.
The application also provides electronic equipment comprising the neural network circuit.
By adopting the scheme of the application, on one hand, the advantages of low power consumption and high calculation performance can be obtained by simulating the neurons from the physical structure of the circuit, and on the other hand, the signal transmission of the neuron form circuit is optimized by using the STDP mechanism, so that the circuit processing time can be further shortened. The ferroelectric field effect transistor is used in circuit design, so that the power consumption of the circuit can be reduced again through the characteristics of non-volatile property and the like, and the processing speed is improved. The novel neural network circuit structure provided by the scheme also has positive significance for promoting the development of the neural morphology circuit.
Drawings
Preferred embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:
fig. 1 is a schematic diagram of a neural network circuit model according to an embodiment of the present application.
FIG. 2 is a schematic diagram showing the STDP mechanism of electronic synapses.
FIG. 3A is a schematic diagram of an electronic synaptic circuit and a portion of a post-synaptic neuron circuit according to one embodiment of the application.
Fig. 3B is a timing diagram illustrating the operation of the circuit shown in fig. 3A.
FIG. 4 is a graph showing the normalized conductance of an electronic synaptic circuit as a function of time according to one embodiment of the present application.
Detailed Description
In the following detailed description of the embodiments, reference is made to the accompanying drawings, which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the application may be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the application. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. For the purpose of illustration only, the connection between elements in the figures is meant to indicate that at least the elements at both ends of the connection are in communication with each other and is not intended to limit the inability to communicate between elements that are not connected. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the output terminals provided, and is not intended to limit the communication between the two units to only signals as shown in the figures.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments of the application. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to embodiments of the present application.
Transistors may refer to transistors of any structure, such as Field Effect Transistors (FETs) or bipolar transistors (BJTs). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, or the like, depending on the channel material. The carriers are electrons or holes, and can be classified into N-type transistors and P-type transistors. The control electrode refers to the grid electrode of the field effect transistor, the first electrode can be the drain electrode or the source electrode of the field effect transistor, the corresponding second electrode can be the source electrode or the drain electrode of the field effect transistor, when the transistor is a bipolar transistor, the control electrode refers to the base electrode of the bipolar transistor, the first electrode can be the collector electrode or the emitter electrode of the bipolar transistor, and the corresponding second electrode can be the emitter electrode or the collector electrode of the bipolar transistor.
The traditional computer architecture divides the equipment into a computing unit and a storage unit, the computing unit is required to be called for completing one-time computing to compute the data to be processed, and then the computing result is stored in the storage unit. When the traditional computer architecture faces larger data and more complex calculation processes, the calculation processes need to be split into a plurality of simple calculation, the steps are repeated for a plurality of times, a plurality of intermediate values are generated before the final calculation result is obtained and stored in a storage unit, and the intermediate values are called to finish the calculation of the final result during calculation.
The artificial neural network circuit (hereinafter referred to as neural network circuit) provided by the application can effectively simplify the complex calculation process, and can avoid the problems caused by calculation separation.
Fig. 1 is a schematic diagram of a neural network circuit model according to one embodiment of the application. The neural network circuit comprises a plurality of nodes, which are also called neurons, and the two neurons can be connected through electronic synapses. The synapse transfers an electrical signal from the electronic presynaptic neuron to the postsynaptic neuron, the path of the transfer depending on the weights of the electronic synapses between the neurons. The higher the weight, the tighter the connection between the two neurons.
As shown in fig. 1, according to one embodiment of the present application, a neuron in a neural network circuit may be connected to a plurality of neurons, and the two neurons are connected and transmit signals through an electronic synapse. The calculations that need to be completed can be converted into multiple round robin calculations in the neural network circuit, and a single calculation process can be converted into a process that starts to transmit signals from the initial neurons set by the user, routes through multiple neurons and electronic synapses, and finally transmits to the target neurons set by the user in the neural network circuit. The neural network circuit automatically adjusts weights among neurons based on a preset learning mechanism, so that calculation processes of different problems are realized.
Each electronic synapse may receive a signal from at least one neuron (referred to as a pre-synaptic neuron relative to the synapse), and/or may send a signal to at least one neuron (referred to as a post-synaptic neuron relative to the synapse).
FIG. 2 is a schematic diagram showing the STDP learning mechanism of electronic synapses. Wherein the time Δt of the horizontal axis represents the time difference between the time at which the post-synaptic neuron transmits a signal and the time at which the pre-synaptic neuron transmits a signal, and the Δw of the vertical axis represents the rate of change of the weight of the electronic synapse. As can be seen from fig. 2, for such an electronic synapse, when Δt is positive, the weight change rate of the electronic synapse decreases with increasing Δt.
In order to prepare an electronic synapse with the STDP learning mechanism characteristic curve, the application provides an electronic synapse circuit. In particular, ferroelectric transistors (fefets) are included in such electronic synaptic circuits.
With the development of semiconductor device technology, some new devices with adjustable resistance and nonvolatile characteristics have been proposed, including resistive random access memories, phase change memories, ferroelectric transistors (fefets), and the like. Among them, fefets have advantages of low power consumption and high operation speed, and thus have received extensive attention from the scientific research and industry.
FeFET is a novel transistor in which a layer of ferroelectric material is added between the gate electrode and the gate oxide layer of a conventional MOSFET, and the magnitude and duration of the voltage applied to the gate electrode of the FeFET can be changed by modulating the magnitude of the amount of charge induced in the gate oxide layer, so that the threshold voltage and channel resistance of the FeFET can be changed. When a specific voltage is applied to the gate source of the FeFET, the electric dipole formed in the crystal structure of the ferroelectric material will remain in line with the direction of the electric field, and even if the gate voltage is removed, the above-mentioned conduction characteristics will not change, and even after the electric field is removed, the electric dipole formed in the crystal structure of the ferroelectric material will remain in such a polarized state, so that the threshold voltage and channel resistance of the FeFET will remain unchanged until the gate source voltage changes, and the threshold voltage and channel resistance will be set again.
FIG. 3A is a schematic diagram of an electronic synaptic circuit and a portion of a post-synaptic neuron circuit according to one embodiment of the application. Fig. 3B is a timing diagram illustrating the operation of the circuit shown in fig. 3A.
As shown in fig. 3A, the electronic synaptic circuit 20 is coupled with its post-synaptic neuron circuit 30, while the electronic synaptic circuit 20 is also coupled with a pre-synaptic neuron circuit (not shown). According to one embodiment, the pre-synaptic neuron circuit may have a circuit structure similar to a post-synaptic neuron circuit.
According to one embodiment, each neuron circuit may transmit at least four signals, including STDP WL1, STDP WL2, LIF WL, when transmitting signals, which may be provided to a subsequent neuron circuit as a control signal and an input signal by a subsequent synapse, and STDP BL, which may be provided to a preceding synapse as a control signal, the preceding synapse being connected between the neuron circuit and the preceding neuron circuit. The term "front" or "rear" as used herein refers to a state where the signal transmission path is a signal transmission path which is input by a user and is relatively closer to the most-initiated neuron circuit, and a state where the signal transmission path is a signal transmission path which is relatively farther from the most-initiated neuron circuit.
For a particular electronic synaptic circuit, LIF WL determines the connection state of the electronic synaptic circuit to the post-synaptic neuron circuit for the control signal provided by the pre-synaptic neuron circuit. STDP WL1 and STDP WL2 provide input signals to the presynaptic neuronal circuit that determine updated values of the electronic synaptic circuit weights. The feedback signal STDP BL is provided by the post-synaptic neuron circuit and determines the timing of modifying the current weight of the electronic synaptic circuit to the updated value.
According to one embodiment, as shown in fig. 3A, the electronic protruding circuit 20 may include at least a switching unit 201, an input unit 202, and a weight calculation unit 203.
According to one embodiment, the switching unit 201 may comprise at least an NMOS transistor M21, for example, the gate of which may be configured to receive a control signal LIF WL from a presynaptic neuronal circuit. As shown in fig. 3B, LIF WL includes a plurality of high-level short pulses, and when LIF WL is high, electronic synaptic circuit 20 is activated to conduct an electrical connection with post-synaptic neuron circuit 30.
According to one embodiment, the input unit 202 may include at least NMOS transistors M23 and M25, and PMOS transistors M24 and M26, for example.
According to one embodiment, the drain of M23 may be configured to receive the input signal STDP WL1 from one pre-synaptic neuron circuit, the source may be coupled to the weight calculation unit 203, and the gate may be configured to receive the feedback signal STDP BL from the post-synaptic neuron circuit.
According to one embodiment, the source of M24 may be coupled to the source of M23 and weight calculation unit 203, the drain thereof may be grounded, and the gate thereof may be configured to receive the feedback signal STDP BL from the post-synaptic neuron circuit.
According to one embodiment, the drain of M25 may be configured to receive the input signal STDP WL2 from the pre-synaptic neuron circuit, the source may be coupled to the weight calculation unit 203, and the gate may be configured to receive the feedback signal STDP BL from the post-synaptic neuron circuit. Wherein the input signals STDP WL1 and STDP WL2 may be from outputs in the same presynaptic neuron circuit. As shown in fig. 3B, STDP WL1 and STDP WL2 may be pulse signals having the same period and different waveforms.
According to one embodiment, the source of M26 may be coupled to the source and weight calculation unit 203 of M25, the gate may be configured to receive the feedback signal STDP BL from the post-synaptic neuron circuit, and the drain may be grounded.
According to one embodiment, the weight calculation unit 203 may include at least a FeFET transistor M22. According to one embodiment, the gate of M22 may be coupled to the source of M23 and the source of M24, the source of M22 may be coupled to the sources of M25 and M26, and the drain may be coupled to the source of M21.
As shown in fig. 3A, a neuron circuit, such as post-synaptic neuron circuit 30, may comprise at least a comparator 301, a resistor 302, and a capacitor 303. The positive input of comparator 301 may be coupled to electronic burst circuit 20 (e.g., may be coupled to the drain of transistor M21) while also being coupled to a power supply through resistor 302. The negative input of the comparator 301 is configured to receive a preset threshold voltage Vth. Once the positive input voltage Vout of the comparator 301 is lower than the negative input voltage Vth, the neuron outputs an output signal Y (including LIF WL ', STDP WL1', and STDP WL2', and STDP BL). According to one embodiment, the neuron circuit may further comprise a delay unit 304 configured to ensure a certain time difference between the high-level pulse of the STDP BL and the high-level pulse of the LIF WL output by the presynaptic neuron circuit.
According to one embodiment of the application, the device parameters such as the gate length, the doping concentration, the gate insulation layer thickness and the like of M21, M22, M23, M24, M25 and M26 are not limited, and can be adjusted according to actual needs.
According to one embodiment, as shown in FIG. 3B, when Vout is higher than Vth, the post-synaptic neuron circuit will not output signal Y and therefore STDP BL is also low. In this case, the transistors M23 and M25 in the input unit 202 are turned off, and at this time the transistors M24 and M26 are turned on, and both the gate and source of the FeFET transistor M22 are grounded. In this case, the threshold voltage and channel resistance of the FeFET transistor M22 are unchanged. According to one embodiment, M22 may be still on when the gate-source voltage is 0.
When LIF WL is high, the charge in capacitor 303 is discharged through the path of M22 in the electronic synaptic circuit. If Vout drops to a level below Vth after a bleed, the post-synaptic neuron circuit 30 transmits a signal Y and STDL BL jumps to a high level.
According to one embodiment, a neuron circuit has a plurality of preceding electronic shock circuits coupled thereto. When any of these electronic synapse circuits is capable of dropping Vout below the Vth level, the neuron circuit will emit signal Y, and all of the preceding electronic synapse circuits coupled thereto will receive a high level of STDP BL.
However, if Vout cannot be reduced to a level below Vth after a bleed, and other prior electronic synapse circuits have not achieved this goal, the power supply will continue to charge capacitor 303 after LIF WL is high, and the charge in capacitor 303 will be bled again the next time LIF WL is high. After several bleeds or integrations, it is possible to achieve the goal of Vout dropping to a level below Vth.
When STDP BL is high, M24 and M26 are off, and M23 and M25 are on, providing STDP WL1 and STDP WL2 to the gate and source of M22, respectively, thereby changing the threshold voltage and channel resistance of M22 and updating the weight of the electronic synaptic circuit. Of course, as described above, the arrival of the STDP BL high may be caused by the electronic burst circuit itself or by another electronic burst circuit coupled to the neuron circuit 30.
But whichever electronic synaptic circuit initiates, the neuron circuit 30 will emit STDP BL such that the weights of all preceding electronic synaptic circuits coupled thereto will change. Because of the different times at which the input signals are provided by different presynaptic neurons, the weights written may be different or the values at which the threshold voltages and channel resistances of the FeFET transistors are set may be different when the neuron circuit 30 will emit STDP BL to each of the preceding electronic synapses.
When the input signal LIF WL goes high again, the updated weight electronic synaptic circuit 20 will bleed the charge in the capacitor 303 with the updated channel resistance.
To achieve the electronic synaptic property shown in fig. 2, according to one embodiment, for the circuit shown in fig. 3A, as shown in fig. 3B, the waveforms of the input signals STDP WL1 and STDP WL2 are different, and the periods are the same.
According to one embodiment, LIF WL is active or high temporarily, STDP WL2 is also active or high temporarily, and STDP WL1 is active or high temporarily after STDP WL2 is active or high has passed.
According to one embodiment, the falling edge of STDP WL2 substantially coincides with the rising edge of STDP WL 1. According to one embodiment, there is a time interval between the rising edge of STDP WL2 (i.e., the instant when the next high level of LIF WL comes) and the falling edge of STDP WL 1.
According to one embodiment, the amplitude of the STDP WL2 high pulse gradually increases over time. According to one embodiment, the amplitude of the STDP WL1 high pulse gradually decreases over time. According to one embodiment, the maximum values of the magnitudes of the STDP WL1 and STDP WL2 high pulses may be the same or different.
According to one embodiment, to meet the turn-on rules of M23 and M25, the STDP BL high pulse amplitude should be greater than the maximum of the amplitudes of the high pulses of STDP WL1 and STDP WL 2.
FIG. 4 is a graph showing the normalized conductance of an electronic synaptic circuit as a function of time according to one embodiment of the present application. As shown in fig. 4, Δt on the horizontal axis is the time difference between the post-synaptic neuron emission signal time and the preset post-synaptic neuron emission signal time, and Δw on the vertical axis represents the conductivity of M22 in the electronic synaptic circuit. In order to make the curve more visual, the change curve of the conductivity is normalized for Δt.
According to one embodiment, the preset post-synaptic neuron firing signal time in Δt is the time from the high level pulse of STDP BL to the point where the falling edge of STDP WL2 coincides with the rising edge of STDP WL1 (Δt may also be calculated relative to other time, but the resulting change curve differs from fig. 4, and the mechanism of the characteristic curve shown in fig. 2 cannot be implemented). If the high level of STDP BL comes after the falling edge of STDP WL2 coincides with the rising edge of STDP WL1, Δt is positive, STDP WL1 is positive and gradually decreases at this stage, STDP WL2 is 0, and the conductivity of M22 and the corresponding weight change rate of the electronic synapse decrease as Δt increases (the weight change rate of the electronic synapse is positively correlated with the conductivity of M22). If the high level of STDP BL comes before the falling edge of STDP WL2 coincides with the rising edge of STDP WL1, Δt is negative, STDP WL1 is 0 at this stage, STDP WL2 is positive and gradually rises, and the conductivity of M22 and the rate of change of the weight of the corresponding electronic synapse become smaller as Δt increases. The magnitude of the conductance variation of M22 is affected by the high-level maximum amplitude of STDP WL 2.
Of course, different input and control signals may be used depending on the STDP mechanism curves of the different electronic synapses.
In the scheme of the application, the memory characteristic and the nonvolatile characteristic of the FeFET are utilized to apply the FeFET to the electronic synapse, and the threshold voltage and the channel resistance of the FeFET are set by adjusting the voltage value applied to the grid electrode of the FeFET, so that the specific weight of the synapse is set, the circuit design can be simplified to a certain extent, and the functions of a plurality of elements can be realized. Meanwhile, due to the advantages of low power consumption and high operation speed, the power consumption of circuits and equipment can be further reduced, and the operation efficiency is improved. The method is applied to the network design of nerve morphology calculation, and the nerve morphology calculation with low power consumption and high calculation performance can be realized.
In the calculation and optimization process, the circuit does not need to store the calculated weight and intermediate values of other input signals, and also does not need to recall the intermediate values before the next calculation, so that the number of times of line use is reduced, the calculation speed is improved, and the circuit power consumption is reduced.
The above embodiments are provided for illustrating the present application and not for limiting the present application, and various changes and modifications may be made by one skilled in the relevant art without departing from the scope of the present application, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.
Claims (14)
1. A neural network circuit, comprising:
A plurality of neuron circuits, and a plurality of electronic synaptic circuits, wherein at least one of the electronic synaptic circuits is configured to receive input and control signals from one pre-synaptic neuron circuit and to receive feedback signals from one post-synaptic neuron circuit;
Wherein, electron abrupt circuit includes at least:
A switching unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to control a connection state of the electronic synaptic circuit with the post-synaptic neuron circuit under the influence of a control signal from the pre-synaptic neuron circuit;
an input unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to receive first and second input signals from the pre-synaptic neuron circuit under control of a feedback signal from the post-synaptic neuron circuit;
And a weight calculation unit coupled between the switching unit and ground and coupled with the input unit, the weight calculation unit including at least a ferroelectric transistor configured to receive the first and second input signals from the input unit to update a channel resistance of the ferroelectric transistor.
2. The neural network circuit of claim 1,
The post-synaptic neuron circuit comprises at least:
a comparator having a positive input coupled to the switching unit of the electronic synaptic circuit, a negative input configured to receive a preset constant signal, an output coupled to the input unit of the electronic synaptic circuit;
a resistor coupled between the positive input of the comparator and a power supply;
A capacitor coupled between the positive input of the comparator and ground;
The switch unit connects the post-synaptic neuron circuit with the electronic synaptic circuit and the ferroelectric transistor is turned on, the voltage at the positive input of the comparator drops, and the comparator is configured to output the feedback signal when the voltage drops below the preset constant signal.
3. The neural network circuit of claim 2, wherein the switching unit includes at least a first transistor having a control electrode configured to receive the control signal, a first electrode coupled to the positive input of the comparator, and a second electrode coupled to the first electrode of the ferroelectric transistor.
4. The neural network circuit of claim 3, wherein the input unit includes at least,
A second transistor having a control electrode configured to receive the feedback signal, a first electrode configured to receive the first input signal, and a second electrode coupled to a control electrode of the ferroelectric transistor;
A third transistor of a type complementary to the second transistor, a control electrode thereof being configured to receive the feedback signal, a first electrode thereof being grounded, a second electrode thereof being coupled to a control electrode of the ferroelectric transistor;
a fourth transistor having a control electrode configured to receive the feedback signal, a first electrode configured to receive the second input signal, and a second electrode coupled to the second electrode of the ferroelectric transistor;
A fifth transistor of a type complementary to the fourth transistor, the control electrode of which is configured to receive the feedback signal, the first electrode of which is grounded, and the second electrode of which is coupled to the second electrode of the ferroelectric transistor.
5. The neural network circuit of any of claims 2-4, wherein the post-synaptic neuron circuit further comprises a delay unit coupled between the output of the comparator and the input of the input unit and configured to generate a time interval between the active levels of the control signal and the feedback signal.
6. The neural network circuit of any of claims 1-4, wherein a control pole of the ferroelectric transistor is configured to receive the first input signal and a second pole of the ferroelectric transistor is configured to receive the second input signal;
The control signal and the second input signal jump to an active level at the same time, and the first input signal generates an active level when the active level of the second input signal jumps to an inactive level;
The effective level of the second input signal gradually increases during one pulse, and the effective level of the first input signal gradually decreases during one pulse.
7. The neural network circuit of claim 6, wherein the magnitude of the effective level of the feedback signal is greater than the maximum magnitude of the effective level of the first or second input signal.
8. An electronic synaptic circuit configured to receive input and control signals from a pre-synaptic neuron circuit and to receive feedback signals from a post-synaptic neuron circuit;
Wherein, electron abrupt circuit includes at least:
A switching unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to control a connection state of the electronic synaptic circuit with the post-synaptic neuron circuit under the influence of a control signal from the pre-synaptic neuron circuit;
An input unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to receive first and second input signals from the pre-synaptic neuron circuit under control of a feedback signal from the post-synaptic neuron circuit;
And a weight calculation unit coupled between the switching unit and ground and coupled with the input unit, the weight calculation unit including at least a ferroelectric transistor configured to receive the first and second input signals from the input unit to update a channel resistance of the ferroelectric transistor.
9. The electronic synaptic circuit of claim 8, wherein the switching unit comprises at least a first transistor having a control electrode configured to receive the control signal, a first electrode coupled to the post-synaptic neuron circuit, and a second electrode coupled to the first electrode of the ferroelectric transistor.
10. The electronic synaptic circuit of claim 9, wherein the input unit comprises at least,
A second transistor having a control electrode configured to receive the feedback signal, a first electrode configured to receive the first input signal, and a second electrode coupled to a control electrode of the ferroelectric transistor;
A third transistor of a type complementary to the second transistor, the control electrode of which is configured to receive the feedback signal, the first electrode of which is grounded, the second electrode of which is coupled to the control electrode of the ferroelectric transistor;
a fourth transistor having a control electrode configured to receive the feedback signal, a first electrode configured to receive the second input signal, and a second electrode coupled to the second electrode of the ferroelectric transistor;
A fifth transistor of a type complementary to the fourth transistor, the control electrode of which is configured to receive the feedback signal, the first electrode of which is grounded, and the second electrode of which is coupled to the second electrode of the ferroelectric transistor.
11. The electronic synaptic circuit of any of claims 8-10, wherein the control electrode of the ferroelectric transistor is configured to receive the first input signal and the second electrode of the ferroelectric transistor is configured to receive the second input signal;
The control signal and the second input signal jump to an active level at the same time, and the first input signal generates an active level when the active level of the second input signal jumps to an inactive level;
The effective level of the second input signal gradually increases during one pulse, and the effective level of the first input signal gradually decreases during one pulse.
12. The electronic synaptic circuit of claim 11, wherein the magnitude of the active level of the feedback signal is greater than the maximum magnitude of the active level of the first or second input signal.
13. An electronic system comprising a neural network circuit as claimed in any one of claims 1 to 7.
14. An electronic device comprising a neural network circuit as claimed in any one of claims 1 to 7.
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