CN115146770B

CN115146770B - An electronic synaptic circuit and neural network circuit based on ferroelectric tunneling junction

Info

Publication number: CN115146770B
Application number: CN202210870776.3A
Authority: CN
Inventors: 张立宁; 冯宁; 刘保良; 黄如
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2022-07-22
Filing date: 2022-07-22
Publication date: 2025-04-18
Anticipated expiration: 2042-07-22
Also published as: CN115146770A

Abstract

An electronic synaptic circuit and a neural network circuit based on ferroelectric tunneling junction. The application relates to a neural network circuit, which comprises a plurality of neuron circuits and a plurality of electronic synaptic circuits, wherein at least one of the electronic synaptic circuits is configured to receive a first input signal, a second input signal and a control signal from one presynaptic neuron circuit and receive a feedback signal of one postsynaptic neuron circuit, wherein the electronic synaptic circuit at least comprises a switching unit, an input unit and a weight calculating unit, and an electronic system and an electronic device comprising the neural network circuit.

Description

Electronic synaptic circuit and neural network circuit based on ferroelectric tunneling junction

Technical Field

The application relates to the field of neural network circuit design, in particular to an electronic synaptic circuit based on ferroelectric tunneling junction and a neural network circuit.

Background

With the rapid development of information technology industries such as artificial intelligence and big data, the processing speed and performance requirements of computers in social production and daily life are higher and higher. The amount of data that a computer needs to process increases exponentially, which places unprecedented stress on both data storage and computation. The most commonly used computer architecture at present is the traditional von neumann architecture, which has the characteristic of memory separation, so that when a computer processes massive data, the computer has to frequently perform data migration between a microprocessor and a memory, and further the computing speed is greatly reduced, and the energy consumption is greatly increased, namely the von neumann bottleneck.

To solve the problem of von neumann architecture, researchers have diverted their eyes to brain-like computing techniques. The nerve science theory modeling is completed by imitating the connection mode of neurons and synapses in the brain, so that the complex calculation problem that the nerve science theory modeling cannot be processed at high speed in the traditional architecture is solved. The LIF neuron model is one of the most basic models commonly used in neuromorphic computing architecture, and its nature abstracts neurons into capacitances, converting the way neurons communicate into action potentials and impulses. In the LIF neuron model, the electric potential of the electric signal input to the neuron and the stability of the final output pulse are all cores capable of improving the stability and processing speed of the neuron model.

As an emerging calculation paradigm, if the behavior of neurons or synapses is simulated from the physical level by hardware circuits, neuromorphic calculations with low power consumption and high computational performance are expected to be achieved. Therefore, selecting a reasonable calculation method and designing and building a hardware circuit are also important problems for realizing nerve morphology calculation.

Disclosure of Invention

The application provides a neural network circuit, which comprises a plurality of neuron circuits and a plurality of electronic synaptic circuits, wherein at least one of the electronic synaptic circuits is configured to receive a first input signal, a second input signal and a control signal from one pre-synaptic neuron circuit and receive a feedback signal from one post-synaptic neuron circuit, the electronic synaptic circuit at least comprises a switch unit, a weight calculation unit and a weight calculation unit, the switch unit is coupled between the switch unit and the ground and is configured to control the connection state of the electronic synaptic circuit and the post-synaptic neuron circuit under the influence of the control signal from the pre-synaptic neuron circuit, the input unit is coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit and is configured to receive the first input signal and the second input signal from the pre-synaptic neuron circuit under the control of the feedback signal from the post-synaptic neuron circuit, the weight calculation unit is coupled between the switch unit and the ground and is further configured to receive a tunneling signal from the ferroelectric junction, and the tunneling resistance calculation unit is further configured to receive the tunneling signal from the ferroelectric junction.

In particular, the post-synaptic neuron circuit comprises at least a comparator having a negative input coupled to the switching unit of the electronic synaptic circuit, a positive input of the comparator being configured to receive a predetermined constant signal, an output of the comparator being coupled to the input unit of the electronic synaptic circuit, a resistor coupled between the negative input of the comparator and a power supply, a capacitor coupled between the negative input of the comparator and ground, the negative input of the comparator being configured to output the feedback signal when the switching unit connects the post-synaptic neuron circuit to the electronic synaptic circuit and the ferroelectric tunneling junction is conductive and the negative input of the comparator is voltage-dropped when the voltage drops below the predetermined constant signal.

In particular, the switching unit comprises at least a first transistor having a control electrode configured to receive the control signal, a first electrode coupled to the negative input terminal of the comparator, and a second electrode coupled to the first terminal of the ferroelectric tunneling junction.

In particular, the input unit comprises at least a second transistor having a control electrode configured to receive the feedback signal, a first electrode configured to receive the first input signal, a second electrode coupled to a first terminal of the ferroelectric tunneling junction, a third transistor having a control electrode configured to receive the feedback signal, a first electrode configured to receive the second input signal, a second electrode coupled to a second terminal of the ferroelectric tunneling junction, and a fourth transistor of a type complementary to the third transistor, a control electrode configured to receive the feedback signal, a first electrode coupled to ground, and a second electrode coupled to a second terminal of the ferroelectric tunneling junction.

In particular, the post-synaptic neuron circuit further comprises a delay unit coupled between the output of the comparator and the input of the input unit and configured to generate a time interval between the active levels of the control signal and the feedback signal.

In particular, the first terminal of the ferroelectric tunneling junction is configured to receive the first input signal, the second terminal of the ferroelectric tunneling junction is configured to receive the second input signal, the control signal jumps to an active level after the first input signal jumps to an inactive level and before the second input signal jumps to an active level, the first input signal jumps to an active level when the second input signal jumps to an inactive level, the active level of the second input signal gradually increases during one pulse, and the active level of the first input signal gradually decreases during one pulse.

In particular, the magnitude of the effective level of the feedback signal is greater than the maximum magnitude of the effective level of the first input signal or the second input signal.

The application also discloses an electronic synaptic circuit configured to receive a first input signal, a second input signal and a control signal from one presynaptic neuronal circuit and receive a feedback signal from the one presynaptic neuronal circuit, wherein the electronic synaptic circuit at least comprises a switch unit coupled between the presynaptic neuronal circuit and the postsynaptic neuronal circuit and configured to control a connection state of the electronic synaptic circuit and the postsynaptic neuronal circuit under the influence of the control signal from the presynaptic neuronal circuit, an input unit coupled to the presynaptic neuronal circuit and the postsynaptic neuronal circuit and configured to receive the first input signal and the second input signal from the presynaptic neuronal circuit under the control of the feedback signal from the postsynaptic neuronal circuit, and a weight calculation unit coupled between the switch unit and the ground and coupled with the input unit and at least comprising a ferroelectric tunneling junction configured to receive the first input signal and the second input signal from the input unit and a new ferroelectric tunneling junction.

The application also discloses an electronic system comprising the neural network circuit.

The application also discloses an electronic device comprising the neural network circuit.

By adopting the scheme of the application, on one hand, the advantages of low power consumption and high calculation performance can be obtained by simulating the neurons from the physical structure of the circuit, and on the other hand, the signal transmission of the neuron form circuit is optimized by using the STDP mechanism, so that the circuit processing time can be further shortened. The ferroelectric tunneling junction is used in circuit design, so that the power consumption of the circuit can be reduced again through the characteristics of non-volatile property and the like, and the processing speed is improved. The novel neural network circuit structure provided by the scheme also has positive significance for promoting the development of the neural morphology circuit.

Drawings

Preferred embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:

FIG. 1 is a schematic diagram of a neural network circuit model according to one embodiment of the application;

FIG. 2 is a schematic diagram showing the STDP mechanism of electronic synapses;

FIG. 3A is a schematic diagram of an electronic synaptic circuit and a portion of a post-synaptic neuron circuit according to one embodiment of the present application;

FIG. 3B is a timing diagram illustrating the operation of the circuit shown in FIG. 3A;

FIG. 4 is a graph showing the normalized conductance of an electronic synaptic circuit as a function of time according to one embodiment of the present application.

Detailed Description

In the following detailed description of the embodiments, reference is made to the accompanying drawings, which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the application may be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the application. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. For the purpose of illustration only, the connection between elements in the figures is meant to indicate that at least the elements at both ends of the connection are in communication with each other and is not intended to limit the inability to communicate between elements that are not connected. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the output terminals provided, and is not intended to limit the communication between the two units to only signals as shown in the figures.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments of the application. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to embodiments of the present application.

Transistors may refer to transistors of any structure, such as Field Effect Transistors (FETs) or bipolar transistors (BJTs). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, or the like, depending on the channel material. The carriers are electrons or holes, and can be classified into N-type transistors and P-type transistors. The control electrode refers to the grid electrode of the field effect transistor, the first electrode can be the drain electrode or the source electrode of the field effect transistor, the corresponding second electrode can be the source electrode or the drain electrode of the field effect transistor, when the transistor is a bipolar transistor, the control electrode refers to the base electrode of the bipolar transistor, the first electrode can be the collector electrode or the emitter electrode of the bipolar transistor, and the corresponding second electrode can be the emitter electrode or the collector electrode of the bipolar transistor.

The traditional computer architecture divides the equipment into a computing unit and a storage unit, the computing unit is required to be called for completing one-time computing to compute the data to be processed, and then the computing result is stored in the storage unit. When the traditional computer architecture faces larger data and more complex calculation processes, the calculation processes need to be split into a plurality of simple calculation, the steps are repeated for a plurality of times, a plurality of intermediate values are generated before the final calculation result is obtained and stored in a storage unit, and the intermediate values are called to finish the calculation of the final result during calculation.

The artificial neural network circuit (hereinafter referred to as neural network circuit) provided by the application can effectively simplify the complex calculation process, and can avoid the problems caused by calculation separation.

Fig. 1 is a schematic diagram of a neural network circuit model according to one embodiment of the application. The neural network circuit comprises a plurality of nodes, which are also called neurons, and the two neurons can be connected through electronic synapses. The synapse transfers an electrical signal from the electronic presynaptic neuron to the postsynaptic neuron, the path of the transfer depending on the weights of the electronic synapses between the neurons. The higher the weight, the tighter the connection between the two neurons.

As shown in fig. 1, according to one embodiment of the present application, a neuron in a neural network circuit may be connected to a plurality of neurons, and the two neurons are connected and transmit signals through an electronic synapse. The calculations that need to be completed can be converted into multiple round robin calculations in the neural network circuit, and a single calculation process can be converted into a process that starts to transmit signals from the initial neurons set by the user, routes through multiple neurons and electronic synapses, and finally transmits to the target neurons set by the user in the neural network circuit. The neural network circuit automatically adjusts weights among neurons based on a preset learning mechanism, so that calculation processes of different problems are realized.

Each electronic synapse may receive a signal from at least one neuron (referred to as a pre-synaptic neuron relative to the synapse), and/or may send a signal to at least one neuron (referred to as a post-synaptic neuron relative to the synapse).

FIG. 2 is a schematic diagram showing the STDP learning mechanism of electronic synapses. Wherein the time Δt of the horizontal axis represents the time difference between the time at which the post-synaptic neuron transmits a signal and the time at which the pre-synaptic neuron transmits a signal, and the Δw of the vertical axis represents the rate of change of the weight of the electronic synapse. As can be seen from fig. 2, for such an electronic synapse, when Δt is positive, the weight change rate of the electronic synapse decreases with increasing Δt.

In order to prepare an electronic synapse with the STDP learning mechanism characteristic curve, the application provides an electronic synapse circuit. In particular, ferroelectric Tunneling Junctions (FTJ) are included in such electronic synaptic circuits.

With the development of semiconductor device technology, some new devices with adjustable resistance and nonvolatile characteristics have been proposed, including resistive random access memories, phase change memories, ferroelectric Tunneling Junctions (FTJ), and the like. Among them, the ferroelectric tunneling junction has advantages of high density, low power consumption, high operation speed, and the like, and thus has received a great deal of attention from the scientific research and industry.

The FTJ is a novel tunneling junction based on ferroelectric materials, is a heterostructure with an ultrathin ferroelectric layer in the middle and asymmetric conductive layers on two sides, and can change the height of the potential barrier in the whole FTJ when voltage is applied to two ends of the FTJ, so that the tunneling resistance is changed. The structure of the semiconductor device is various, and the common structure is an MFIS structure formed by sequentially stacking four materials of silicon, an insulating layer, a ferroelectric layer and metal, and also is a MFS, MFM, MFIM structure. However, even if the applied voltage is removed, the conduction characteristics are not changed, so that the tunneling resistance of the FTJ remains unchanged until the applied voltage is changed, and the tunneling resistance is set again. Ferroelectric tunneling junctions are therefore often used as linear resistors as memories.

The memory made of the ferroelectric tunneling junction has the advantages of non-volatility, nondestructive reading, high reading and writing speed, low power consumption and the like, and has the advantages of simple structure, small size, easy integration, long service life and the like compared with the traditional ferroelectric memory, and the application range of the ferroelectric memory can be further widened.

FIG. 3A is a schematic diagram of an electronic synaptic circuit and a portion of a post-synaptic neuron circuit according to one embodiment of the application. Fig. 3B is a timing diagram illustrating the operation of the circuit shown in fig. 3A.

As shown in fig. 3A, electronic synaptic circuit 200 is coupled with its post-synaptic neuron circuit 300, while electronic synaptic circuit 200 is also coupled with a pre-synaptic neuron circuit (not shown). According to one embodiment, the pre-synaptic neuron circuit may have a circuit structure similar to a post-synaptic neuron circuit.

According to one embodiment, each neuron circuit may transmit at least four signals, including STDP WL1, STDP WL2, LIF WL, when transmitting signals, which may be provided to a subsequent neuron circuit as a control signal and an input signal by a subsequent synapse, and STDP BL, which may be provided to a preceding synapse as a control signal, the preceding synapse being connected between the neuron circuit and the preceding neuron circuit. The term "front" or "rear" as used herein refers to a state where the signal transmission path is a signal transmission path which is input by a user and is relatively closer to the most-initiated neuron circuit, and a state where the signal transmission path is a signal transmission path which is relatively farther from the most-initiated neuron circuit.

For a particular electronic synaptic circuit, LIF WL determines the connection state of the electronic synaptic circuit to the post-synaptic neuron circuit for the control signal provided by the pre-synaptic neuron circuit. STDP WL1 and STDP WL2 provide input signals to the presynaptic neuronal circuit that determine updated values of the electronic synaptic circuit weights. The feedback signal STDP BL is provided by the post-synaptic neuron circuit and determines the timing of modifying the current weight of the electronic synaptic circuit to the updated value.

According to one embodiment, as shown in fig. 3A, the electronic synaptic circuit 200 may include at least a switching unit 201, an input unit 202 and a weight calculation unit 203.

According to one embodiment, the switching unit 201 may comprise at least an NMOS transistor M21, for example, the gate of which may be configured to receive a control signal LIF WL from a presynaptic neuronal circuit. As shown in fig. 3B, LIF WL includes a plurality of high-level short pulses, and when LIF WL is high, electronic synaptic circuit 200 is activated to conduct an electrical connection with post-synaptic neuron circuit 300.

According to one embodiment, the input unit 202 may include at least NMOS transistors M22 and M23, and PMOS transistor M24, for example.

According to one embodiment, the drain of M22 may be configured to receive the input signal STDP WL1 from one pre-synaptic neuron circuit, the source may be coupled to the weight calculation unit 203, and the gate may be configured to receive the feedback signal STDP BL from the post-synaptic neuron circuit.

According to one embodiment, the drain of M23 may be configured to receive the input signal STDP WL2 from the pre-synaptic neuron circuit, the source may be coupled to the weight calculation unit 203, and the gate may be configured to receive the feedback signal STDP BL from the post-synaptic neuron circuit. Wherein the input signals STDP WL1 and STDP WL2 may be from outputs in the same presynaptic neuron circuit. As shown in fig. 3B, STDP WL1 and STDP WL2 may be pulse signals having the same period and different waveforms.

According to one embodiment, the source of M24 may be coupled to the source and weight calculation unit 203 of M23, the gate may be configured to receive the feedback signal STDP BL from the post-synaptic neuron circuit, and the drain may be grounded.

According to one embodiment, the weight calculation unit 203 may comprise at least a ferroelectric tunnel junction FTJ. According to one embodiment, the first end of the FTJ is coupled to the sources of M21 and M22, and the other end may be coupled to the source of M24.

As shown in fig. 3A, a neuron circuit, such as post-synaptic neuron circuit 300, may comprise at least a comparator 301, a resistor 302, and a capacitor 303. The negative input of comparator 301 may be coupled to electronic synaptic circuit 200 (e.g., may be coupled to the drain of transistor M21) while also being coupled to a power supply via resistor 302. The positive input of the comparator 301 is configured to receive a preset threshold voltage Vth. Once the negative input voltage Vout of the comparator 301 is lower than the positive input voltage Vth, the neuron outputs an output signal Y (including LIF WL ', STDP WL1', and STDP WL2', and STDP BL).

According to one embodiment, the neuron circuit may further comprise a delay unit 304 configured to ensure a certain time difference between the high-level pulse of the STDP BL and the high-level pulse of the LIF WL output by the presynaptic neuron circuit.

According to one embodiment of the application, the FTJ structure and the corresponding ferroelectric layer material and ferroelectric layer thickness, the insulating layer material, the insulating layer thickness, the metal material, the doping type and doping concentration of Si and other parameters are not limited, and can be adjusted according to actual needs.

According to one embodiment of the application, the parameters of the devices such as the gate length, the doping concentration, the gate insulation layer thickness and the like of M21, M22, M23 and M24 are not limited, and can be adjusted according to actual needs.

According to one embodiment, as shown in FIG. 3B, when Vout is higher than Vth, the post-synaptic neuron circuit will not output signal Y and therefore STDP BL is also low. In this case, the transistors M22 and M23 in the input unit 202 are turned off, and at this time, the transistor M24 is turned on, and the resistance value of the FTJ is set at the last time the voltage is applied across them, so that the tunneling resistance of the FTJ is unchanged even though the voltage applied across them is removed at this time.

When LIF WL is high, the charge in capacitor 303 is discharged through the path of FTJ in the electronic synaptic circuit. If Vout drops to a level below Vth after a bleed, the post-synaptic neuron circuit 300 transmits a signal Y and STDL BL jumps to a high level.

According to one embodiment, a neuron circuit has a plurality of preceding electronic shock circuits coupled thereto. When any of these electronic synapse circuits is capable of dropping Vout below the Vth level, the neuron circuit will emit signal Y, and all of the preceding electronic synapse circuits coupled thereto will receive a high level of STDP BL.

However, if Vout cannot be reduced to a level below Vth after a bleed, and other prior electronic synapse circuits have not achieved this goal, the power supply will continue to charge capacitor 303 after LIF WL is high, and the charge in capacitor 303 will be bled again the next time LIF WL is high. After several bleeds or integrations, it is possible to achieve the goal of Vout dropping to a level below Vth.

When STDP BL is high, M24 is turned off, M22 and M23 are turned on, STDP WL1 and STDP WL2 are respectively provided to two ends of FTJ, so that the tunneling resistance value of FTJ is changed, and the weight of the electronic synaptic circuit is updated. Of course, as described above, the arrival of the STDP BL high may be caused by the electronic burst circuit itself, or may be caused by other electronic burst circuits coupled to the neuron circuit 300.

But whichever electronic synaptic circuit initiates, the neuron circuit 300 will emit STDP BL such that the weights of all preceding electronic synaptic circuits coupled thereto will change. Because of the different times at which the input signals are provided by different presynaptic neurons, the weights written may be different or the tunneling resistance of ferroelectric tunneling junction FTJ may be set to a different value when neuron circuit 300 is to emit STDP BL to each preceding electronic synapse.

When the input signal LIF WL goes high again, the updated weight electronic synaptic circuit 200 will bleed the charge in the capacitor 303 with the updated tunneling resistance.

To achieve the electronic synaptic property shown in fig. 2, according to one embodiment, for the circuit shown in fig. 3A, as shown in fig. 3B, the waveforms of the input signals STDP WL1 and STDP WL2 are different, and the periods are the same.

According to one embodiment, LIF WL may transition to an active level at the same time or after STDP WL1 transitions from an active level to an inactive level and at the same time or before STDP WL2 transitions to an active level. When STDP WL2 transitions from an active level to an inactive level, STDP WL1 transitions to an active level.

According to one embodiment, the falling edge of STDP WL2 substantially coincides with the rising edge of STDP WL 1. According to one embodiment, there is a time interval between the rising edge of STDP WL2 and the falling edge of STDP WL 1. According to one embodiment of the application, the instant at which the next high level of LIF WL comes is located in the time interval between the falling edge of STDP WL1 and the rising edge of STDP WL 2.

According to one embodiment, the amplitude of the STDP WL2 high pulse gradually increases over time. According to one embodiment, the amplitude of the STDP WL1 high pulse gradually decreases over time. According to one embodiment, the maximum or minimum value of the amplitude of the STDP WL1 and STDP WL2 high pulses may be the same or different depending on the ferroelectric layer material characteristics.

According to one embodiment, to meet the turn-on rules of M22 and M23, the STDP BL high pulse amplitude should be greater than the maximum of the amplitudes of the high pulses of STDP WL1 and STDP WL 2.

FIG. 4 is a graph showing the normalized conductance of an electronic synaptic circuit as a function of time according to one embodiment of the present application. As shown in fig. 4, Δt on the horizontal axis is the time difference between the post-synaptic neuron emission signal time and the preset post-synaptic neuron emission signal time, and Δw on the vertical axis represents the conductivity of M22 in the electronic synaptic circuit. In order to make the curve more visual, the change curve of the conductivity is normalized for Δt.

According to one embodiment, the preset post-synaptic neuron firing signal time in Δt is the time from the high level pulse of STDP BL to the point where the falling edge of STDP WL2 coincides with the rising edge of STDP WL1 (Δt may also be calculated relative to other time, but the resulting change curve differs from fig. 4, and the mechanism of the characteristic curve shown in fig. 2 cannot be implemented). If the high level of STDP BL comes after the falling edge of STDP WL2 coincides with the rising edge of STDP WL1, Δt is positive, STDP WL1 is positive and gradually decreases at this stage, STDP WL2 is 0, and the conductivity of the FTJ and the corresponding weight change rate of the electronic synapse become smaller as Δt increases (the weight change rate of the electronic synapse is positively correlated with the conductivity of the FTJ). If the high level of STDP BL comes before the falling edge of STDP WL2 coincides with the rising edge of STDP WL1, Δt is negative, STDP WL1 is 0 at this stage, STDP WL2 is positive and gradually rises, and the conductivity of M22 and the rate of change of the weight of the corresponding electronic synapse become smaller as Δt increases. The magnitude of the conductance change of FTJ is affected by the high-level maximum amplitude of STDP WL 2.

Of course, different input and control signals may be used depending on the STDP mechanism curves of the different electronic synapses.

According to the scheme of the application, the memory characteristic and the nonvolatile characteristic of the Ferroelectric Tunneling Junction (FTJ) are utilized to apply the ferroelectric tunneling junction to the electronic synapse, and the tunneling resistance of the FTJ is set by adjusting the voltage value applied to the two ends of the FTJ, so that the specific weight of the synapse is set, the circuit design can be simplified to a certain extent, and the functions of a plurality of elements can be realized. Meanwhile, due to the advantages of high density, low power consumption and high operation speed, the power consumption of circuits and equipment can be further reduced, and the operation efficiency is improved. The method is applied to the network design of nerve morphology calculation, and the nerve morphology calculation with low power consumption and high calculation performance can be realized.

In the calculation and optimization process, the circuit does not need to store the calculated weight and intermediate values of other input signals, and also does not need to recall the intermediate values before the next calculation, so that the number of times of line use is reduced, the calculation speed is improved, and the circuit power consumption is reduced.

The above embodiments are provided for illustrating the present application and not for limiting the present application, and various changes and modifications may be made by one skilled in the relevant art without departing from the scope of the present application, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.

Claims

1. A neural network circuit, comprising:

a plurality of neuron circuits, and a plurality of electronic synaptic circuits, wherein at least one of the electronic synaptic circuits is configured to receive a first input signal, a second input signal and a control signal from one pre-synaptic neuron circuit and to receive a feedback signal from one post-synaptic neuron circuit;

Wherein, electron abrupt circuit includes at least:

a switching unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to control a connection state of the electronic synaptic circuit with the post-synaptic neuron circuit under the influence of a control signal from the pre-synaptic neuron circuit;

an input unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to receive a first input signal and a second input signal from the pre-synaptic neuron circuit under control of a feedback signal from the post-synaptic neuron circuit;

And a weight calculation unit coupled between the switch unit and ground and coupled to the input unit, the weight calculation unit including at least a ferroelectric tunneling junction configured to receive the first and second input signals from the input unit to update a tunneling resistance of the ferroelectric tunneling junction.

2. The neural network circuit of claim 1, wherein

The post-synaptic neuron circuit comprises at least:

A comparator having a negative input coupled to the switching unit of the electronic synaptic circuit, a positive input configured to receive a preset constant signal, and an output coupled to the input unit of the electronic synaptic circuit;

a resistor coupled between the negative input of the comparator and a power supply;

A capacitor coupled between the negative input of the comparator and ground;

When the switch unit connects the post-synaptic neuron circuit with the electronic synaptic circuit and the ferroelectric tunneling junction is turned on, the voltage of the negative input terminal of the comparator drops, and when the voltage drops below the preset constant signal, the comparator is configured to output the feedback signal.

3. The neural network circuit of claim 2, wherein the switching unit comprises at least a first transistor having a control electrode configured to receive the control signal, a first electrode coupled to the negative input of the comparator, and a second electrode coupled to the first end of the ferroelectric tunneling junction.

4. The neural network circuit of claim 3, wherein the input unit includes at least,

A second transistor having a control electrode configured to receive the feedback signal, a first electrode configured to receive the first input signal, and a second electrode coupled to a first end of the ferroelectric tunneling junction;

A third transistor having a control electrode configured to receive the feedback signal, a first electrode configured to receive the second input signal, and a second electrode coupled to a second end of the ferroelectric tunneling junction;

A fourth transistor of a type complementary to the third transistor, the control electrode of which is configured to receive the feedback signal, the first electrode of which is grounded, and the second electrode of which is coupled to the second end of the ferroelectric tunneling junction.

5. The neural network circuit of any of claims 2-4, wherein the post-synaptic neuron circuit further comprises a delay unit coupled between an output of the comparator and an input of the input unit configured to generate a time interval between the active levels of the control signal and the feedback signal.

6. The neural network circuit of any of claims 1-4, wherein a first end of the ferroelectric tunneling junction is configured to receive the first input signal and a second end of the ferroelectric tunneling junction is configured to receive the second input signal;

The control signal jumps to an active level after the first input signal jumps to an inactive level and before the second input signal jumps to an active level, the first input signal jumps to an active level when the second input signal jumps to an inactive level;

The effective level of the second input signal gradually increases during one pulse, and the effective level of the first input signal gradually decreases during one pulse.

7. The neural network circuit of claim 6, wherein the magnitude of the effective level of the feedback signal is greater than the maximum magnitude of the effective level of the first or second input signals.

8. An electronic synaptic circuit configured to receive a first input signal, a second input signal and a control signal from a pre-synaptic neuron circuit and to receive a feedback signal from a post-synaptic neuron circuit;

Wherein, electron abrupt circuit includes at least:

9. The electronic synaptic circuit of claim 8, wherein the switching unit comprises at least a first transistor having a control electrode configured to receive the control signal, a first electrode coupled to the post-synaptic neuron circuit, and a second electrode coupled to a first end of the ferroelectric tunneling junction.

10. The electronic synaptic circuit of claim 9, wherein the input unit comprises at least,

11. The electronic synaptic circuit of any of claims 8-10, wherein a first terminal of the ferroelectric tunneling junction is configured to receive the first input signal and a second terminal of the ferroelectric tunneling junction is configured to receive the second input signal;

12. The electronic synaptic circuit of claim 11, wherein the magnitude of the effective level of the feedback signal is greater than the maximum magnitude of the effective level of the first input signal or the second input signal.

13. An electronic system comprising the neural network circuit of any one of claims 1-7.

14. An electronic device comprising the neural network circuit of any one of claims 1-7.