CN115000168A - P-type nitride enhanced HEMT device and preparation method thereof - Google Patents
P-type nitride enhanced HEMT device and preparation method thereof Download PDFInfo
- Publication number
- CN115000168A CN115000168A CN202210721922.6A CN202210721922A CN115000168A CN 115000168 A CN115000168 A CN 115000168A CN 202210721922 A CN202210721922 A CN 202210721922A CN 115000168 A CN115000168 A CN 115000168A
- Authority
- CN
- China
- Prior art keywords
- layer
- nitride cap
- cap layer
- thickness
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
- H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
一种P型氮化物增强型HEMT器件及其制备方法，用传统制备方法淀积氮化镓帽层并进行Mg杂质掺杂后，不再进一步刻蚀掉非栅极下的氮化物帽层，而是继续经过淀积刻蚀形成一层n型掺杂的GaN保护层，然后再对栅极下方的氮化镓帽层进行退火，使得Mg杂质被激活，形成P型氮化物帽层。栅电极下方激活的原Mg掺杂氮化物帽层耗尽了栅下沟道中的二维电子气，提高了器件的阈值电压，实现增强型器件。同常规P型氮化物增强型HEMT器件采用的干法刻蚀工艺相比，该制备方法避免制作时的干法刻蚀步骤，减少了刻蚀对势垒层表面的损伤，极少了表面态引起的动态电阻退化和可靠性退化；增大了产品的片内均匀性和批次重复性，提高了产品良率。
A P-type nitride enhanced HEMT device and a preparation method thereof. After depositing a gallium nitride cap layer and doping with Mg impurities by a traditional preparation method, the nitride cap layer under the non-gate is not further etched away, Instead, a layer of n-type doped GaN protective layer is formed by deposition and etching, and then the gallium nitride cap layer under the gate is annealed to activate the Mg impurities to form a p-type nitride cap layer. The activated original Mg-doped nitride capping layer under the gate electrode depletes the two-dimensional electron gas in the channel under the gate, which increases the threshold voltage of the device and realizes the enhancement mode device. Compared with the dry etching process used in conventional P-type nitride enhanced HEMT devices, the preparation method avoids the dry etching step during fabrication, reduces the damage to the surface of the barrier layer by etching, and reduces the surface state Induced dynamic resistance degradation and reliability degradation; increased product on-chip uniformity and batch repeatability, and improved product yield.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a P-type nitride enhanced HEMT device and a preparation method thereof.
Background
Gallium nitride is a typical material of third-generation semiconductors, has a large forbidden band width (3.4eV), high electron mobility and high electron saturation velocity, and has a wide application potential in the fields of next-generation radio frequency devices, power electrical devices and the like. Particularly, gallium nitride materials and other group III-V nitride materials (e.g., AlGaN) can form High Electron Mobility Transistors (HEMTs) having a heterojunction structure because spontaneous polarization and piezoelectric polarization effects characteristic of nitride materials form a high concentration (1 × 10) at the heterojunction interface 13 cm -2 ) And high mobility (2000 cm) 2 V.s), and thus GaN HEMT has the characteristics of high breakdown voltage, low on-resistance, high switching frequency, small size and the like, and has become a future power switch due to the characteristics of high frequency, high efficiency, high temperature resistance, small size and the likeOne of the important candidates for a device. The P-type nitride enhanced HEMT is taken as a first-generation GaN power switch device and has important application in the fields of future wireless charging, envelope tracking, laser radar, electric vehicles and the like.
Because the concentration of 2DEG (two-dimensional electron gas) at the nitride heterojunction interface is very high and is formed when the heterojunction structure is formed, and the gate Schottky barrier of the device cannot completely exhaust the 2DEG below the gate, the prepared nitride high electron mobility device is depletion type, and a certain reverse voltage is required to be applied to the gate to ensure that the two-dimensional electron gas in the channel of the device is depleted to reach an off state. However, when the gallium nitride-based HEMT is applied to various high-power applications as a power electronic device, an enhancement transistor is usually preferred to ensure the safe operation of the power electronic system and reduce the requirements of a negative voltage generating circuit and a protection circuit, thereby simplifying the circuit and system design, reducing static power consumption and the like.
Currently, reported methods for implementing a gallium nitride based enhancement type HEMT device include a Cascode structure, a thin barrier layer, a trench gate, a pn junction under the gate, fluorine plasma implantation under the gate, and the like, wherein a P-type gallium nitride is taken as a gate cap layer (see fig. 1, fig. 2, and fig. 3) because of its excellence in high threshold voltage (about 2V), high gate voltage swing, good threshold voltage stability, and the like, so that the P-type gallium nitride is favored by the industry, and has become a main method for implementing a gallium nitride based enhancement type HEMT device.
However, the technology still has defects at present, and since various research institutions and enterprises at present basically adopt a dry etching method to prepare a P-nitride enhanced device, the P-nitride enhanced device is usually prepared based on an AlGaN/GaN heterojunction material, and a P-cap layer required in the device is a region below a gate electrode, the nitride cap layer needs to be etched in a large-area and very precise dry etching manner, and even if P-nitride residues of several nm or over-etching of a barrier layer can have serious influence on a channel region of the device. However, the etching selection ratio of the current dry etching process to the P-type nitride cap layer and the barrier layer is not very high, and meanwhile, the etching effect in the ICP dry etching, such as the micro-trench effect, the load effect and the like, can have important influences on the uniformity, the yield and the like of the device. In addition, a plasma physical bombardment process exists in the ICP dry etching, so that the barrier layer can be damaged by plasma in the etching process, and the performance of the device is further influenced.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a P-type nitride enhanced HEMT device and a preparation method thereof, so as to improve the device performance, optimize the process and improve the yield.
In order to achieve the purpose, the invention adopts the technical scheme that:
a P-type nitride enhanced HEMT device comprises a substrate, a composite buffer layer, a channel layer and a barrier layer from bottom to top, wherein the barrier layer is provided with a P-type nitride cap layer, an Mg-doped nitride cap layer, a source electrode and a drain electrode; the P-type nitride cap layer is separated from the source electrode and the drain electrode by the Mg-doped nitride cap layer, and the gate electrode is arranged above the P-type nitride cap layer.
The invention also provides a preparation method of the P-type nitride enhanced HEMT device, which comprises the following steps:
s1: sequentially epitaxially growing a III-nitride on a substrate to serve as a composite buffer layer, a channel layer, a barrier layer, an original Mg-doped nitride cap layer and an n-type doped GaN protective layer;
s2: removing the GaN protective layer at the position corresponding to the lower part of the gate electrode, annealing at high temperature to activate the part of the original Mg-doped nitride cap layer corresponding to the position below the gate electrode to form a P-type nitride cap layer, keeping the original Mg-doped nitride cap layers in other regions in a high-resistance state, and removing the rest GaN protective layer;
s3: preparing electrical isolation of the device on the barrier layer, the channel layer and the original Mg-doped nitride cap layer;
s4: removing part of the original Mg-doped nitride cap layer on the surface of the barrier layer, preparing a source electrode and a drain electrode at the removed positions, and performing high-temperature thermal annealing to form ohmic contact with two-dimensional electron gas, wherein the rest original Mg-doped nitride cap layer comprises two parts which are respectively positioned between the P-type nitride cap layer and the source electrode and between the P-type nitride cap layer and the drain electrode, namely the Mg-doped nitride cap layer;
s5: and preparing a gate electrode on the P-type nitride cap layer, and forming Schottky contact with the Mg-doped nitride cap layer.
In one embodiment, the substrate is one of silicon, sapphire, silicon carbide, diamond; the group III nitride is a multi-component compound consisting of one or two or more of gallium nitride, aluminum nitride and indium nitride.
In one embodiment, the composite buffer layer comprises three layers, namely a nucleation layer, a transition layer and a buffer layer from bottom to top, and in S1, a group iii nitride nucleation layer, a transition layer and a buffer layer are sequentially grown as the composite buffer layer; the material of the nucleation layer is AlN or GaN, and the thickness is 100-300 nm; the transition layer is made of AlGaN and has a thickness of 200-1000 nm; the buffer layer is made of GaN or AlGaN and has a thickness of 100-3000 nm.
In one embodiment, the S1 employs a metal organic chemical vapor deposition MOCVD method, in which the nucleation layer is grown by the MOCVD method under the low temperature conditions of 500-.
In one embodiment, the material of the channel layer is GaN or InGaN, and the thickness is 50nm-500 nm; the barrier layer is made of AlGaN or InAlN or AlN or InAlGaN and has a thickness of 2-40 nm; the original Mg-doped nitride cap layer is made of GaN or InGaN, the doped impurity is Mg, and the doping concentration is 1 multiplied by 10 17 -7×10 19 cm -3 The thickness is 50-200 nm; the GaN protective layer is doped with Si with a doping concentration of 1 × 10 16 -1×10 20 cm -3 The thickness is 50-500 nm.
In one embodiment, an isolating layer is arranged between the barrier layer and the channel layer, wherein the isolating layer is made of AlN and has a thickness of 0.5-2 nm.
In one embodiment, two layers of metal are adopted for the gate electrode, and the material of the lower layer is Ti, Ni, Al, Ta, TiN or TaN; the source electrode and the drain electrode are made of four layers of metal, and the lowest two layers are made of Ti/Al or Ta/Al or Mo/Al.
In one embodiment, in S2, the GaN protection layer is removed by photolithography and etching; s4, preparing a source electrode and a drain electrode by adopting a vacuum evaporation or magnetron sputtering technology; and S5, preparing a gate electrode on the P-type nitride cap layer by adopting a vacuum evaporation or magnetron sputtering technology.
In one embodiment, the process conditions of the high temperature annealing at S2 are: using N at a temperature of 600 deg.C 2 Annealing for 20min in the atmosphere; the process conditions of the high-temperature thermal annealing of S4 are as follows: the rapid thermal annealing was performed at 850 deg.c for 30 seconds in a nitrogen atmosphere.
Compared with the prior art, the invention has the beneficial effects that:
firstly, the preparation method avoids the dry etching step in the manufacturing process of the conventional P-type nitride cap layer, reduces the surface etching damage of the barrier layer, reduces the surface state of the barrier layer by covering the GaN cap layer, reduces the current collapse effect and the grid leakage, and improves the performance of the device.
Secondly, the technology provided by the invention is compatible with the original process, the process manufacturing steps are relatively simple, and the device performance improvement effect is obvious.
Drawings
Fig. 1 is a schematic structural view (cross-sectional view) of a P-type nitride enhanced HEMT device of the present invention.
Fig. 2 is a schematic diagram showing the structure of a protective layer, a composite buffer layer and an isolation layer in the P-type nitride enhanced HEMT device of the present invention.
Fig. 3 is a schematic structural view (top view) of the P-type nitride enhanced HEMT device of the present invention.
FIG. 4 is a process flow diagram of the present invention.
Fig. 5 is a schematic view of a manufacturing process of the P-type nitride enhanced HEMT device of the present invention.
Detailed Description
The embodiments of the present invention will be described in detail below with reference to the drawings and examples.
As shown in fig. 1, fig. 2 and fig. 3, the present invention firstly provides a P-type nitride enhancement HEMT device, which has a structure comprising a substrate 1, a composite buffer layer 2, a channel layer 3 and a barrier layer 4 from bottom to top, wherein the barrier layer 4 is provided with a P-type nitride cap layer 51, a Mg-doped nitride cap layer 52, a source electrode 6 and a drain electrode 7. The P-type nitride cap layer 51 is separated from the source electrode 6 and from the drain electrode 7 by Mg-doped nitride cap layer 52. A gate electrode 8 is provided on the P-type nitride cap layer 51, and the gate electrode 8 forms a schottky contact with the P-type nitride cap layer 51. The source electrode 6 and the drain electrode 7 both form ohmic contact with the barrier layer 4; a heterojunction is formed between the channel layer 3 and the barrier layer 4, and a two-dimensional electron gas channel is formed on the channel layer 3 side of the heterojunction interface by a polarization effect.
Referring to fig. 4, the invention also provides a method for manufacturing the device, comprising the following steps:
s1: sequentially epitaxially growing a III-nitride on a substrate 1 to serve as a composite buffer layer 2, a channel layer 3, a barrier layer 4, an original Mg-doped nitride cap layer 5 and an n-type doped GaN protective layer 9. The process of the step can adopt a Metal Organic Chemical Vapor Deposition (MOCVD) method.
S2: and removing the GaN protective layer 9 at the position corresponding to the lower part of the gate electrode 8, annealing at high temperature to activate the part of the original Mg-doped nitride cap layer 5 corresponding to the lower part of the gate electrode 8 to form a P-type nitride cap layer 51, keeping the original Mg-doped nitride cap layer 5 in the other area in a high-resistance state, and removing the rest GaN protective layer 9. In this step, the GaN protection layer 9 may be removed by photolithography and etching.
S3: electrical isolation of the device is fabricated on the barrier layer 4, the channel layer 3 and the original Mg-doped nitride cap layer 5.
S4: and removing part of the original Mg-doped nitride cap layer 5 on the surface of the barrier layer 4, preparing a source electrode 6 and a drain electrode 7 at the removed positions, and performing high-temperature thermal annealing to form ohmic contact with two-dimensional electron gas, wherein the rest original Mg-doped nitride cap layer 5 comprises two parts which are respectively positioned between the P-type nitride cap layer 51 and the source electrode 6 and between the P-type nitride cap layer 51 and the drain electrode 7, namely an Mg-doped nitride cap layer 52. In this step, the source electrode 6 and the drain electrode 7 are prepared by vacuum evaporation or magnetron sputtering.
S5: the gate electrode 8 is prepared on the P-type nitride cap layer 51 to form a schottky contact with the P-type nitride cap layer 51. In this step, the gate electrode 8 is prepared by vacuum evaporation or magnetron sputtering.
In the invention, after the gallium nitride cap layer is deposited by using the traditional preparation method and Mg impurity is doped, the nitride cap layer under the non-grid electrode is not further etched, but an n-type GaN protective layer is formed by deposition and etching continuously, and then the gallium nitride cap layer under the grid electrode is annealed, so that the Mg impurity is activated to form a P-type nitride cap layer. The original Mg doped nitride cap layer 51 activated below the gate electrode 8 depletes the two-dimensional electron gas in the channel under the gate, improves the threshold voltage of the device, and realizes an enhanced device.
Compared with the dry etching process adopted by the conventional preparation method of the P-type nitride enhanced HEMT device, the preparation method avoids the dry etching step in the conventional P-type nitride preparation process, reduces the damage of etching on the surface of the barrier layer 4, and reduces the dynamic resistance degradation and reliability degradation caused by the surface state; the uniformity and batch repeatability in the chip of the product are improved, and the yield of the product is improved.
In the present invention, the substrate 1 may be one of silicon, sapphire, silicon carbide, and diamond.
In the present invention, the composite buffer layer 2, the channel layer 3, and the barrier layer 4 each employ a group iii nitride semiconductor such as gallium nitride, aluminum nitride, indium nitride, or a multi-component compound of two or more of them.
Illustratively, in the present invention, the composite buffer layer 2 may include three layers, as shown in fig. 2, the nucleation layer 21, the transition layer 22 and the buffer layer 23 are respectively formed from bottom to top, and in S1, the group iii nitride nucleation layer 21, the transition layer 22 and the buffer layer 23 are sequentially grown, and as the composite buffer layer 2, specifically, the nucleation layer 21 may be grown by the MOCVD method under the low temperature conditions of 500-. Wherein AlN or GaN can be used as the material of the nucleation layer 21, and the thickness is 100-300 nm; the material of the transition layer 22 can adopt AlGaN with the thickness of 200-1000nm, and preferably, it can adopt gradient AlGaN with the composition being gradually changed from 0.75 to 0.15. The buffer layer 23 can be made of GaN or AlGaN with a thickness of 100-3000 nm.
Illustratively, in the present invention, the material of the channel layer 3 may be GaN or InGaN, and the thickness is 50nm to 500 nm. The barrier layer 4 can be made of AlGaN, InAlN, AlN or InAlGaN, and has a thickness of 2-40 nm; the original Mg-doped nitride cap layer 5 can be made of GaN or InGaN, the doped impurity is Mg, and the doping concentration is 1 multiplied by 10 17 -7×10 19 The thickness is 50-200 nm; a GaN protective layer 9 doped with Si at a concentration of 1 × 10 16 -7×10 20 The thickness is 50-500 nm.
Illustratively, in the present invention, two layers of metal are used for the gate electrode 8, the upper layer is made of Au, and the lower layer is made of Ti, Ni, Al, Ta, TiN or TaN; the source electrode 6 and the drain electrode 7 adopt four layers of metal of Ti/Al/Ni/Au, wherein the materials of the two lowest layers adopt Ti/Al or Ta/Al or Mo/Al.
Illustratively, in the present invention, a separation layer 31 may be further disposed between the barrier layer 4 and the channel layer 3, and the material of the separation layer 31 may be AlN and have a thickness of 0.5-2 nm.
Illustratively, in the present invention S2, the process conditions of the high temperature annealing are: using N at a temperature of 600 deg.C 2 Annealing for 20min in the atmosphere; so that the chemical bond between Mg ions and H ions in the gallium nitride cap layer which is not protected by the protective layer is broken, the conductivity of Mg is activated, a P-type gallium nitride cap layer is formed, and the gallium nitride cap layer which is protected by the protective layer still has a high-resistance state.
In the invention S4, the process conditions of the high-temperature thermal annealing are as follows: rapid thermal annealing was performed at 850 deg.c for 30 seconds in a nitrogen atmosphere, so that the source electrode 6, the drain electrode 7, and the barrier layer 4 formed ohmic contacts.
Referring to fig. 5, the present invention provides the following three examples of the preparation of the above device:
example 1: the substrate 1 is made of P-type silicon with the thickness of 725 mu m and is nucleatedLayer 21 is aluminum nitride and has a thickness of 200 nm. The transition layer 22 is made of AlGaN, the thickness is 800nm, and the aluminum component is gradually changed from 0.75 to 0.15. The buffer layer 23 is made of gallium nitride and has a thickness of 1000nm, and the channel layer 3 is made of gallium nitride and has a thickness of 300 nm. The barrier layer 4 is made of aluminum gallium nitride, the aluminum component is 0.15, and the thickness is 10 nm. The isolation layer 31 is made of aluminum nitride and has a thickness of 1 nm. The thickness of the original Mg-doped nitride cap layer 5 is 100nm, the doped impurity is Mg, and the doping concentration is 3x10 19 cm -3 (ii) a An n-type doped GaN protective layer 9 doped with Si at a concentration of 1 × 10 18 cm -3 The thickness is 100 nm. The transistor is characterized in that the lowest two layers of metal of the source electrode 6 and the drain electrode 7 are Ti/Al, and the lowest layer of metal of the gate electrode 8 is Ni.
The preparation method comprises the following steps:
step one, the silicon substrate is cleaned, as shown in a in fig. 5.
And introducing hydrogen into the reaction chamber at the high temperature of 1000 ℃, removing pollutants on the surface of the substrate 1, and forming a microscopic step structure on the surface of the substrate so as to grow various epitaxial layers by a subsequent epitaxial process.
Step two, epitaxially growing a composite buffer layer 2 on the substrate 1, as shown in fig. 5 b.
The composite buffer layer 2 comprises three layers, namely a nucleation layer 21 with the thickness of 200nm is grown on the substrate by an MOCVD method under the low temperature condition of 500 ℃.
Then, the temperature is raised to 1000 ℃, a transition layer 22 with the thickness of 800nm is grown on the nucleation layer 21 by the MOCVD method, and then a buffer layer 23 with the thickness of 1000nm is grown on the transition layer 22.
Step three, manufacturing a channel layer 3, an isolation layer 31, a barrier layer 4 and an original Mg-doped nitride cap layer 5, as shown in c in FIG. 5.
A channel layer 3 having a thickness of 300nm is first grown on the buffer layer 23 at a temperature of 1000 c by using an MOCVD method.
Then, a 1nm spacer layer 31 was epitaxially formed on the channel layer 3, and a 10nm thick barrier layer 4 was epitaxially formed on the spacer layer 31.
A nitride cap layer was then epitaxially grown on the barrier layer 4 while doping with Mg at a concentration of 3 × 10 19 cm -3 And forming an original Mg doped nitride cap layer 5.
Step four, growing the GaN protection layer 9 as shown in d of fig. 5.
A GaN protective layer 9 with the thickness of 100nm is generated above the whole original Mg-doped nitride cap layer 5 by adopting the MOCVD technology, the GaN protective layer 9 is grown and simultaneously doped with silicon, and the doping concentration is 1 multiplied by 10 18 cm -3 An n-type doped GaN protection layer 9 is formed.
And step five, activating the nitride cap layer, as shown by e and f in figure 5.
A photoresist mask is made by using a photolithography process to expose a portion of the surface of the GaN protection layer 9, and the GaN protection layer 9 without the photoresist mask is removed by using reactive ion etching equipment and technology (RIE) to expose a middle portion of the nitride cap layer, as shown in fig. 5 e.
Then N at 600 ℃ is used 2 Annealing is carried out for 20min in the atmosphere, so that chemical bonds between Mg ions and H ions in the gallium nitride cap layer which is not protected by the protective layer are broken, the conductivity of Mg is activated, a P-type gallium nitride cap layer 51 is formed, and the original Mg-doped nitride cap layer 5 which is protected by the protective layer is still in a high-resistance state.
Finally, the GaN protection layer 9 is removed by dry etching, as shown in fig. f.
And step six, cleaning.
And (3) placing the sample wafer which is subjected to the steps in acetone to remove organic pollutants on the surface, then placing the sample wafer in an acidic solvent to remove a surface oxidation layer and inorganic pollutants, finally removing the surface solvent by using deionized water, and drying the sample wafer in a nitrogen atmosphere.
And step seven, etching the mesa to manufacture isolation, as shown in g in figure 5.
And manufacturing a photoresist mask by adopting a photoetching process, exposing partial surface of the nitride cap layer, etching the Mg-doped nitride cap layer 52, the barrier layer 4, the channel layer 3 and partial buffer layer 23 which are not covered by the photoresist mask by adopting reactive ion etching equipment and technology (RIE), and etching to form a table top with neat edges and steep side walls to form an isolation region between different transistors.
Step eight, the source electrode 6 and the drain electrode 7 are fabricated as shown by h in fig. 5.
And manufacturing a photoresist mask by adopting a photoetching process, exposing partial surface of the nitride cap layer, etching and removing the nitride cap layer without being covered by the photoresist mask by adopting reactive ion etching equipment and RIE (reactive ion etching), and cleaning the residual photoresist.
And then, a photoresist mask is manufactured by adopting a photoetching process, and the areas where the source electrode 6 and the drain electrode 7 are to be manufactured are exposed. Growing a plurality of layers of metal Ti/Al/Ni/Au in the area by an electron beam evaporation mode, namely Ti with the thickness of 20nm, Al with the thickness of 120nm, Ni with the thickness of 40nm and Au with the thickness of 50nm from bottom to top in sequence, and forming a source electrode 6 and a drain electrode 7 after stripping.
And finally, performing rapid thermal annealing for 30s in a nitrogen atmosphere at 850 ℃ so that the source electrode 6, the drain electrode 7 and the barrier layer 4 form ohmic contact.
Step nine, a gate electrode 8 is fabricated as shown by i in fig. 5.
A photoresist mask is made by a photolithography process to expose the region where the gate electrode 8 is to be made.
Then, the gate electrode metal of the Ni/Au combination is prepared by using an electron beam evaporation technology, wherein the thickness of Ni is 50nm, the thickness of Au is 150nm, and a gate electrode 8 is formed after stripping, as shown in i in FIG. 5.
And finally, thermally annealing at 460 ℃ for 10min to form Schottky contact between the gate electrode 8 and the P-type nitride cap layer 51, thereby completing the manufacture of the whole device.
Example 2: a substrate 1 of silicon carbide material is selected, P-type doping is carried out, and the thickness is 300 mu m. The nucleation layer 21 is made of gallium nitride and has a thickness of 200 nm. The transition layer 22 is Al 0.55 Ga 0.25 N, thickness 500nm, aluminum composition 0.55. The buffer layer 23 is made of Al 0.05 Ga 0.25 N, 0.05 of aluminum component and 1000nm of thickness. The material of the channel layer 3 is gallium nitride, and the thickness is 300 nm. The barrier layer 4 is made of Al 0.15 Ga 0.25 N, 0.15 component and 15nm thickness. The isolation layer 31 is made of AlN and has a thickness of 1.5 nm. The original Mg-doped nitride cap layer 5 is made of gallium nitride, the thickness is 60nm, and the doping concentration is 5x10 19 cm -3 (ii) a n-type doped GaN protective layer 9, dopingThe impurity is Si, and the doping concentration is 2X 10 18 And the thickness is 60 nm. The transistor is characterized in that the two layers of the lowest layer of the source electrode 6 and the drain electrode 7 are Ta/Al, and the layer of the lowest layer of the gate electrode 8 is Ti.
The substrate 1 is placed in organic acetone solution to wash away grease and pollutants on the surface of the substrate, then is washed by flowing deionized water, and then is dried by high-purity nitrogen.
2.1) growing a 200nm nucleating layer 21 on the surface of the substrate 1 by adopting an MOCVD method under the low temperature condition of 600 ℃.
2.2) raising the temperature to 1000 ℃, and growing a transition layer 22 with the thickness of 500nm and a buffer layer 23 with the thickness of 1000nm on the aluminum nitride nucleation layer by using the MOCVD method.
3.1) growing a channel layer 3 with a thickness of 300nm on the buffer layer by using an MOCVD method at a temperature of 1000 ℃.
3.2) a 1.5nm spacer layer 31 is epitaxially formed on the channel layer 3. Finally, a 15nm thick barrier layer 4 is epitaxially grown on the spacer layer 31.
3.3) then epitaxial nitride cap layer on barrier layer 4 while in-situ Mg doping is performed with doping concentration of 5x10 19 cm -3 And obtaining the original Mg doped nitride cap layer 5.
Generating a GaN protective layer 9 with the thickness of 60nm above the whole original Mg-doped nitride cap layer 5 by adopting the MOCVD technology; in-situ doping of silicon atoms with a doping concentration of 2 × 10 is carried out while the GaN protective layer 9 is being epitaxially grown 18 An n-doped protective layer 9 is formed.
5.1) adopting a photoetching process to manufacture a photoresist mask, exposing partial surface of the GaN protective layer 9, and adopting reactive ion etching equipment and technology (RIE) to remove the GaN protective layer 9 without the coverage of the photoresist mask and expose the middle nitride cap layer, as shown in e in figure 5.
5.2) then using N at a temperature of 600 DEG C 2 And annealing for 20min in the atmosphere to break chemical bonds between Mg ions and H ions in the gallium nitride cap layer which is not protected by the protective layer, activate the conductivity of Mg to form a P-type gallium nitride cap layer 51, wherein the gallium nitride cap layer protected by the protective layer is still in a high-resistance state.
5.3) finally, the n-doped GaN protection layer 9 is removed using dry etching techniques, as shown by f in fig. 5.
And 6, cleaning.
The specific implementation of this step is the same as step six of example 1.
And manufacturing a photoresist mask by adopting a photoetching process, exposing partial surface of the nitride cap layer, etching the nitride cap layer without being covered by the photoresist mask, the barrier layer 4, the channel layer 3 and partial buffer layer 23 by adopting reactive ion etching equipment and a technology RIE (reactive ion etching), and etching to form a table top with regular edges and steep side walls to form an isolation region between different transistors.
And 8.1) manufacturing a photoresist mask by adopting a photoetching process, and exposing the surface of a part of the nitride cap layer.
And 8.2) etching and removing the nitride cap layer without the coverage of the photoresist mask by reactive ion etching equipment and RIE (reactive ion etching), and cleaning the residual photoresist.
8.3) adopting the photoetching process to manufacture a photoresist mask to expose the areas where the source electrode 6 and the drain electrode 7 are to be manufactured. And growing a plurality of layers of metal Ta/Al/Ni/Au in the area by means of electron beam evaporation, namely Ta with the thickness of 20nm, Al with the thickness of 120nm, Ni with the thickness of 40nm and Au with the thickness of 50nm from bottom to top in sequence to form a source electrode 6 and a drain electrode 7. After the peeling, the source electrode 6 and the drain electrode 7 are formed.
8.5) finally carrying out rapid thermal annealing for 30s in a nitrogen atmosphere at 850 ℃ so that the source electrode 6 and the drain electrode 7 form ohmic contact with the barrier layer 4.
9.1) adopting a photoetching process to manufacture a photoresist mask to expose the area to be manufactured with the gate electrode 8;
9.2) then using electron beam evaporation technology to prepare the gate electrode metal of Ti/Au combination, wherein the thickness of Ti is 50nm, the thickness of Au is 150nm, and forming a gate electrode 8 after stripping, as shown in g in figure 5.
9.3) finally carrying out thermal annealing at the temperature of 460 ℃ for 10min, so that Schottky contact is formed between the gate electrode 8 and the P-type cap layer 51, and the whole device is manufactured.
Example 3: sapphire is selected as a substrate 1, and the thickness is 300 mu m. The thickness of the nucleation layer 21 is 300nm, and the material is gallium nitride. The thickness of the transition layer 22 is 1000nm, the material is gallium nitride, the thickness of the buffer layer 23 is 500nm, and the material is gallium nitride. The thickness of the channel layer 3 is 200nm, and the material is gallium nitride. Barrier layer 4 is made of Al 0.2 Ga 0.25 N, aluminum component 0.2, thickness 20 nm. The isolation layer 31 is made of AlN and has a thickness of 0.5 nm. The original Mg-doped nitride cap layer 5 is 80nm, the material is gallium nitride, the doping is Mg doping, and the doping concentration is 4x10 19 cm -3 (ii) a An n-type doped GaN protective layer 9 doped with Si at a concentration of 1 × 10 19 (ii) a And the two layers at the bottom of the source electrode and the drain electrode are Ti/Al, and the bottom layer of the gate electrode is TiN.
Step a, the sapphire substrate is cleaned, as shown in a in fig. 5.
Removing impurities such as greasy dirt, sweat stain and the like on the surface of the substrate by using organic acetone and the like on the substrate 1, and then blowing the substrate by using nitrogen.
Step B, epitaxially growing a composite buffer layer 2 on the substrate 1, as shown in fig. 5B.
A nucleation layer 21 of 300nm is grown on the substrate 1 by MOCVD at a low temperature of 650 c.
Then raising the temperature to 1100 ℃, growing a transition layer 22 with the thickness of 1000nm by using an MOCVD method, and then growing a buffer layer 23 with the thickness of 500nm on the transition layer.
Step C, fabricating a channel layer 3, an isolation layer 31, a barrier layer 4 and an original Mg-doped nitride cap layer 5, as shown in fig. 5C.
Firstly, a channel layer 3 with the thickness of 200nm is grown on the buffer layer by adopting an MOCVD method and setting the temperature to be 1000 ℃.
Then a 0.5nm spacer layer 31 was epitaxial on the channel layer 3 and finally a 20nm thick barrier layer 4 was epitaxial on the spacer layer 31.
Then, a nitride cap layer is epitaxially grown on the barrier layer 4, and Mg doping is carried out while the gallium nitride cap layer is grown, wherein the doping concentration is 4x10 19 cm -3 And obtaining the original Mg doped nitride cap layer 5.
Step D, growing a GaN protection layer 9, as shown in D of fig. 5.
A GaN protective layer 9 with a thickness of 80nm is formed on the whole nitride cap layer by using the MOCVD technology. The GaN protective layer 9 is epitaxially doped with in-situ Si impurities at a concentration of 1 × 10 19 An n-type doped GaN protection layer 9 is formed.
Step E, the nitride cap layer is activated as shown in FIG. 5 as E, f.
A photoresist mask is made by using a photolithography process to expose a portion of the surface of the GaN protection layer 9, and the GaN protection layer 9 without the photoresist mask is removed by using Reactive Ion Etching (RIE) equipment and technique to expose a middle portion of the nitride cap layer, as shown in fig. 5 e.
Then N at 600 ℃ is used 2 And annealing for 20min in the atmosphere to break chemical bonds between Mg ions and H ions in the gallium nitride cap layer which is not protected by the protective layer, activate the conductivity of Mg impurities and form a P-type gallium nitride cap layer, wherein the gallium nitride cap layer protected by the protective layer is still in a high-resistance state.
Finally, the GaN protection layer is removed using CMP technique, as shown by f in fig. 5.
And F, cleaning.
The specific implementation of this step is the same as step six of example 1
And G, etching the mesa to manufacture isolation, as shown by G in figure 5.
And manufacturing a photoresist mask by adopting a photoetching process, exposing partial surface of the nitride cap layer, etching the nitride cap layer, the barrier layer 4, the channel layer 3 and partial buffer layer 23 which are not covered by the photoresist mask by adopting reactive ion etching equipment and RIE (reactive ion etching), and etching to form a table top with regular edges and steep side walls to form isolation regions among different transistors.
Step H, source electrode 6 and drain electrode 7 are fabricated as shown in fig. 5H.
Manufacturing a photoresist mask by adopting a photoetching process, exposing partial surface of the nitride cap layer, etching and removing the nitride cap layer without being covered by the photoresist mask by adopting reactive ion etching equipment and a RIE (reactive ion etching) technology, and cleaning residual photoresist;
and then, a photoresist mask is manufactured by adopting a photoetching process, and the areas where the source electrode 6 and the drain electrode 7 are to be manufactured are exposed. And growing a plurality of layers of metal Ti/Al/Ni/Au in the area in an electron beam evaporation mode, namely Ti with the thickness of 20nm, Al with the thickness of 120nm, Ni with the thickness of 40nm and Au with the thickness of 50nm from bottom to top in sequence, and stripping to form a source electrode 6 and a drain electrode 7. As shown by h in fig. 5
And finally, performing rapid thermal annealing for 30s in a nitrogen atmosphere at 850 ℃ so that the source electrode 6, the drain electrode 7 and the barrier layer 4 form ohmic contact.
Step I, a gate electrode 8 is fabricated as shown in fig. 5I.
A photoresist mask is made by a photolithography process to expose the region where the gate electrode 8 is to be made.
Then, the gate electrode metal of TiN/Au combination is prepared by using the electron beam evaporation technology, wherein the thickness of TiN is 50nm, the thickness of Au is 150nm, and the gate electrode 8 is formed after stripping, as shown in i in figure 5.
And finally, thermally annealing at 460 ℃ for 10min to form Schottky contact between the gate electrode 8 and the P-type nitride cap layer 51, thereby completing the manufacture of the whole device.
While the foregoing description is illustrative of the present invention and is not intended to limit the invention in any way, it will be apparent to those skilled in the art that, having the benefit of this disclosure and principles, numerous modifications and variations in form and detail are possible without departing from the principles and structures described herein, e.g., substrate 1 may be a diamond substrate other than silicon, silicon carbide, sapphire, buffer layer 23 may be gallium nitride, buffer layer 23 may be aluminum gallium nitride, barrier layer 4 may be aluminum gallium nitride, indium aluminum nitride, indium aluminum gallium nitride, channel layer 4 may be gallium nitride, aluminum gallium nitride, cap layer 5 may be gallium nitride, aluminum gallium nitride, n-doped GaN cap layer 9 may be other high temperature resistant n-type group iii nitride protective materials, and the two lowermost layers of metal of source and drain electrodes 6, 6 may be Ti/Al, and source/drain electrodes 6 may be Ti/Al, and GaN protective materials other than GaN Ta/Al, Mo/Al material can be used, Al, Ta, Ni and TaN material can be used as the lowest layer of the gate electrode 8 besides Ti and TiN, and the thickness of each epitaxial layer can meet the technical range in the specification, but the modification and the change based on the idea of the invention are still within the protection scope of the invention.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210721922.6A CN115000168A (en) | 2022-06-24 | 2022-06-24 | P-type nitride enhanced HEMT device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210721922.6A CN115000168A (en) | 2022-06-24 | 2022-06-24 | P-type nitride enhanced HEMT device and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115000168A true CN115000168A (en) | 2022-09-02 |
Family
ID=83037928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210721922.6A Pending CN115000168A (en) | 2022-06-24 | 2022-06-24 | P-type nitride enhanced HEMT device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115000168A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115440586A (en) * | 2022-09-26 | 2022-12-06 | 山东大学 | Preparation method of InAlN/GaN HEMT based on mixed gas annealing |
| CN115841950A (en) * | 2022-10-14 | 2023-03-24 | 西安电子科技大学 | GaN enhanced PMOS device based on annealing diffusion and preparation method thereof |
| WO2024060083A1 (en) * | 2022-09-21 | 2024-03-28 | 华为技术有限公司 | Semiconductor device and manufacturing method therefor, and electronic device |
| CN119789451A (en) * | 2024-11-20 | 2025-04-08 | 西安电子科技大学广州研究院 | A method for manufacturing a selectively activated p-GaN gate HEMT device |
| CN119789451B (en) * | 2024-11-20 | 2026-02-13 | 西安电子科技大学广州研究院 | A method for fabricating a selectively activated p-GaN gate HEMT device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080087915A1 (en) * | 2006-10-12 | 2008-04-17 | Yasuhiro Uemoto | Nitride semiconductor device and method for fabricating the same |
| CN102709319A (en) * | 2011-02-17 | 2012-10-03 | 富士通株式会社 | Semiconductor device and method of manufacturing the same, and power supply apparatus |
| CN111969046A (en) * | 2020-07-15 | 2020-11-20 | 西安电子科技大学 | High-linearity enhanced gallium nitride high-electron-mobility transistor and preparation method thereof |
| CN112289858A (en) * | 2019-07-22 | 2021-01-29 | 中国科学院苏州纳米技术与纳米仿生研究所 | Group III nitride enhanced HEMT device and preparation method thereof |
-
2022
- 2022-06-24 CN CN202210721922.6A patent/CN115000168A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080087915A1 (en) * | 2006-10-12 | 2008-04-17 | Yasuhiro Uemoto | Nitride semiconductor device and method for fabricating the same |
| CN102709319A (en) * | 2011-02-17 | 2012-10-03 | 富士通株式会社 | Semiconductor device and method of manufacturing the same, and power supply apparatus |
| CN112289858A (en) * | 2019-07-22 | 2021-01-29 | 中国科学院苏州纳米技术与纳米仿生研究所 | Group III nitride enhanced HEMT device and preparation method thereof |
| CN111969046A (en) * | 2020-07-15 | 2020-11-20 | 西安电子科技大学 | High-linearity enhanced gallium nitride high-electron-mobility transistor and preparation method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024060083A1 (en) * | 2022-09-21 | 2024-03-28 | 华为技术有限公司 | Semiconductor device and manufacturing method therefor, and electronic device |
| CN115440586A (en) * | 2022-09-26 | 2022-12-06 | 山东大学 | Preparation method of InAlN/GaN HEMT based on mixed gas annealing |
| CN115841950A (en) * | 2022-10-14 | 2023-03-24 | 西安电子科技大学 | GaN enhanced PMOS device based on annealing diffusion and preparation method thereof |
| CN119789451A (en) * | 2024-11-20 | 2025-04-08 | 西安电子科技大学广州研究院 | A method for manufacturing a selectively activated p-GaN gate HEMT device |
| CN119789451B (en) * | 2024-11-20 | 2026-02-13 | 西安电子科技大学广州研究院 | A method for fabricating a selectively activated p-GaN gate HEMT device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107946358B (en) | An AlGaN/GaN heterojunction HEMT device compatible with Si-CMOS process and a manufacturing method thereof | |
| US9349819B2 (en) | Heterojunction semiconductor device and manufacturing method | |
| CN114899227A (en) | Enhanced gallium nitride-based transistor and preparation method thereof | |
| CN220065702U (en) | An enhanced HEMT device | |
| JP2016139781A (en) | Enhancement high electron mobility transistor and method of manufacturing the same | |
| CN109819678A (en) | The gate dielectric material of doping | |
| CN104091835A (en) | Gallium nitride heterojunction schottky barrier diode and manufacturing method thereof | |
| CN113380623A (en) | Method for realizing enhanced HEMT (high Electron mobility transistor) through p-type passivation | |
| CN109873034B (en) | Normally-off HEMT power device for depositing polycrystalline AlN and preparation method thereof | |
| CN115000168A (en) | P-type nitride enhanced HEMT device and preparation method thereof | |
| CN109244130A (en) | Self aligning grid structure GaN MIS-HEMT device and preparation method thereof based on p-GaN and SiN layer | |
| CN113745333B (en) | A gallium oxide-based MIS-HEMT device and a method for preparing the same | |
| CN112018177B (en) | Full-vertical Si-based GaN UMOSFET power device and preparation method thereof | |
| CN114843342A (en) | Gallium nitride-based transistor structure with drain electrode buried layer and preparation method | |
| CN118136663A (en) | Nitrogen polarity enhanced gallium nitride high electron mobility transistor structure and preparation method thereof | |
| CN113628962A (en) | III-nitride enhanced HEMT device and manufacturing method thereof | |
| CN114823850B (en) | P-type mixed ohmic contact gallium nitride transistor | |
| CN207925477U (en) | A AlGaN/GaN Heterojunction HEMT Device Compatible with Si-CMOS Process | |
| CN118888582B (en) | Current aperture vertical electron transistor and preparation method thereof | |
| CN114334650A (en) | Novel structure in p-GaN HEMT | |
| JP5569321B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN119730294A (en) | Gallium nitride radio frequency device structure with high long-term reliability and preparation method thereof | |
| CN116387344A (en) | Single particle burnout resistant gallium nitride reference vertical trench MOSFET device structure and manufacturing method thereof | |
| CN118431275A (en) | A HEMT power device structure and preparation method thereof | |
| CN118435360A (en) | Junction barrier Schottky diode and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |