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CN114995582A - Circuit and method for generating dead time in driving circuit - Google Patents

Circuit and method for generating dead time in driving circuit Download PDF

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Publication number
CN114995582A
CN114995582A CN202210609033.0A CN202210609033A CN114995582A CN 114995582 A CN114995582 A CN 114995582A CN 202210609033 A CN202210609033 A CN 202210609033A CN 114995582 A CN114995582 A CN 114995582A
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switching tube
circuit
gate
tube
drain
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CN202210609033.0A
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CN114995582B (en
Inventor
夏雪
孙权
董磊
袁婷
王勇
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XI'AN AEROSPACE MINXIN TECHNOLOGY CO LTD
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XI'AN AEROSPACE MINXIN TECHNOLOGY CO LTD
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Electronic Switches (AREA)
  • Inverter Devices (AREA)

Abstract

The invention provides a circuit and a method for generating dead TIME in a driving circuit, wherein a resistor is connected with a TIME end and a resistor is connected with GND or VDD to generate a charging or discharging current and a signal S for controlling the charging or discharging current, then two comparators are used for generating the dead TIME at two sides by charging or discharging the voltage at one end of each comparator, and finally the comparator outputs a signal with the dead TIME in the same phase or the opposite phase through an output driving level generating circuit. Through the size of TIME end connecting resistance, the size of dead TIME can be flexibly adjusted, the efficiency can be improved, and the phenomenon that the power tube is conducted when the dead TIME is too small or the dead TIME is too large to cause large loss is avoided.

Description

Circuit and method for generating dead time in driving circuit
Technical Field
The invention belongs to the technical field of power supplies, and particularly relates to a circuit and a method for generating dead time in a driving circuit.
Background
The driving circuit plays a very critical role in a circuit system, receives a control part and a main circuit part in the circuit, and drives the main circuit by converting a signal of the control part into a driving signal. The drive circuit with dead time requires dead time between at least two drive signals. In circuits such as a half-bridge circuit, a full-bridge circuit and an active clamping forward circuit, a driving circuit with dead time can be applied, and because the driving circuit has dead time, not only can the power tube be prevented from being conducted at the same time, but also the driving circuit can be applied to some resonant circuits.
The dead time generating circuit in the prior art can only generate fixed dead time, the dead time cannot be flexibly adjusted, if the dead time is too small, the power tubes can be simultaneously conducted, if the dead time is too large, loss can be increased, and efficiency is reduced.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a circuit and a method for generating dead time in a driving circuit, which realize that a clock signal with the dead time is input in the same phase or in opposite phase.
The invention is realized by the following technical scheme:
a circuit for generating dead time in a driving circuit, comprising a dead time generating circuit for generating a complete dead time rectangular wave;
the output end of the current generating circuit is connected with the input end of the dead time generating circuit and generates charge and discharge current for the dead time generating circuit;
the input end of the comparator circuit is connected with the output end of the dead time generation circuit and is used for respectively generating two-side dead time;
and the input end of the output driving level generating circuit is connected with the output end of the comparator circuit and is used for selectively generating the in-phase or anti-phase output driving level.
Further, the dead time generating circuit includes a ramp generating circuit and a comparator circuit;
the slope generating circuit comprises a falling edge delay circuit and a rising edge delay circuit, the falling edge delay circuit and the rising edge delay circuit are controlled by an S end, the falling edge delay circuit is provided with a rectangular wave input port VD1, and the rising edge delay circuit is provided with a rectangular wave input port VD 2.
Further, the falling edge delay circuit comprises a switch tube M1 and a switch tube M3, the drain electrode of the switch tube M1 and the drain electrode of the switch tube M3 are connected and are both connected with the comparator circuit, the grid electrode of the switch tube M1 is connected with the S end, and the source electrode is connected with the rising edge delay circuit; the source electrode of the switching tube M3 is connected with the comparator circuit, and the grid electrode of the switching tube M3 is connected with the rectangular wave input port VD 1;
the rising edge delay circuit comprises a switch tube M2 and a switch tube M4, wherein the source electrode of the switch tube M4 is connected with the source electrode of the switch tube M1, the grid electrode of the switch tube M4 is connected with the rectangular wave input port VD2, and the drain electrode of the switch tube M2 is connected with the drain electrode of the switch tube M4; the grid electrode of the switching tube M2 is connected with the end S, and the source electrode is respectively connected with the drain electrodes of the switching tube M1 and the switching tube M3 and is connected to the comparator circuit;
a power supply VDD is connected between the source electrode of the switch tube M4 and the source electrode of the switch tube M1, and a ground wire is connected between the source electrode of the switch tube M3 and the comparator circuit.
Further, the comparator circuit comprises a capacitor C and a comparator COMP 1;
two ends of the capacitor C are respectively connected with a ground wire and a source electrode of a switch tube M2, a drain electrode of a switch tube M1 and a drain electrode of a switch tube M3, an anode of the comparator COMP1 is connected with the source electrode of the switch tube M2, the drain electrode of the switch tube M1 and the drain electrode of the switch tube M3, a cathode of the comparator COMP1 is connected with a VREF end, and an output end of the comparator COMP outputs a signal dead time signal VO.
Further, the current generation circuit comprises
The first current mirror circuit comprises a switching tube M17 and a switching tube M18, the drains of the switching tube M17 and the switching tube M18 are interconnected, the positive electrode of an output end COMP2 of a comparator COMP2 is connected with a VREF end, and the negative electrode of the output end COMP2 of the comparator COMP2 is connected with a TIME end; the source electrode of the switching tube M17 is connected with the grid electrode of a switching tube M19, the source electrode of the switching tube M18 is connected with the grid electrode of a switching tube M20, and the source electrodes of the switching tube M19 and the switching tube M20 are interconnected;
the second current mirror circuit comprises a switching tube M27, a switching tube M28 and a switching tube M33; the drain electrode of the switching tube M28 is connected with the source electrode of the switching tube M8;
a third current mirror circuit, which comprises a switching tube M29, a switching tube M30, a switching tube M34, a switching tube M35, a switching tube M36 and a switching tube M37, wherein the drain of the switching tube M29 is connected with the drain of the switching tube M20;
the drain of the switching tube M36 is connected with the source of a switching tube M25, the drain of the switching tube M37 is connected with the source of a switching tube M26, and the gates of the switching tube M25 and the switching tube M26 are interconnected; the drain of the switching tube M25 is connected with the drain of the switching tube M23, the drain of the switching tube M26 is connected with the drain of the switching tube M24, and the gates of the switching tube M23 and the switching tube M24 are interconnected;
the fourth current mirror circuit comprises a switching tube M15 and a switching tube M16, and the gates of the switching tube M15 and the switching tube M16 and the drain of the switching tube M15 are both connected with the drain of the switching tube M30;
a fifth current mirror circuit, which includes a switching tube M31 and a switching tube M32, the drain of the switching tube M31 is connected with the source of the switching tube M22, the drain of the switching tube M22 is connected with the drain of the switching tube M21, the source of the switching tube M20 and the source of the switching tube M19, the gates of the switching tube M22 and the switching tube M21 are interconnected, and the source of the switching tube M21 is connected with the drain of the switching tube M16;
a sixth current mirror circuit, which includes a switching tube M8, a switching tube M9, a switching tube M10, a switching tube M11, a switching tube M13 and a switching tube M14, wherein the drain and the gate of the switching tube M8 are connected to the drain of the switching tube M19; the drain electrode of the switching tube M14 is connected with the source electrode of the switching tube M24;
a seventh current mirror circuit, which includes a switching tube M5, a switching tube M6, a switching tube M7 and a switching tube M12, wherein the drain of the switching tube M5 is interconnected with the gate, and the drain of the switching tube M12 is connected with the drains of the switching tube M34 and the switching tube M35;
the interconnected circuits of the drains of the switching tube M19 and the switching tube M20 are connected with the interconnected circuits of the drains of the switching tube M21 and the switching tube M22; the grid interconnection circuit of the switching tube M21 and the switching tube M22 is connected with the grid interconnection circuit of the switching tube M23, the switching tube M24, the switching tube M25 and the switching tube M26.
Furthermore, the source electrodes of the switching tubes in the second current mirror circuit, the third current mirror circuit, the fourth current mirror circuit and the fifth current mirror circuit are all grounded; and the sources of the sixth current mirror circuit and the sixth current mirror circuit are both connected with a power supply VDD.
Further, the comparator circuit includes
The eighth current mirror circuit comprises a switching tube M38, a switching tube M39, a switching tube M55 and a switching tube M56, wherein the sources of the switching tube M38, the switching tube M39, the switching tube M55 and the switching tube M56 are all connected with a power supply VDD, and the power supply VDD is also connected with the sources of the switching tube M41, the switching tube M48, the switching tube M50, the switching tube M52A, the switching tube M53, the switching tube M62, the switching tube M64 and the switching tube M67;
the grid of the switch tube M41 is connected with the output end of a NAND gate E1, one input end of the NAND gate E1 is connected with the S end, the other input end of the NAND gate E is connected with the output end of a NOT gate F1, the output end of the NOT gate F1 is connected with the output end of a NOT gate F2 and the input end of an AND gate W1, the other input end of the AND gate W1 is connected with the output end of the NOT gate F3, and the output end of the AND gate W1 is connected with the grid of a switch tube M42;
the drains of the switching tube M41 and the switching tube M42 are interconnected and provided with an I2 end, the drains of the switching tube M41 and the switching tube M42 are interconnected and connected with the grid of the switching tube M43, the drain of the switching tube M39 is respectively connected with the sources of the switching tube M43 and the switching tube M44, and the grid of the switching tube M44 is connected with a VREF end;
a ninth current mirror circuit, which includes a switching tube M45 and a switching tube M46, the drain of the switching tube M43 is connected to the gate of the switching tube M46 and the drain and gate of the switching tube M45, respectively, the drains of the switching tube M44 and the switching tube M46 are interconnected and connected to the gate of the switching tube M47;
the drains of the switching tube M48 and the switching tube M497 are interconnected and connected with a drain interconnection circuit of the switching tube M40 and the switching tube M47; the drains of the switching tube M48 and the switching tube M49 are interconnected and connected with a switching tube M50 and a switching tube M51 grid interconnection circuit, the drains of the switching tube M50 and the switching tube M51 are interconnected and connected with a switching tube M52A and a switching tube M52B grid interconnection circuit, and the drains of the switching tube M52A and the switching tube M52B are interconnected and provided with a Y1 end;
the gate of the switching tube M53 is connected with the output end of a nand gate E2, one input end of the nand gate E2 is connected with the S end, the other input end is connected with the output end of a not gate F4, the input end of the not gate F4 is connected with the output end of a not gate F5, the in-out section of the not gate F5 is connected with the input end of the not gate F6, and the input end of the not gate F6 is connected with a clock signal VD; the output end of the not gate F6 is also connected with one input end of an and gate W2, the other input end of the and gate W2 is connected with the output end of a not gate F7, the input end of the not gate F7 is connected with an S end, the output end of the and gate W2 is connected with the grid of a switch tube M54, and the drains of the switch tube M53 and the switch tube M54 are interconnected and are provided with an I1 end; the drains of the switch tube M53 and the switch tube M54 are interconnected and connected with the grid of the switch tube M57; the drain of the switching tube M55 is respectively connected with the sources of the switching tube M57 and the switching tube M58, the gate of the switching tube M58 is connected with the VREF end, and the drains of the switching tube M57 and the switching tube M58 are connected with the ninth current mirror circuit;
the drain of the switching tube M58 is also connected with the grid of a switching tube M61, the drains of the switching tube M56 and the switching tube M61 are interconnected and are connected with a switching tube M62 and a switching tube M63 grid interconnection circuit, the drains of the switching tube M62 and the switching tube M63 are interconnected and are connected with a switching tube M64 and a switching tube M65 grid interconnection circuit, the drains of the switching tube M64 and the switching tube M65 are interconnected and are connected with a switching tube M67 and a switching tube M68 grid interconnection circuit, and the drains of the switching tube M67 and the switching tube M68 are interconnected and are provided with a Y2 end;
the source electrodes of the switching tube M42, the switching tube M45, the switching tube M46, the switching tube M47, the switching tube M49, the switching tube M51, the switching tube M52B, the switching tube M54, the switching tube M61, the switching tube M63, the switching tube M65 and the switching tube M68 are all grounded.
Further, the drains of the switching tube M41 and the switching tube M42 are interconnected, and a circuit connected with the gate of the switching tube M43 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is grounded;
the drains of the switching tube M53 and the switching tube M54 are interconnected, and a circuit connected with the gate of the switching tube M57 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is grounded.
Further, the output drive level generating circuit includes a selector a1 and a selector a 2;
the input end of the selector A1 is respectively connected with the output end of an NOT gate F8 and the output end of an NOT gate F9, the input end of the NOT gate F8 is connected with an end Y2, the input end of the NOT gate F9 is connected with an end Y1, and the output end of the selector A1 is connected with the input end of an AND gate W3;
the input end of the selector A2 is respectively connected with the output end of a not gate F8 and the output end of a not gate F10, the input end of the not gate F10 is connected with the output end of a not gate F8, and the output end of the selector A2 is connected with the input end of an AND gate W4;
the input ends of the and gate W3 and the and gate W4 are interconnected, the output end of the and gate W3 outputs a signal YA, and the output end of the and gate W4 outputs a signal YB.
A method for generating dead time in a driver circuit, comprising the steps of:
the resistor is connected with the resistor through the TIME end, the resistor is connected with GND or VDD, the charging and discharging current for the dead TIME generating circuit is generated, and the S end voltage is used for controlling charging or discharging; when the resistor is connected with GND and the S end voltage is low level, charging the voltage of the input end of the comparator; when the resistor is connected with VDD and the voltage of the S end is high level, charging the voltage of the input end of the comparator;
a comparator circuit generating a double-sided dead time; when the resistor is connected with GND, the left comparator generates a left dead time, and the right comparator generates a right dead time; when the resistor is connected with VDD, the left comparator generates right dead time, and the right comparator generates left dead time;
an output drive level generation circuit for selectively generating an in-phase or an inverted output drive level; when the resistor is connected with GND, the S end is at low level, and the generated output driving levels YA and YB are in the same phase; when the resistor is connected with VDD, the S end is high level, the generated output driving level YA and YB are in reverse phase, and dead time is generated in the driving circuit.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention provides a circuit and a method for generating dead TIME in a driving circuit, wherein a resistor is connected with a TIME end and a resistor is connected with GND or VDD to generate a charging or discharging current and a signal S for controlling the charging or discharging current, then two comparators are used for generating the dead TIME at two sides by charging or discharging the voltage at one end of each comparator, and finally the comparator outputs a signal with the dead TIME in the same phase or the opposite phase through an output driving level generating circuit. Through the size of TIME end connecting resistance, can adjust the size of dead TIME in a flexible way, efficiency can obtain improving, switches on when avoiding the dead TIME too little to lead to the power tube, perhaps dead TIME too big causes great loss.
Drawings
FIG. 1 is a circuit diagram for generating dead time in a driver circuit according to the present invention;
FIG. 2 is a dead time generation circuit diagram of the present invention;
FIG. 3 is a circuit diagram of the current generation circuit of the present invention;
FIG. 4 is a circuit diagram of a comparator according to the present invention;
FIG. 5 is a circuit diagram of an output driving level generating circuit according to the present invention;
FIG. 6 is a waveform diagram of the resistor at each end when the TIME is connected to the ground line GND according to the present invention;
FIG. 7 is a waveform diagram of the present invention with TIME connected to resistor and resistor connected to power VDD.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The present invention provides a circuit for generating dead time in a driving circuit, as shown in fig. 1, comprising a dead time generating circuit for generating a complete dead time rectangular wave;
the output end of the current generating circuit is connected with the input end of the dead time generating circuit and is used for generating and charging and discharging current to the dead time generating circuit;
the input end of the comparator circuit is connected with the output end of the dead time generation circuit and is used for respectively generating the dead time at two sides;
and the input end of the output driving level generating circuit is connected with the output end of the comparator circuit and is used for selectively generating the in-phase or anti-phase output driving level.
Specifically, as shown in fig. 1, two comparator circuits may be provided, and are respectively used for the falling edge delay circuit and the rising edge delay circuit, and the comparator circuit that determines to be turned on is controlled by the connected S terminal.
Preferably, as shown in fig. 2, the dead time generation circuit includes a ramp generation circuit and a comparator circuit;
the slope generating circuit comprises a falling edge delay circuit and a rising edge delay circuit, the falling edge delay circuit and the rising edge delay circuit are controlled by an S end, the falling edge delay circuit is provided with a rectangular wave input port VD1, and the rising edge delay circuit is provided with a rectangular wave input port VD 2.
Specifically, the falling edge delay circuit comprises a switching tube M1 and a switching tube M3, the drain of the switching tube M1 and the drain of the switching tube M3 are connected and are both connected with a comparator circuit, the gate of the switching tube M1 is connected with the S terminal, and the source is connected with the rising edge delay circuit; the source electrode of the switching tube M3 is connected with the comparator circuit, and the grid electrode of the switching tube M3 is connected with the rectangular wave input port VD 1;
the rising edge delay circuit comprises a switching tube M2 and a switching tube M4, wherein the source electrode of the switching tube M4 is connected with the source electrode of the switching tube M1, the grid electrode of the switching tube M3526 is connected with the rectangular wave input port VD2, and the drain electrode of the switching tube M2 is connected with the drain electrode of the switching tube M2; the grid electrode of the switching tube M2 is connected with the end S, and the source electrode is respectively connected with the drain electrodes of the switching tube M1 and the switching tube M3 and is connected to the comparator circuit;
a power supply VDD is connected between the source electrode of the switch tube M4 and the source electrode of the switch tube M1, and a ground wire is connected between the source electrode of the switch tube M3 and the comparator circuit.
Further, the comparator circuit comprises a capacitor C and a comparator COMP 1;
two ends of the capacitor C are respectively connected with a ground wire, a source electrode of the switch tube M2, a drain electrode of the switch tube M1 and a drain electrode of the switch tube M3, an anode of the comparator COMP1 is connected with a source electrode of the switch tube M2, a drain electrode of the switch tube M1 and a drain electrode of the switch tube M3, a cathode of the comparator COMP1 is connected with a VREF end, and an output end of the comparator COMP1 outputs a dead time signal VO.
Specifically, the dead time generation circuit comprises a falling edge delay circuit controlled by VD1 and a rising edge delay circuit controlled by VD 2. The two functions can not work simultaneously and are controlled by the terminal S. In the figure, the left half parts where M1, M2, M3 and M4 are located are ramp generating circuits, the right half parts are comparator structures, and ramp signals are changed into rectangular waves through the comparators. When the S end is at a low level, M1 is conducted, M2 is turned off, and the parts of the ramp generating circuit where M1 and M3 are located work; when the S terminal is at high level, M1 turns off, M2 turns on, and the part of the ramp generation circuit where M2 and M4 are located operates. The dead time generating circuit can only generate the dead time of one side of the rectangular wave, so that two identical dead time generating module circuits are needed for generating the complete dead time rectangular wave. The port of the input rectangular wave is VD1, which becomes (VD 1)', after passing through the inverter, the two signals generate a complete driving signal with dead time after passing through the dead time generating circuit.
VD1 and VD2 are rectangular wave signals needing time delay, and the circuit controls the time delay by controlling charging and discharging currents. Taking the left half part of the ramp generating circuit in the dead time generating circuit as an example, the width and length of M3 are large, so when VD1 is a rising edge, the drain voltage of M3 drops to 0 almost instantaneously, but when VD1 is a falling edge, the drain voltage of M3 generates a ramp voltage, and the ramp voltage is compared with a fixed voltage VREF to generate a rectangular wave one-side delay time.
Preferably, as shown in fig. 3, the current generation circuit includes
The first current mirror circuit comprises a switching tube M17 and a switching tube M18, the drains of the switching tube M17 and the switching tube M18 are interconnected, the anode of an output end comparator COMP2 of a comparator COMP2 is connected with a VREF end, and the cathode of the output end comparator COMP2 is connected with a TIME end; the source electrode of the switching tube M17 is connected with the grid electrode of a switching tube M19, the source electrode of the switching tube M18 is connected with the grid electrode of a switching tube M20, and the source electrodes of the switching tube M19 and the switching tube M20 are interconnected;
the second current mirror circuit comprises a switching tube M27, a switching tube M28 and a switching tube M33; the drain electrode of the switching tube M28 is connected with the source electrode of the switching tube M8;
a third current mirror circuit, which comprises a switching tube M29, a switching tube M30, a switching tube M34, a switching tube M35, a switching tube M36 and a switching tube M37, wherein the drain of the switching tube M29 is connected with the drain of the switching tube M20;
the drain of the switching tube M36 is connected with the source of a switching tube M25, the drain of the switching tube M37 is connected with the source of a switching tube M26, and the gates of the switching tube M25 and the switching tube M26 are interconnected; the drain of the switching tube M25 is connected with the drain of the switching tube M23, the drain of the switching tube M26 is connected with the drain of the switching tube M24, and the gates of the switching tube M23 and the switching tube M24 are interconnected;
the fourth current mirror circuit comprises a switching tube M15 and a switching tube M16, and the gates of the switching tube M15 and the switching tube M16 and the drain of the switching tube M15 are both connected with the drain of the switching tube M30;
a fifth current mirror circuit, which includes a switching tube M31 and a switching tube M32, the drain of the switching tube M31 is connected with the source of the switching tube M22, the drain of the switching tube M22 is connected with the drain of the switching tube M21, the source of the switching tube M20 and the source of the switching tube M19, the gates of the switching tube M22 and the switching tube M21 are interconnected, and the source of the switching tube M21 is connected with the drain of the switching tube M16;
a sixth current mirror circuit, which includes a switching tube M8, a switching tube M9, a switching tube M10, a switching tube M11, a switching tube M13 and a switching tube M14, wherein the drain and the gate of the switching tube M8 are connected to the drain of the switching tube M19; the drain electrode of the switching tube M14 is connected with the source electrode of the switching tube M24;
a seventh current mirror circuit, which includes a switching tube M5, a switching tube M6, a switching tube M7 and a switching tube M12, wherein the drain of the switching tube M5 is interconnected with the gate, and the drain of the switching tube M12 is connected with the drains of the switching tube M34 and the switching tube M35;
the interconnected circuits of the drains of the switching tube M19 and the switching tube M20 are connected with the interconnected circuits of the drains of the switching tube M21 and the switching tube M22; the grid interconnection circuit of the switching tube M21 and the switching tube M22 is connected with the grid interconnection circuit of the switching tube M23, the switching tube M24, the switching tube M2/5 and the switching tube M26.
Specifically, the source electrodes of the switching tubes in the second current mirror circuit, the third current mirror circuit, the fourth current mirror circuit and the fifth current mirror circuit are all grounded; and the sources of the sixth current mirror circuit and the sixth current mirror circuit are both connected with a power supply VDD.
Specifically, when the TIME terminal of the current generation circuit is connected with the resistor R, and the other terminal of the resistor is connected with the GND terminal, at this TIME, M20 is turned off, the current mirror using the M29 current as a reference does not generate current, and M21 is turned off. M19 is turned on, the magnitude of the generated current is VREF/R, corresponding current is generated through the current mirror structure, the output S end of the NAND gate is at low level, M23 and M24 are turned on, M25 and M26 are turned off, and currents flowing out of M23 and M24 are I1 and I2 respectively.
When the resistor R is connected to the TIME terminal and the other end of the resistor is connected to the VDD terminal, M19 is turned off, no current is generated by a current mirror using the M8 current as a reference, and M22 is turned off. M20 is conducted, the magnitude of the generated current is VREF/R, corresponding current is generated through the current mirror structure, the output S end of the NAND gate is at high level, M23 and M24 are turned off, M25 and M26 are conducted, and the current flowing to M25 and M26 are I1 and I2 respectively.
Preferably, as shown in fig. 4, the comparator circuit comprises
The eighth current mirror circuit comprises a switching tube M38, a switching tube M39, a switching tube M55 and a switching tube M56, sources of the switching tube M38, the switching tube M39, the switching tube M55 and the switching tube M56 are all connected with a power supply VDD, and the power supply VDD is further connected with sources of the switching tube M41, the switching tube M48, the switching tube M50, the switching tube M52A, the switching tube M53, the switching tube M62, the switching tube M64 and the switching tube M67;
the grid of the switch tube M41 is connected with the output end of a NAND gate E1, one input end of the NAND gate E1 is connected with the S end, the other input end of the NAND gate E is connected with the output end of a NOT gate F1, the output end of the NOT gate F1 is connected with the output end of a NOT gate F2 and the input end of an AND gate W1, the other input end of the AND gate W1 is connected with the output end of the NOT gate F3, and the output end of the AND gate W1 is connected with the grid of a switch tube M42;
the drains of the switching tube M41 and the switching tube M42 are interconnected and provided with an I2 end, the drains of the switching tube M41 and the switching tube M42 are interconnected and connected with the grid of the switching tube M43, the drain of the switching tube M39 is respectively connected with the sources of the switching tube M43 and the switching tube M44, and the grid of the switching tube M44 is connected with a VREF end;
a ninth current mirror circuit, which includes a switching tube M45 and a switching tube M46, the drain of the switching tube M43 is connected to the gate of the switching tube M46 and the drain and gate of the switching tube M45, respectively, the drains of the switching tube M44 and the switching tube M46 are interconnected and connected to the gate of the switching tube M47;
the drains of the switching tube M48 and the switching tube M497 are interconnected and connected with a drain interconnection circuit of the switching tube M40 and the switching tube M47; the drains of the switching tube M48 and the switching tube M49 are interconnected and are connected with a switching tube M50 and a switching tube M51 grid interconnection circuit, the drains of the switching tube M50 and the switching tube M51 are interconnected and are connected with a switching tube M52A and a switching tube M52B grid interconnection circuit, and the drains of the switching tube M52A and the switching tube M52B are interconnected and are provided with a Y1 end;
the gate of the switching tube M53 is connected with the output end of a nand gate E2, one input end of the nand gate E2 is connected with the S end, the other input end is connected with the output end of a not gate F4, the input end of the not gate F4 is connected with the output end of a not gate F5, the in-out section of the not gate F5 is connected with the input end of the not gate F6, and the input end of the not gate F6 is connected with a clock signal VD; the output end of the not gate F6 is also connected with one input end of an and gate W2, the other input end of the and gate W2 is connected with the output end of a not gate F7, the input end of the not gate F7 is connected with an S end, the output end of the and gate W2 is connected with the grid of a switch tube M54, and the drains of the switch tube M53 and the switch tube M54 are interconnected and are provided with an I1 end; the drains of the switch tube M53 and the switch tube M54 are interconnected and connected with the grid of the switch tube M57; the drain of the switching tube M55 is respectively connected with the sources of the switching tube M57 and the switching tube M58, the gate of the switching tube M58 is connected with the VREF end, and the drains of the switching tube M57 and the switching tube M58 are connected with the ninth current mirror circuit;
the drain of the switching tube M58 is also connected with the grid of a switching tube M61, the drains of the switching tube M56 and the switching tube M61 are interconnected and are connected with a switching tube M62 and a switching tube M63 grid interconnection circuit, the drains of the switching tube M62 and the switching tube M63 are interconnected and are connected with a switching tube M64 and a switching tube M65 grid interconnection circuit, the drains of the switching tube M64 and the switching tube M65 are interconnected and are connected with a switching tube M67 and a switching tube M68 grid interconnection circuit, and the drains of the switching tube M67 and the switching tube M68 are interconnected and are provided with a Y2 end;
the source electrodes of the switching tube M42, the switching tube M45, the switching tube M46, the switching tube M47, the switching tube M49, the switching tube M51, the switching tube M52B, the switching tube M54, the switching tube M61, the switching tube M63, the switching tube M65 and the switching tube M68 are all grounded.
Specifically, the drains of the switching tube M41 and the switching tube M42 are interconnected, and a circuit connected with the gate of the switching tube M43 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is grounded;
the drains of the switching tube M53 and the switching tube M54 are interconnected, and a circuit connected with the gate of the switching tube M57 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is grounded.
Specifically, the comparator circuit analyzes the left comparator. When the S terminal is at a low level, the gate voltage of M41 is at a high level, M41 is turned off, and M42 is turned on and off according to the change of the rectangular wave signal. When M42 is switched on, the grid voltage at the end M43 is directly changed into low level and almost has no time delay, when M42 is switched off, the grid voltage at the end M43 is charged and compared with reference VREF of a comparator to generate an output delay signal Y1, the Y1 signal is in the same phase as the VD signal, but the rising edge of the Y1 signal has time delay relative to the rising edge of the VD signal; when the S end is at a high level, M41 can carry out on-off operation along with the change of a rectangular wave signal, M42 is turned off, when M41 is turned on, the grid voltage of the M43 end is at a high level VDD, when M41 is turned off, the grid voltage of the M43 end carries out discharge operation, the discharge operation is compared with the reference VREF of a comparator, an output delay signal Y1 is generated, the Y1 signal is in the same phase with the VD signal, but the falling edge of the Y1 signal has delay relative to the falling edge of the VD signal.
The right comparator was analyzed. When the S terminal is at a low level, the gate voltage of M53 is at a high level, M53 is turned off, and M54 is turned on and off according to the change of the rectangular wave signal. When M54 is switched on, the grid voltage at the end M54 is directly changed into low level and almost has no time delay, when M53 is switched off, the grid voltage at the end M55 is charged and compared with reference VREF of a comparator to generate an output delay signal Y2, the Y2 signal is opposite to the VD signal, but the rising edge of the Y2 signal has time delay relative to the falling edge of the VD signal; when the S end is at a high level, M53 can carry out on-off operation along with the change of a rectangular wave signal, M54 is turned off, when M53 is turned on, the grid voltage of the M55 end is at a high level VDD, when M53 is turned off, the grid voltage of the M55 end carries out discharge operation, the discharge operation is compared with the reference VREF of a comparator, an output delay signal Y2 is generated, the Y2 signal and the VD signal are in opposite phases, but the falling edge of the Y2 signal has delay relative to the rising edge of the VD signal. It should be noted that when S is low, the gate voltages of M42 and M54 are in reverse correlation, and when S is high, the gate voltages of M41 and M53 are in reverse correlation.
Preferably, as shown in fig. 5, the output drive level generating circuit includes a selector a1 and a selector a 2;
the input end of the selector A1 is respectively connected with the output end of an NOT gate F8 and the output end of an NOT gate F9, the input end of the NOT gate F8 is connected with an end Y2, the input end of the NOT gate F9 is connected with an end Y1, and the output end of the selector A1 is connected with the input end of an AND gate W3;
the input end of the selector A2 is respectively connected with the output end of an NOT gate F8 and the output end of an NOT gate F10, the input end of the NOT gate F10 is connected with the output end of an NOT gate F8, and the output end of the selector A2 is connected with the input end of an AND gate W4;
the input ends of the and gate W3 and the and gate W4 are interconnected, the output end of the and gate W3 outputs a signal YA, and the output end of the and gate W4 outputs a signal YB.
Specifically, when TIME is connected with a resistor R, and the other end of the resistor is connected with a GND terminal, an S terminal is at a low level, the selector selects a signal output from the a path, an obtained signal YA is an inverted signal of Y2, and a signal YB is the same as a signal Y1; when TIME is connected with a resistor R, the other end of the resistor is connected with a VDD end, an S end is in high level, a selector selects a B path signal to output, the obtained signal YA is an inverted signal of Y1, and the signal YB is an inverted signal of Y2.
Specifically, as shown in fig. 6, when the TIME is connected to the resistor R, and the other end of the resistor is connected to the GND terminal, the S terminal is at low level, M23 and M24 are turned on, the generated Y1 signal and VD are in the same direction, the rising edge of the Y1 signal is delayed with respect to the rising edge of the VD signal, the Y2 signal and VD signal are in opposite phases, the rising edge of the Y2 signal is delayed with respect to the falling edge of the VD signal, YA and Y2 are in opposite phases, and YB and Y1 are in the same phase. When TIME is connected with a resistor R, the other end of the resistor is connected with a VDD end, the S end is at a high level, M25 and M26 are conducted, a generated Y1 signal and VD are in the same direction, the falling edge of the Y1 signal has TIME delay relative to the falling edge of the VD signal, the Y2 signal and the VD signal are in opposite phases, the falling edge of the Y2 signal has TIME delay relative to the rising edge of the VD signal, YA and Y1 are in opposite phases, and YB and Y2 are in opposite phases.
The invention provides a method for generating dead time in a driving circuit, which comprises the following steps:
the resistor is connected with the resistor through the TIME end, the resistor is connected with GND or VDD, the charging and discharging current for the dead TIME generating circuit is generated, and the S end voltage is used for controlling charging or discharging; when the resistor is connected with GND and the S end voltage is low level, charging the voltage of the input end of the comparator; when the resistor is connected with VDD and the voltage of the S end is high level, charging the voltage of the input end of the comparator;
a comparator circuit generating a double-sided dead time; when the resistor is connected with GND, the left comparator generates a left dead time, and the right comparator generates a right dead time; when the resistor is connected with VDD, the left comparator generates right dead time, and the right comparator generates left dead time;
an output drive level generation circuit for selectively generating an in-phase or an inverted output drive level; when the resistor is connected with GND, the S end is at low level, and the generated output driving levels YA and YB are in the same phase; when the resistor is connected with VDD, the S end is high level, the generated output driving level YA and YB are in reverse phase, and dead time is generated in the driving circuit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A circuit for generating dead time in a driving circuit, comprising a dead time generating circuit for generating a complete dead time rectangular wave;
the output end of the current generating circuit is connected with the input end of the dead time generating circuit and generates charge and discharge current for the dead time generating circuit;
the input end of the comparator circuit is connected with the output end of the dead time generation circuit and is used for respectively generating the dead time at two sides;
and the input end of the output driving level generating circuit is connected with the output end of the comparator circuit and is used for selectively generating the in-phase or anti-phase output driving level.
2. A circuit for generating dead time in a driver circuit according to claim 1, wherein the dead time generating circuit includes a ramp generating circuit and a comparator circuit;
the slope generating circuit comprises a falling edge delay circuit and a rising edge delay circuit, the falling edge delay circuit and the rising edge delay circuit are controlled by an S end, the falling edge delay circuit is provided with a rectangular wave input port VD1, and the rising edge delay circuit is provided with a rectangular wave input port VD 2.
3. The circuit for generating dead time in a driving circuit according to claim 2, wherein the falling edge delay circuit comprises a switching tube M1 and a switching tube M3, the drain of the switching tube M1 and the drain of the switching tube M3 are connected and are both connected with the comparator circuit, the gate of the switching tube M1 is connected with the S terminal, and the source is connected with the rising edge delay circuit; the source electrode of the switching tube M3 is connected with the comparator circuit, and the grid electrode of the switching tube M3 is connected with the rectangular wave input port VD 1;
the rising edge delay circuit comprises a switch tube M2 and a switch tube M4, wherein the source electrode of the switch tube M4 is connected with the source electrode of the switch tube M1, the grid electrode of the switch tube M4 is connected with the rectangular wave input port VD2, and the drain electrode of the switch tube M2 is connected with the drain electrode of the switch tube M4; the grid electrode of the switching tube M2 is connected with the end S, and the source electrode is respectively connected with the drain electrodes of the switching tube M1 and the switching tube M3 and is connected to the comparator circuit;
a power supply VDD is connected between the source electrode of the switch tube M4 and the source electrode of the switch tube M1, and a ground wire is connected between the source electrode of the switch tube M3 and the comparator circuit.
4. A circuit for generating dead time in a driver circuit as claimed in claim 3 wherein said comparator circuit comprises a capacitor C and a comparator COMP 1;
two ends of the capacitor C are respectively connected with a ground wire, a source electrode of the switch tube M2, a drain electrode of the switch tube M1 and a drain electrode of the switch tube M3, an anode of the comparator COMP1 is connected with a source electrode of the switch tube M2, a drain electrode of the switch tube M1 and a drain electrode of the switch tube M3, a cathode of the comparator COMP1 is connected with a VREF end, and an output end of the comparator COMP1 outputs a signal VO.
5. A circuit for generating dead time in a driver circuit as claimed in claim 4, wherein the current generating circuit comprises
The first current mirror circuit comprises a switching tube M17 and a switching tube M18, the drains of the switching tube M17 and the switching tube M18 are interconnected, the positive electrode of an output end COMP2 of a comparator COMP2 is connected with a VREF end, and the negative electrode of the output end COMP2 of the comparator COMP2 is connected with a TIME end; the source electrode of the switching tube M17 is connected with the grid electrode of a switching tube M19, the source electrode of the switching tube M18 is connected with the grid electrode of a switching tube M20, and the source electrodes of the switching tube M19 and the switching tube M20 are interconnected;
the second current mirror circuit comprises a switching tube M27, a switching tube M28 and a switching tube M33; the drain electrode of the switching tube M28 is connected with the source electrode of the switching tube M8;
the third current mirror circuit comprises a switching tube M29, a switching tube M30, a switching tube M34, a switching tube M35, a switching tube M36 and a switching tube M37, wherein the drain electrode of the switching tube M29 is connected with the drain electrode of the switching tube M20;
the drain of the switching tube M36 is connected with the source of a switching tube M25, the drain of the switching tube M37 is connected with the source of a switching tube M26, and the gates of the switching tube M25 and the switching tube M26 are interconnected; the drain of the switching tube M25 is connected with the drain of the switching tube M23, the drain of the switching tube M26 is connected with the drain of the switching tube M24, and the gates of the switching tube M23 and the switching tube M24 are interconnected;
the fourth current mirror circuit comprises a switching tube M15 and a switching tube M16, and the gates of the switching tube M15 and the switching tube M16 and the drain of the switching tube M15 are both connected with the drain of the switching tube M30;
a fifth current mirror circuit, which includes a switching tube M31 and a switching tube M32, the drain of the switching tube M31 is connected with the source of the switching tube M22, the drain of the switching tube M22 is connected with the drain of the switching tube M21, the source of the switching tube M20 and the source of the switching tube M19, the gates of the switching tube M22 and the switching tube M21 are interconnected, and the source of the switching tube M21 is connected with the drain of the switching tube M16;
a sixth current mirror circuit, which includes a switching tube M8, a switching tube M9, a switching tube M10, a switching tube M11, a switching tube M13 and a switching tube M14, wherein the drain and the gate of the switching tube M8 are connected to the drain of the switching tube M19; the drain electrode of the switching tube M14 is connected with the source electrode of the switching tube M24;
a seventh current mirror circuit, which includes a switching tube M5, a switching tube M6, a switching tube M7 and a switching tube M12, wherein the drain of the switching tube M5 is interconnected with the gate, and the drain of the switching tube M12 is connected with the drains of the switching tube M34 and the switching tube M35;
the interconnected circuits of the drains of the switching tube M19 and the switching tube M20 are connected with the interconnected circuits of the drains of the switching tube M21 and the switching tube M22; the grid interconnection circuit of the switching tube M21 and the switching tube M22 is connected with the grid interconnection circuit of the switching tube M23, the switching tube M24, the switching tube M25 and the switching tube M26.
6. A circuit for generating dead time in a driver circuit according to claim 5, wherein the sources of the switching transistors of the second, third, fourth and fifth current mirror circuits are all grounded; and the sources of the sixth current mirror circuit and the sixth current mirror circuit are both connected with a power supply VDD.
7. A circuit for producing dead time in a driver circuit as claimed in claim 1, wherein the comparator circuit comprises
The eighth current mirror circuit comprises a switching tube M38, a switching tube M39, a switching tube M55 and a switching tube M56, wherein the sources of the switching tube M38, the switching tube M39, the switching tube M55 and the switching tube M56 are all connected with a power supply VDD, and the power supply VDD is also connected with the sources of the switching tube M41, the switching tube M48, the switching tube M50, the switching tube M52A, the switching tube M53, the switching tube M62, the switching tube M64 and the switching tube M67;
the gate of the switching tube M41 is connected with the output end of a nand gate E1, one input end of the nand gate E1 is connected with the S end, the other input end of the nand gate E1 is connected with the output end of a not gate F1, the output end of the not gate F1 is connected with the output end of a not gate F2 and the input end of an and gate W1, the other input end of the and gate W1 is connected with the output end of the not gate F3, and the output end of the and gate W1 is connected with the gate of the switching tube M42;
the drains of the switching tube M41 and the switching tube M42 are interconnected and are provided with an I2 end, the drains of the switching tube M41 and the switching tube M42 are interconnected and are connected with the gate of the switching tube M43, the drain of the switching tube M39 is connected with the sources of the switching tube M43 and the switching tube M44, respectively, and the gate of the switching tube M44 is connected with a VREF end;
a ninth current mirror circuit, which includes a switching tube M45 and a switching tube M46, the drain of the switching tube M43 is connected to the gate of the switching tube M46 and the drain and the gate of the switching tube M45, respectively, and the drains of the switching tube M44 and the switching tube M46 are interconnected and connected to the gate of the switching tube M47;
the drains of the switching tube M48 and the switching tube M497 are interconnected and connected with the drain interconnection circuit of the switching tube M40 and the switching tube M47; the drains of the switching tube M48 and the switching tube M49 are interconnected and connected with a switching tube M50 and a switching tube M51 grid interconnection circuit, the drains of the switching tube M50 and the switching tube M51 are interconnected and connected with a switching tube M52A and a switching tube M52B grid interconnection circuit, and the drains of the switching tube M52A and the switching tube M52B are interconnected and provided with a Y1 end;
the gate of the switching tube M53 is connected with the output end of a nand gate E2, one input end of the nand gate E2 is connected with the S end, the other input end is connected with the output end of a not gate F4, the input end of the not gate F4 is connected with the output end of a not gate F5, the in-out section of the not gate F5 is connected with the input end of the not gate F6, and the input end of the not gate F6 is connected with a clock signal VD; the output end of the not gate F6 is also connected with one input end of an and gate W2, the other input end of the and gate W2 is connected with the output end of a not gate F7, the input end of the not gate F7 is connected with an S end, the output end of the and gate W2 is connected with the grid of a switch tube M54, and the drains of the switch tube M53 and the switch tube M54 are interconnected and are provided with an I1 end; the drains of the switch tube M53 and the switch tube M54 are interconnected and connected with the grid of the switch tube M57; the drain electrode of the switching tube M55 is respectively connected with the source electrodes of the switching tube M57 and the switching tube M58, the grid electrode of the switching tube M58 is connected with the VREF end, and the drain electrodes of the switching tube M57 and the switching tube M58 are connected with the ninth current mirror circuit;
the drain of the switching tube M58 is also connected with the grid of a switching tube M61, the drains of the switching tube M56 and the switching tube M61 are interconnected and are connected with a switching tube M62 and a switching tube M63 grid interconnection circuit, the drains of the switching tube M62 and the switching tube M63 are interconnected and are connected with a switching tube M64 and a switching tube M65 grid interconnection circuit, the drains of the switching tube M64 and the switching tube M65 are interconnected and are connected with a switching tube M67 and a switching tube M68 grid interconnection circuit, and the drains of the switching tube M67 and the switching tube M68 are interconnected and are provided with a Y2 end;
the source electrodes of the switching tube M42, the switching tube M45, the switching tube M46, the switching tube M47, the switching tube M49, the switching tube M51, the switching tube M52B, the switching tube M54, the switching tube M61, the switching tube M63, the switching tube M65 and the switching tube M68 are all grounded.
8. The circuit for generating dead time in a driving circuit as claimed in claim 7, wherein the circuit in which the drains of the switching tube M41 and the switching tube M42 are interconnected and the gate of the switching tube M43 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is grounded;
the drains of the switching tube M53 and the switching tube M54 are interconnected, and the circuit connected with the gate of the switching tube M57 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is grounded.
9. A circuit for generating dead time in a driver circuit as claimed in claim 1 wherein said output drive level generating circuit comprises selector a1 and selector a 2;
the input end of the selector A1 is respectively connected with the output end of an NOT gate F8 and the output end of an NOT gate F9, the input end of the NOT gate F8 is connected with an end Y2, the input end of the NOT gate F9 is connected with an end Y1, and the output end of the selector A1 is connected with the input end of an AND gate W3;
the input end of the selector A2 is respectively connected with the output end of an NOT gate F8 and the output end of an NOT gate F10, the input end of the NOT gate F10 is connected with the output end of an NOT gate F8, and the output end of the selector A2 is connected with the input end of an AND gate W4;
the input ends of the and gate W3 and the and gate W4 are interconnected, the output end of the and gate W3 outputs a signal YA, and the output end of the and gate W4 outputs a signal YB.
10. A method for generating dead time in a driver circuit, wherein a circuit for generating dead time in a driver circuit according to any of claims 1 to 9 comprises the steps of:
the resistor is connected with the resistor through the TIME end, the resistor is connected with GND or VDD, the charging and discharging current for the dead TIME generating circuit is generated, and the S end voltage is used for controlling charging or discharging; when the resistor is connected with GND and the S end voltage is low level, charging the voltage of the input end of the comparator; when the resistor is connected with VDD and the voltage of the S end is high level, charging the voltage of the input end of the comparator;
a comparator circuit generating a double-sided dead time; when the resistor is connected with GND, the left comparator generates a left dead time, and the right comparator generates a right dead time; when the resistor is connected with VDD, the left comparator generates right dead time, and the right comparator generates left dead time;
an output drive level generation circuit selectively generating an in-phase or an inverted output drive level; when the resistor is connected with GND, the S end is at low level, and the generated output driving levels YA and YB are in the same phase; when the resistor is connected with VDD, the S end is high level, the generated output driving levels YA and YB are in opposite phase, and dead time is generated in the driving circuit.
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