CN105186636B - power charging circuit - Google Patents
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- CN105186636B CN105186636B CN201510727461.3A CN201510727461A CN105186636B CN 105186636 B CN105186636 B CN 105186636B CN 201510727461 A CN201510727461 A CN 201510727461A CN 105186636 B CN105186636 B CN 105186636B
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Abstract
The present invention provides a kind of power charging circuit, including：Current-limiting resistance, first end connect input voltage anode；Output capacitance, first end connect the second end of the current-limiting resistance, and second end connection input voltage negative terminal is simultaneously grounded, and the voltage between the input voltage anode and input voltage negative terminal is input voltage, and the voltage at the output capacitance both ends is output voltage；Current-limiting control circuit, its input terminal connects the input voltage anode, its output end connects the first end of the output capacitance, the output end output current limiting electric current of the current-limiting control circuit, the cut-off current is limited to less than before charging complete equal to preset cut-off current, and the cut-off current is no longer limited after charging complete.The present invention can either avoid overcurrent risk of the power supply in charging process, and can provide enough load currents after completing to charge.
Description
Technical field
The present invention relates to power source charges technology more particularly to a kind of power charging circuits.
Background technology
Various types of power supplys such as Switching Power Supply at work, will first fill the output capacitance of output port of power source
Electricity after charging complete, then is powered the load of output port.In power source charges, in order to prevent charging current it is excessive and
The elements such as output capacitance are damaged, current-limiting resistance is generally used and current limliting is carried out to charging current.
With reference to figure 1, Fig. 1 shows a kind of electrical block diagram of power charging circuit 100 in the prior art.The power supply
Charging circuit 100 includes an a current-limiting resistance R0 and output capacitance C0, which is used to provide load electricity to load
Flow Iload.
When starting to charge up, input voltage VIN charges to output capacitance C0 by current-limiting resistance R0, and by current-limiting resistance
R0 limits the size of charging current so that output voltage VO UT is increased close to input voltage VIN from 0V；It is defeated after completing charging
Enter voltage VIN and provide load current Iload further through current-limiting resistance R0 for load, current-limiting resistance R0 will also limit load current
The size of Iload.
The charging current of output capacitance C0 is limited using current-limiting resistance R0, there are when charging overcurrent risk and fill
The contradiction between power supply capacity after electricity.If the resistance value of current-limiting resistance R0 is excessive, electric current when charging will become smaller, no
There are the risks of overcurrent, but after charging, the load current Iload for powering to the load is also restrained and becomes smaller；If
The resistance value of current-limiting resistance R0 is too small, then electric current when charging becomes larger, the load current Iload to power after charging also becomes larger
, still, since charging current becomes larger, there are the risks of overcurrent.
Invention content
The problem to be solved in the present invention is to provide a kind of power charging circuit, can either avoid power supply in charging process
Overcurrent risk, and enough load currents can be provided after completing to charge.
In order to solve the above technical problems, the present invention provides a kind of power charging circuits, including：
Current-limiting resistance, first end connect input voltage anode；
Output capacitance, first end connect the second end of the current-limiting resistance, and second end connects input voltage negative terminal simultaneously
Ground connection, the voltage between the input voltage anode and input voltage negative terminal are input voltage, the electricity at the output capacitance both ends
Pressure is output voltage；
Current-limiting control circuit, input terminal connect the input voltage anode, and output end connects the output capacitance
First end, the output end output current limiting electric current of the current-limiting control circuit, the cut-off current are limited before charging complete
To be less than or equal to preset cut-off current, the cut-off current is no longer limited after charging complete.
According to one embodiment of present invention, the power charging circuit to the charging process of the output capacitance include according to
The secondary first stage to connect, second stage and phase III, wherein
The first stage starts to charge up process for the output capacitance, and the cut-off current is zero in the first stage,
It only flows through the electric current of the current-limiting resistance and provides charging current for the output capacitance；
The second stage is the quickening charging process of the output capacitance, and the cut-off current is on second stage is gradual
The cut-off current is risen to, the electric current and the cut-off current for flowing through the current-limiting resistance provide charging for the output capacitance jointly
Electric current；
The phase III is that the output capacitance completes the process after charging, flows through electric current and the institute of the current-limiting resistance
It states cut-off current and provides load current jointly for load.
According to one embodiment of present invention, in the second stage, if the cut-off current rises to the limit
Before flow valuve, the output capacitance has been completed to charge, then is directly entered the phase III；In the second stage, such as
Cut-off current described in fruit rises to after the cut-off current, and the output capacitance does not complete charging, then the cut-off current is kept
For the cut-off current, the phase III is entered after completing charging.
According to one embodiment of present invention, the current-limiting control circuit includes：
Limit detection circuit is detected the voltage difference of the input voltage and output voltage, is generated after relatively
First Current limited Control signal；
Level displacement circuit directly or indirectly carries out level shift to generate second to the first Current limited Control signal
Current limited Control signal；
Current limliting output circuit, it is in parallel with the current-limiting resistance, it is generated under the control of the second Current limited Control signal defeated
Go out the cut-off current.
According to one embodiment of present invention, the power charging circuit to the charging process of the output capacitance include according to
The secondary first stage to connect, second stage and phase III, wherein
In the first stage, the limit detection circuit detects that the output voltage is zero, the current limliting output electricity
The cut-off current that road generates is zero, only flows through charging current of the electric current of the current-limiting resistance as the output capacitance, institute
It is that the output capacitance starts to charge up process to state the first stage；
In the second stage, the limit detection circuit detects that the voltage difference of the input voltage and output voltage is big
Judge a little in into Current limited Control, then the first Current limited Control signal is logic high, is generated by level displacement circuit
The second Current limited Control signal be logic low, then control the cut-off current that the current limliting output circuit generates and gradually rise up to
The cut-off current, the cut-off current and flows through the electric current of the current-limiting resistance together as the charging current of output capacitance, institute
State the quickening charging process that second stage is the output capacitance；
In the phase III, the limit detection circuit detects that the voltage difference of the input voltage and output voltage is small
Judge a little in exiting Current limited Control, then the first Current limited Control signal is logic low, by the level displacement circuit
The the second Current limited Control signal generated is logic high, then controls the cut-off current of current limliting output circuit generation and flow through described
The electric current of current-limiting resistance provides load current for load jointly, and the phase III is that the output capacitance completes the mistake after charging
Journey.
According to one embodiment of present invention, in the second stage, if the cut-off current rises to the limit
Before flow valuve, the output capacitance has been completed to charge, then is directly entered the phase III；In the second stage, such as
Cut-off current described in fruit rises to after the cut-off current, and the output capacitance does not complete charging, then the cut-off current is kept
For the cut-off current, the phase III is entered after completing charging.
According to one embodiment of present invention, the current-limiting control circuit further includes：Current limliting delay circuit, to described first
For the delay of Current limited Control signal to generate time delayed signal, the level displacement circuit carries out level shift to obtain to the time delayed signal
To the second Current limited Control signal.
According to one embodiment of present invention, the power charging circuit to the charging process of the output capacitance include according to
The secondary first stage to connect, second stage and phase III, wherein
In the first stage, the limit detection circuit detects that the output voltage is zero, the current limliting output electricity
The cut-off current that road generates is zero, only flows through charging current of the electric current of the current-limiting resistance as the output capacitance, institute
It is that the output capacitance starts to charge up process to state the first stage；
In the second stage, the limit detection circuit detects that the voltage difference of the input voltage and output voltage is big
Judge a little in into Current limited Control, then the first Current limited Control signal is logic high, by the current limliting delay circuit
The time delayed signal of generation is logic low, is logic using the second Current limited Control signal that the level displacement circuit generates
Low level then controls the cut-off current that the current limliting output circuit generates and gradually rises up to the cut-off current, the cut-off current
With flow through the electric current of the current-limiting resistance charging current as the output capacitance together, the second stage is the output
The quickening charging process of capacitance；
In the phase III, the limit detection circuit detects that the voltage difference of the input voltage and output voltage is small
Judge a little in exiting Current limited Control, then the first Current limited Control signal is logic low, by the current limliting delay circuit
The time delayed signal of generation is logic high, is logic using the second Current limited Control signal that the level displacement circuit generates
High level, the then cut-off current for controlling the current limliting output circuit generation and the electric current for flowing through the current-limiting resistance are load jointly
Load current is provided, the phase III is that the output capacitance completes the process after charging.
According to one embodiment of present invention, in the second stage, if the cut-off current rises to the limit
Before flow valuve, the output capacitance has been completed to charge, then is directly entered the phase III；In the second stage, such as
Cut-off current described in fruit rises to after the cut-off current, and the output capacitance does not complete charging, then the cut-off current is kept
For the cut-off current, the phase III is entered after completing charging.
According to one embodiment of present invention, the limit detection circuit includes：
Internal power source voltage generative circuit receives the output voltage and is converted into internal power source voltage；
The internal power source voltage is converted to the first bias current by the first bias current generative circuit；
First voltage turns current circuit, and the input voltage is converted to the first electric current；
Second voltage turns current circuit, and the output voltage is converted to the second electric current；
First current mirror, input terminal receive first electric current, and output end receives second electric current, the electric current
Mirror is compared to generate comparison signal first electric current and the second electric current；
9th MOS transistor, first bias current are transmitted to after the second current mirror and third current mirror mirror image
The grid of the drain electrode of 9th MOS transistor, the 9th MOS transistor receives the comparison signal, and the 9th MOS is brilliant
The source electrode of body pipe is grounded, and the drain electrode of the 9th MOS transistor exports the first Current limited Control signal.
According to one embodiment of present invention, the first voltage turns current circuit and includes：First resistor, the first termination
The input voltage is received, second end exports first electric current.
According to one embodiment of present invention, the second voltage turns current circuit and includes：Second resistance, the first termination
The output voltage is received, second end exports second electric current.
According to one embodiment of present invention, the second voltage turns current circuit and includes：
Second resistance, first end receive the output voltage；
Current limliting hysteresis circuitry, input terminal connect the second end of the second resistance, output end output second electricity
Stream, the current limliting hysteresis circuitry adjust second electric current under the control of the second Current limited Control signal.
According to one embodiment of present invention, the current limliting hysteresis circuitry includes：
3rd resistor, first end connect the second end of the second resistance, and second end connects first current mirror
Output end；
Third MOS transistor, drain electrode connect the first end of the 3rd resistor, and source electrode connects the 3rd resistor
Second end, grid receive the second Current limited Control signal.
According to one embodiment of present invention, the internal power source voltage generative circuit includes：
4th resistance, first end receive the output voltage；
First clamp diode, cathode connect the second end of the 4th resistance, plus earth；
4th MOS transistor, drain electrode receive the output voltage, and grid connects the second end of the 4th resistance,
Its source electrode exports the internal power source voltage.
According to one embodiment of present invention, the first bias current generative circuit includes：5th resistance, first end
The source electrode of the 4th MOS transistor is connected, second end exports first bias current.
According to one embodiment of present invention, the current limliting delay circuit includes：
Charge-discharge control circuit, first bias current after the second current mirror and the 4th current mirror mirror image via being transmitted to
The control terminal of the input terminal of the charge-discharge control circuit, the charge-discharge control circuit receives the first Current limited Control letter
Number；
Capacitance, first end connect the output end of the charge-discharge control circuit, and second end is grounded, and the charge and discharge is automatically controlled
Circuit processed is charged or is discharged under the control of the first Current limited Control signal, to the capacitance, the capacitance
First end export the time delayed signal.
According to one embodiment of present invention, the charge-discharge control circuit includes：
11st MOS transistor, input terminal of the source electrode as the charge-discharge control circuit, grid receive described the
One Current limited Control signal, drain electrode connect the first end of the capacitance；
12nd MOS transistor, drain electrode connect the first end of the capacitance, and grid receives first Current limited Control
Signal, source electrode ground connection.
According to one embodiment of present invention, the level displacement circuit includes：
Phase inverter carries out reverse phase to the time delayed signal；
15th MOS transistor, grid receive the time delayed signal, source electrode ground connection；
16th MOS transistor, grid connect the output end of the phase inverter to receive the reverse phase of the time delayed signal
Signal, source electrode ground connection；
17th MOS transistor, source electrode receive the output voltage, and drain electrode connects the 15th MOS transistor
Drain electrode；
18th MOS transistor, source electrode receive the output voltage, and drain electrode connects the 17th MOS transistor
Grid and the 16th MOS transistor drain electrode, grid connects the drain electrode of the 17th MOS transistor；
Wherein, the drain electrode of the 16th MOS transistor and the 18th MOS transistor exports the second Current limited Control letter
Number.
According to one embodiment of present invention, the level displacement circuit includes：
Phase inverter carries out reverse phase to the first Current limited Control signal；
15th MOS transistor, grid connects the output end of the phase inverter to be believed with receiving first Current limited Control
Number inversion signal, source electrode ground connection；
16th MOS transistor, grid receive the first Current limited Control signal, source electrode ground connection；
17th MOS transistor, source electrode receive the output voltage, and drain electrode connects the 15th MOS transistor
Drain electrode；
18th MOS transistor, source electrode receive the output voltage, and drain electrode connects the 17th MOS transistor
Grid and the 16th MOS transistor drain electrode, grid connects the drain electrode of the 17th MOS transistor；
Wherein, the drain electrode of the 16th MOS transistor and the 18th MOS transistor exports the second Current limited Control letter
Number.
According to one embodiment of present invention, the current limliting output circuit includes：
5th current mirror carries out mirror image to obtain the second bias current to first bias current；
20th MOS transistor, grid receive the second Current limited Control signal；
7th resistance, first end connect the drain electrode of the 20th MOS transistor, second end connection the 5th electricity
Flow the output end of mirror；
21st MOS transistor, source electrode connect the input terminal of the current-limiting control circuit, drain electrode connection described the
The source electrode of 20 MOS transistors, grid connect the drain electrode of the 20th MOS transistor；
22nd MOS transistor, source electrode connect the input terminal of the current-limiting control circuit, and drain electrode connects the limit
The output end of flow control circuit, grid connect the grid of the 21st MOS transistor, flow through the 22nd MOS
The electric current of transistor is the cut-off current；
6th resistance, first end connect the input terminal of the current-limiting control circuit, second end connection the described 20th
The first end of the grid of one MOS transistor and the 7th resistance；
Second clamp diode, cathode connect the input terminal of the current-limiting control circuit, anode connection described second
The grid of 12 MOS transistors.
According to one embodiment of present invention, when the 20th MOS transistor is connected, the 21st MOS is brilliant
Body pipe and the 22nd MOS transistor form current mirror, and second bias current is described via being obtained after the current mirror mirror image
Cut-off current, the cut-off current and flows through the electric current of the current-limiting resistance charging current as the output capacitance together；When
When 20th MOS transistor turns off, the input voltage passes through the branch pressure voltage that the 6th resistance and the 7th resistance generate
Gate source voltage as the 22nd MOS transistor cut-off current and flows through the limit to obtain the cut-off current
The electric current of leakage resistance is together as the load current of supplying power for outside.
Compared with prior art, the present invention has the following advantages：
The power charging circuit of the embodiment of the present invention increases the current-limiting control circuit in parallel with current-limiting resistance, the current limliting control
Circuit processed provides additional cut-off current, is limited charging current before charging complete, and cut-off current is less than or equal to pre-
If cut-off current so that the charging current for flowing to output capacitance will not be excessive, is conducive to avoid overcurrent risk；Charging complete it
Afterwards, cut-off current is no longer limited, which can be more than the cut-off current, so as to provide sufficiently large load electricity
Stream.Overcurrent risk when the power charging circuit of the embodiment of the present invention can solve to charge in the prior art and the power supply after charging
Contradiction between ability.
Description of the drawings
Fig. 1 is a kind of electrical block diagram of power charging circuit in the prior art；
Fig. 2 is the circuit structure block diagram of power charging circuit according to a first embodiment of the present invention；
Fig. 3 is the detailed circuit structure of the current-limiting control circuit in power charging circuit according to a first embodiment of the present invention
Figure；
Fig. 4 is the working signal waveform diagram of power charging circuit shown in Fig. 3；
Fig. 5 is the circuit structure block diagram of power charging circuit according to a second embodiment of the present invention；
Fig. 6 is the detailed circuit structure of the current-limiting control circuit in power charging circuit according to a second embodiment of the present invention
Figure；
Fig. 7 is the working signal waveform diagram of power charging circuit shown in Fig. 6；
Fig. 8 is the circuit structure block diagram of power charging circuit according to a third embodiment of the present invention；
Fig. 9 is the detailed circuit structure of the current-limiting control circuit in power charging circuit according to a third embodiment of the present invention
Figure；
Figure 10 is the working signal waveform diagram of power charging circuit shown in Fig. 9.
Specific implementation mode
With reference to specific embodiments and the drawings, the invention will be further described, but the guarantor of the present invention should not be limited with this
Protect range.
First embodiment
With reference to figure 2, Fig. 2 shows the electrical block diagrams of the power charging circuit 200 of first embodiment.The power supply fills
Circuit 200 include current-limiting resistance R0, current-limiting control circuit 201 and output capacitance C0, the power charging circuit 200 be used for
Load provides load current Iload.
Wherein, the first end of current-limiting resistance R0 connects input voltage anode；The first end connection current limliting electricity of output capacitance C0
The second end of R0 is hindered, the second end connection input voltage negative terminal of output capacitance C0 is simultaneously grounded, input voltage anode and input voltage
Voltage between negative terminal is input voltage VIN, and the voltage at the both ends output capacitance C0 is output voltage VO UT；Current-limiting control circuit
201 input terminal connects the input voltage anode, and output end connects the first end of the output capacitance.
Current-limiting resistance R0 limits the electric current for flowing through current-limiting resistance R0.Current-limiting control circuit 201 is then to charge
When, the electric current to output capacitance C0 chargings from input voltage anode to output voltage anode is controlled；It completes to charge
Afterwards, and the load current Iload of the powering load to flowing to output voltage negative terminal from output voltage anode is controlled.Current limliting
The output end output current limiting electric current IOUT of control circuit 201, cut-off current IOUT are limited to less than before charging complete
In preset cut-off current, cut-off current IOUT is no longer limited after charging complete.Wherein, " charging complete " is commonly referred to as
The output voltage VO UT at the both ends output capacitance C0 rises to equal with input voltage VIN.
Still further, the charging process of output capacitance C0 includes the first stage to connect successively, second stage and
Three stages；
The process that starts to charge up that first stage is output capacitance C0, cut-off current IOUT are 0, only flow through current-limiting resistance R0
Electric current smaller charging current is provided for output capacitance C0；
Second stage is the quickening charging process of output capacitance C0, and cut-off current IOUT gradually rises up to cut-off current from 0, is flowed
The electric current and cut-off current IOUT for crossing current-limiting resistance R0 provide the charging current incrementally increased for output capacitance C0；
Phase III is the completion charging process of output capacitance C0, and cut-off current IOUT is no longer limited, and flows through current limliting electricity
Electric current and the cut-off current IOUT for hindering R0 provide load current Iload for load.In the phase III, current-limiting control circuit 201 has
It is provided with the ability of the cut-off current IOUT more than the cut-off current, but according to the needs of actual loading, cut-off current IOUT
Actual value be likely larger than the cut-off current, be equal to the cut-off current or be less than the cut-off current.
Current-limiting control circuit 201 may include limit detection circuit 202, current limliting delay circuit 205, level displacement circuit
203 and current limliting output circuit 204.
Wherein, limit detection circuit 202 is that the voltage difference between input voltage VIN and output voltage VO UT is examined
It surveys, the first Current limited Control signal ILIMIT1 is generated after relatively；Current limliting delay circuit 205 is by the first Current limited Control signal
ILIMIT1 is into obtaining time delayed signal IDELAY after line delay；Level displacement circuit 203 is to time delayed signal IDELAY into line level position
The second Current limited Control signal ILIMIT2 is obtained after shifting；Current limliting output circuit 204 is generated by the second Current limited Control signal ILIMIT2
The cut-off current of control.Specifically, the cut-off current that current limliting output circuit 204 is generated in charging is used for output capacitance C0
Charging, as a part for charging current, cut-off current at this time is restricted to be no more than preset cut-off current；Current limliting output electricity
The cut-off current that road 204 generates after completing to charge is for powering to the load, as a part of load current Iload, at this time
Cut-off current be released from limitation.
Furthermore, in the first stage, limit detection circuit 202 detects that output voltage VO UT is zero, current limliting output
The cut-off current that circuit 204 generates is zero, only flows through charging current of the electric current of current-limiting resistance R0 as output capacitance C0, the
One stage started to charge up process for output capacitance C0's；In second stage, limit detection circuit 202 detects input voltage VIN
It is more than into Current limited Control with the voltage difference of output voltage VO UT and judges a little, then the first Current limited Control signal ILIMIT1 is logic
High level is logic low by the second Current limited Control signal ILIMIT2 that level displacement circuit 203 generates, then controls limit
The cut-off current that stream output circuit 204 generates gradually rises up to cut-off current, cut-off current and the electric current one for flowing through current-limiting resistance R0
And as the charging current of output capacitance, second stage is the quickening charging process of output capacitance C0；In the phase III, current limliting inspection
Slowdown monitoring circuit 202 detects that the voltage difference of input voltage VIN and output voltage VO UT are less than and exits Current limited Control and judge a little, then first
Current limited Control signal ILIMIT1 is logic low, the second Current limited Control signal generated by level displacement circuit 203
ILIMIT2 is logic high, then controls the cut-off current of the generation of current limliting output circuit 204 and flow through the electric current of current-limiting resistance R0
Common to provide load current for load, the phase III is that the output capacitance completes the process after charging.
With reference to figure 3, Fig. 3 shows the particular circuit configurations signal of the current-limiting control circuit 201 of first embodiment of the invention
Figure.
Wherein, limit detection circuit 202 may include that first voltage turns current circuit 2021, second voltage turns current circuit
2022, internal power source voltage generative circuit 2023, the first bias current generative circuit 2024, first the 2025, second electricity of current mirror
Flow mirror 2026, third current mirror 2027 and MOS transistor M9.
Wherein, output voltage VO UT is converted to limit detection circuit 202 and limit by internal power source voltage generative circuit 2023
Stream delay circuit 203 works required internal power source voltage LVDD.The internal power source voltage generative circuit 2023 may include：
Resistance R4, first end receive output voltage VO UT；Clamp diode D1, cathode connect the second end of resistance R4, anode
Ground connection；MOS transistor M4, drain electrode receive output voltage, and grid connects the second end of resistance R4, and source electrode exports inside this
Supply voltage LVDD.
Internal power source voltage LVDD is converted to the first bias current IB1 by the first bias current generative circuit 2024.First
Bias current generative circuit 2024 may include resistance R5, the source electrode of the first end connection MOS transistor M4 of resistance R5, internal electricity
Source voltage LVDD generates the first bias current IB1 via resistance R5, and the first bias current IB1 is defeated by the second end of resistance R5
Go out.
First voltage turns current circuit 2021 and input voltage VIN is converted to the first electric current IIN1.First voltage turns electric current
Circuit 2021 may include resistance R1, and first end receives input voltage VIN, and input voltage VIN flows through resistance R1 and generates first
Electric current IIN1, the first electric current IIN1 are exported via the second end of resistance R1.
Second voltage turns current circuit 2022 and output voltage VO UT is converted to the second electric current IIN2.Second voltage turns electric current
Circuit 2022 may include：Resistance R2, first end receive output voltage VO UT；Current limliting hysteresis circuitry 206, input terminal connection
The second end of resistance R2, output end export the second electric current IIN2, and current limliting hysteresis circuitry 206 is according to the second Current limited Control signal
ILIMIT2 adjusts the current value of the second electric current IIN2.
As a preferred embodiment, current limliting hysteresis circuitry 206 may include：Resistance R3, first end connect resistance
The second end of R2, second end connect the output end of the first current mirror 2025；MOS transistor M3, drain electrode connection 3rd resistor
The first end of R3, source electrode connect the second end of 3rd resistor R3, and grid receives the second Current limited Control signal ILIMIT2.
Whether NMOS transistor M3 is short-circuit for controlling resistance R3 under the control of the second Current limited Control signal ILIMIT2,
To which the detection of the voltage difference between input voltage VIN and output voltage VO UT carries out sluggish control.
When more specifically, the second Current limited Control signal ILIMIT2 control MOS transistors M3 is connected (such as the second current limliting
It is high level to control signal ILIMIT2), resistance R3 is short-circuited so that output voltage VO UT is converted to second via resistance R2
Electric current IIN2.And when the second Current limited Control signal ILIMIT2 control MOS transistor M2 shutdowns (such as the second Current limited Control signal
ILIMIT2 is low level), resistance R3 connects with resistance R2 so that output voltage is converted to by resistance R2 and resistance R3
Two electric current IIN2.By the variation of resistance, current limliting sluggishness circuit 206 realizes the adjusting to the second electric current IIN2, so as to
Determine judgement when judging point and exiting Current limited Control of input voltage VIN and output voltage VO UT when entering Current limited Control
Point.
First current mirror 2025 includes MOS transistor M1 and MOS transistor M2.Be converted to by input voltage VIN
After one electric current IIN1 is via the first current mirror mirror image, and compared by the second electric current IIN2 that output voltage VO UT is converted to
Compared with, i.e., the voltage difference between input voltage VIN and output voltage VO UT is converted into current difference and is detected and compares, relatively after
The comparison signal ILIMIT0 of generation is for controlling MOS transistor M9 (MOS transistor M9 is, for example, NMOS transistor).
Second current mirror 2026 includes MOS transistor M5 and MOS transistor M6, and third current mirror 2027 includes MOS crystal
Pipe M7 and MOS transistor M8.First bias current IB1 provides pull-up partially by the second current mirror 2026 and third current mirror 2027
Electric current is set, to generate the first Current limited Control signal ILIMIT1.
Current limliting delay circuit 205 may include charge-discharge control circuit 2031 and capacitance C1.
Wherein, (the 4th current mirror for example can be with via the second current mirror 2026 and the 4th current mirror by the first bias current IB1
Including MOS transistor M7 and MOS transistor M10) after mirror image, it is transmitted to the input terminal of charge-discharge control circuit 2031, as electricity
Hold the charging current of C1.Charge-discharge control circuit 2031 under the control of the first Current limited Control signal ILIMIT1, to capacitance C1 into
Row is charged and discharged.
The charge-discharge control circuit 2031 may include：MOS transistor 11, source electrode is as charge-discharge control circuit 2031
Input terminal, grid receives the first Current limited Control signal ILIMIT1, the first end of drain electrode connection capacitance C1；MOS transistor
12, the first end of drain electrode connection capacitance C1, grid receives the first Current limited Control signal ILIMIT1, source electrode ground connection.
Capacitance C1 is charged or put by the first Current limited Control signal ILIMIT1 control charge-discharge control circuits 2031
Electricity, to generate time delayed signal IDELAY on capacitance C1.Time delayed signal IDELAY after 2032 reverse phase of phase inverter via generating
The inversion signal of time delayed signal IDELAY.Time delayed signal IDELAY and its inversion signal carry out electricity via level displacement circuit 203
Prosposition generates the second Current limited Control signal ILIMIT2 after moving.
Wherein, control charge-discharge control circuit 2031 produces delay during carrying out charge or discharge to capacitance C1
Td.Concrete principle is, when the first Current limited Control signal ILIMIT1 is low level, MOS transistor M11 conductings and MOS transistor
M12 is turned off, then the electric current exported from MOS transistor M10 charges to capacitance C1 by M11, to generate delay Td；First
When Current limited Control signal ILIMIT1 is high level, MOS transistor M11 shutdowns and MOS transistor M12 conductings, then capacitance C1 passes through
MOS transistor M12 carries out repid discharge, and be delayed very little at this time, can be ignored.
Level displacement circuit 203 may include：Phase inverter 2032 and level shift execution module 2033.
Wherein, phase inverter 2032 may include MOS transistor M13 and MOS transistor M14.The source of MOS transistor M13
Pole receives internal power source voltage LVDD, the grid reception delay signal IDELAY of MOS transistor M13；MOS transistor M14
Drain electrode connection M13 drain electrode, the grid reception delay signal IDELAY of MOS transistor M14, the source electrode of MOS transistor M14 connects
Ground.The inversion signal of the drain electrode output time delayed signal IDELAY of MOS transistor M13 and MOS transistor M14.
Level shift execution module 2033 may include：MOS transistor M15, grid reception delay signal IDELAY,
Source electrode is grounded；MOS transistor M16, grid connect the output end of phase inverter 2032 with the reverse phase of reception delay signal IDELAY
Signal, source electrode ground connection；MOS transistor M17, source electrode receive output voltage VO UT, drain electrode connection MOS transistor M15
Drain electrode；MOS transistor M18, source electrode receive output voltage VO UT, the grid of drain electrode connection MOS transistor M17 and
The drain electrode of MOS transistor M16, grid connect the drain electrode of MOS transistor M17；Wherein, MOS transistor M16 and MOS transistor
The drain electrode of M18 exports the second Current limited Control signal ILIMIT2.
It should be noted that the circuit structure of phase inverter 2032 shown in Fig. 3 and level displacement circuit 203 is only example, this
Field technology personnel should be appreciated that phase inverter 2032 and level displacement circuit 203 can also use in the prior art that other are appropriate
Circuit structure.
Current limliting output circuit 204 may include the 5th current mirror, MOS transistor M20~M22, resistance R5~R7 and pincers
Position diode D2.
Wherein, by the 5th current mirror, (the 5th current mirror includes MOS transistor M5 and MOS brilliant to the first bias current IB1
Body pipe M19) the required second bias current IB2 of current limliting is obtained after mirror image.
MOS transistor M20 for example can be PMOS transistor, and grid receives the second Current limited Control signal
ILIMIT2；The drain electrode of the first end connection MOS transistor M20 of resistance R7, second end connect the output end of the 5th current mirror,
Namely the drain electrode of MOS transistor M19；MOS transistor M21 for example can be PMOS transistor, and source electrode connects Current limited Control electricity
For the input terminal on road 201 to receive input voltage VIN, the source electrode of drain electrode connection MOS transistor M20, grid connects MOS crystal
The drain electrode of pipe M20；MOS transistor M22 source electrode connection current-limiting control circuit 201 input terminal to receive input voltage VIN,
For the output end of drain electrode connection current-limiting control circuit 201 to receive output voltage VO UT, grid connects the grid of MOS transistor M21
Pole, the electric current for flowing through MOS transistor M22 are the cut-off current IOUT that current-limiting control circuit provides；The first end of resistance R6 connects
The input terminal of current-limiting control circuit 201 is connect, second end connects the grid of MOS transistor M21 and the first end of resistance R7；Pincers
The input terminal of the cathode connection current-limiting control circuit 201 of position diode D2, anode connect the grid of MOS transistor M22.
In conjunction with Fig. 2 and Fig. 3, whether the second Current limited Control signal ILIMIT2 controls PMOS tube M21 by MOS transistor M20
The second bias current IB2 that current limliting needs is provided, i.e.,：When MOS transistor M20 is connected, from the input of current-limiting control circuit 201
The cut-off current IOUT for the output end for flowing to current-limiting control circuit 201 is held to pass through MOS transistor M21 and MOS by bias current IB2
The current mirror mirror image that transistor M22 is constituted obtains, cut-off current IOUT with flow through the electric current of current-limiting resistance R0 together as defeated
Go out the charging current of capacitance C0；When MOS transistor M20 is turned off, cut-off current IOUT no longer passes through MOS by bias current IB2
The current mirror mirror image that transistor M21 and MOS transistor M22 are constituted obtains, but is received by the input terminal of current-limiting control circuit 201
To input voltage VIN divide to obtain the gate source voltage of MOS transistor M22 by resistance R6 and resistance R7, the gate source voltage is true
The cut-off current IOUT of MOS transistor M22 is determined to flow through, cut-off current IOUT at this time and the electric current one for flowing through current-limiting resistance R0
It rises as the load current Iload to power to the load；Clamp diode D2 carries out clamper to the gate source voltage of MOS transistor M22
Protection.
With reference to figure 4, Fig. 4 shows the working signal waveform diagram of power charging circuit shown in Fig. 3.What Fig. 4 included
Signal has：Input voltage VIN, output voltage VO UT, internal power source voltage LVDD, the first Current limited Control signal ILIMIT1, delay
Signal IDELAY, the second Current limited Control signal ILIMIT2, the first bias current IB1, the second bias current IB2, cut-off current
IOUT。
In conjunction with Fig. 2, Fig. 3 and Fig. 4, the operation principle of the power charging circuit comprising Current limited Control of first embodiment is sketched
It is as follows：
When initial, input voltage VIN V1, output voltage VO UT are 0, then the second Current limited Control signal ILIMIT2 is also
0, then：
Input voltage VIN is more than with the voltage difference of output voltage VO UT by the resistance R1 and electricity in limit detection circuit 202
The judgement point V1-V4 into Current limited Control that R2 is determined is hindered, then enters Current limited Control；By the second Current limited Control signal ILIMIT2
The MOS transistor M3 shutdowns of control, resistance R3 is not short-circuit, and input voltage VIN and output voltage VO UT detect electricity by current limliting respectively
Resistance R1 and resistance R2 and R3 in road 202 are converted into the first electric current IIN1 and the second electric current IIN2, by the first electric current
The detection of IIN1 and the second electric current IIN2 are compared, and realize the inspection of the voltage difference between input voltage VIN and output voltage VO UT
Survey is compared, so that it is determined that the judgement point V1-V2 of input voltage VIN and output voltage VO UT when exiting Current limited Control；
By the MOS transistor M20 conductings of the second Current limited Control signal ILIMIT2 controls, the second bias current IB2 is by MOS
The current mirror mirror image that transistor M21 and MOS transistor M22 are constituted, flows to generate from the input terminal of current-limiting control circuit 201
The cut-off current IOUT of the output end of current-limiting control circuit 201, cut-off current IOUT and the electric current one for flowing through current-limiting resistance R0
The charging current as output capacitance C0 is played, that is, starts current-limiting charge；But since output voltage VO UT at this time is 0, MOS brilliant
The M4 shutdowns of body pipe, internal power source voltage LVDD are also 0, then the first bias current IB1 is 0 so that the second bias current IB2 and limit
Galvanic electricity stream IOUT is also 0, then the charging current of output capacitance C0 just only flows through the electric current of current-limiting resistance R0, due to current limliting
The resistance value of resistance R0 is larger, so charging current at this time is smaller, on the output voltage VO UT at the both ends output capacitance C0 is slow
It rises；
It is the first stage above, i.e. output capacitance C0's starts to charge up process.
When output voltage VO UT rises to cut-in voltage (or referred to as comparison point) VGS4 of MOS transistor M4, MOS is brilliant
The M4 conductings of body pipe, internal power source voltage LVDD starts to increase, and rises with the rising of output voltage VO UT, internal electric source electricity
The increase of pressure LVDD makes the first bias current IB1, the second bias current IB2 and cut-off current IOUT also begin to increase, then
The charging current of output capacitance C0 also increases therewith so that output voltage VO UT starts to accelerate to rise；
At this time since output voltage VO UT is still smaller, the voltage difference between input voltage VIN and output voltage VO UT is big
In the judgement point (V1- for exiting Current limited Control determined by resistance R1, resistance R2 and the resistance R3 in limit detection circuit 202
V2), the voltage for accordingly detecting the comparison signal ILIMIT0 compared is smaller, and MOS transistor M9 can't be made to be connected,
That is MOS transistor M9 is turned off, then the first Current limited Control signal ILIMIT1 is that (its voltage is equal to internal electric source to logic high
Voltage LVDD), then the MOS transistor M12 conductings in current limliting delay circuit 205, capacitance C1 are discharged by MOS transistor M12,
Since discharge current is unrestricted, delay time is very short, can be ignored, then time delayed signal IDELAY is logic low (voltage 0),
So that MOS transistor M15 shutdowns, MOS transistor M16 conductings in level displacement circuit 203, the second Current limited Control signal
ILIMIT2 is logic low (its voltage is 0), and the second Current limited Control signal ILIMIT2, which continues control MOS transistor M20, to be led
Logical, the second bias current IB2 continues through the current mirror mirror image that MOS transistor M21 and MOS transistor M22 are constituted and generates current limliting
Electric current IOUT, cut-off current IOUT and flow through the electric current of the current-limiting resistance R0 charging current as output capacitance C0 together；
When output voltage VO UT rises to the clamp voltage VZ1 of clamp diode D1, internal power source voltage LVDD is also
Reach clamp voltage LVDDclamp, then the first bias current IB1, the second bias current IB2 and cut-off current IOUT also reach respectively
To respective cut-off current IB1limit, IB2limit and IOUTlimit, the charging current of output capacitance C0 also reaches maximum at this time
Cut-off current (flows through the sum of electric current and cut-off current IOUTlimit of current-limiting resistance R0), and output voltage VO UT is pressed in this stage
Rise according to prestissimo and fixed speed rises；
Second stage above, i.e. the quickening charging process of output capacitance C0.It should be noted that if in cut-off current
IOUT rises to before cut-off current IOUTlimit, has completed to charge, has just been directly entered the phase III；If in cut-off current
IOUT rises to after cut-off current IOUTlimit, does not complete charging also, that cut-off current IOUT keeps cut-off current IOUTlimit
Continue to charge, the phase III is entered after completing to charge.
When output voltage VO UT rises to comparison point V2, which is less than with the voltage difference of input voltage VIN by current limliting
Resistance R1 judges point (V1-V2) with resistance R2 and the R3 current limliting determined in detection circuit 202, then Current limited Control is exited, by detecting
The comparison signal ILIMIT0 voltages compared also increase to can be so that MOS transistor M9 be connected, which is VGS9, that
First Current limited Control signal ILIMIT1 is by logic high (its voltage be equal to internal power source voltage LVDDclamp) saltus step
Logic low (such as voltage is 0), then the MOS transistor M11 conductings in current limliting delay circuit 205, transistor M12 shutdowns,
Capacitance C1 is charged by MOS transistor M11, due to charging current by the first bias current IB1 by MOS transistor M5 and
The current limit that the current mirror mirror image that M6, MOS transistor M7 and M10 are formed obtains, produces delay time Td, that is, what is exported prolongs
When signal IDELAY be that (its voltage is internal electric source to high level by low level (voltage 0) saltus step after Td time delays
LVDDclamp), then the MOS transistor M15 in level displacement circuit 203 also passes through after Td time delays just conducting, MOS crystal
Pipe M16 is turned off after Td time delays, and such second Current limited Control signal ILIMIT2 is after Td time delays by MOS crystalline substances
Body pipe M18 pull-up, is high level (voltage is output voltage VO UT), such output capacitance C0 by low level (voltage 0) saltus step
Charging current continue to cut-off current, then output voltage VO UT also always according to prestissimo, be also fixed speed rise, this
Sample can accelerate the output voltage VO UT rates of climb, can also stabilize the output voltage VOUT；And as the second Current limited Control signal ILIMIT2
After saltus step, then by the MOS transistor M3 conductings of the second Current limited Control signal ILIMIT2 controls, resistance R3 is short-circuited so that defeated
Go out the electric current that voltage VOUT is converted to by resistance R2 and be converted to electric current by resistance R1 with input voltage VIN to be compared,
So that it is determined that the judgement point (V1-V4) of input voltage VIN and output voltage VO UT when entering Current limited Control, this is with exiting current limliting
Judgement point (V1-V2) when control has sluggish range, prevents output voltage VO UT from being caused Current limited Control electric by load effect
Road 201 switches between entering and exiting two states of Current limited Control, to stabilize the output voltage VOUT；
By the MOS transistor M20 shutdowns of the second Current limited Control signal ILIMIT2 controls, from the defeated of current-limiting control circuit 201
The cut-off current IOUT for entering the output end that end flows to current-limiting control circuit 201 no longer passes through MOS crystal by the second bias current IB2
The current mirror mirror image that pipe M21 and MOS transistor M22 are constituted obtains, but passes through the partial pressure of resistance R6 and R7 by input voltage VIN
The gate source voltage of voltage control MOS transistor M22 obtains IOUTmax, and the second bias current IB2 is also no longer by MOS transistor
The current mirror mirror image that M5 and M19 is formed obtains, but obtains end value IB2end by input voltage VIN divided by resistance R6 and R7；
At this point, cut-off current IOUT together with the electric current for flowing through current-limiting resistance R0, in addition to the charging current as output capacitance C0, also makees
For the load current Iload to be powered by output voltage VO UT；
When output voltage VO UT gradually rises it is consistent with input voltage VIN when, internal electric source LVDD maintains clamping voltag
LVDDclamp, output voltage VO UT and input voltage VIN detection relatively after comparison signal ILIMIT0 voltage raised voltage
It to V3 and maintains, the first Current limited Control signal ILIMIT1 maintains low level (voltage 0), current limliting time delayed signal IDELAY to maintain
High level (voltage is internal electric source LVDDclamp), the second Current limited Control signal ILIMIT2 maintains high level, and (voltage is output
Voltage VOUT), the first bias current IB1 maintains cut-off current IB1limit, the second bias current IB2 to maintain end value IB2end,
Cut-off current IOUT maintains IOUTmax, and since the charging current of output capacitance C0 is gradually decreased to 0, that is, completes charging, then limit
Galvanic electricity stream IOUT all switchs to load current Iload with the electric current for flowing through current-limiting resistance R0；
It is the phase III above, i.e. the completion charging process of output capacitance C0 flows through the electric current and current limliting of current-limiting resistance R0
Electric current IOUT provides load current Iload for load jointly.It should be noted that, although cut-off current IOUT shown in Fig. 4 is
Maximum value IOUTmax, but this is merely representative of cut-off current IOUT with the ability more than cut-off current IOUTlimit, according to load
Actual demand, cut-off current IOUT can be more than in the phase III, be less than or equal to cut-off current IOUTlimit, and it is maximum
Value is IOUTmax, that is, possible net capability.
It should be noted that, although embodiment shown in Fig. 3 gives the physical circuit of each current mirror, but this field
It will be appreciated by the skilled person that the realization method of current mirror is without being limited thereto, any realization shape appropriate in the prior art can also be
Formula.In addition, though concrete type (the PMOS crystalline substances of each MOS transistor are given in embodiment shown in Fig. 3 using standard diagram
Body pipe and NMOS transistor), then it will be appreciated by those skilled in the art that the type of these MOS transistors can be according to reality
Replaced, it is only necessary to correspondingly it is controlled signal carry out it is logically high, it is low level switching similar work(can be realized
Can, therefore the concrete type of each MOS transistor is not limited to shown in Fig. 3.
Second embodiment
With reference to figure 5, Fig. 5 shows the electrical block diagram of the power charging circuit 200 of second embodiment.Second implements
The power charging circuit 200 and first embodiment of example are essentially identical, and difference lies in be omitted current limliting in current-limiting control circuit 201
Delay circuit, level displacement circuit 203 directly to limit detection circuit 202 generate the first Current limited Control signal ILIMIT1 into
Line level displacement and obtain the second Current limited Control signal ILIMIT2.
With reference to figure 6, Fig. 6 shows the particular circuit configurations signal of the current-limiting control circuit 201 of second embodiment of the invention
Figure.It is essentially identical with the structure of first embodiment in Fig. 3, the difference is that eliminating current limliting delay circuit and current limliting sluggishness
Description is not repeated herein in circuit.In addition, in figure 6, phase inverter 2032 is carried out to the first Current limited Control signal ILIMIT1
Reverse phase, then the first Current limited Control signal ILIMIT1 and its inverted signal transmission to level shift execution module 2033 carry out electricity
Prosposition is moved to generate the second Current limited Control signal ILIMIT2.
In a second embodiment, in the first stage, limit detection circuit 202 detects that output voltage VO UT is zero, current limliting
The cut-off current that output circuit 204 generates is zero, only flows through charging electricity of the electric current as output capacitance C0 of current-limiting resistance R0
Stream, first stage start to charge up process for output capacitance C0's；In second stage, limit detection circuit 202 detects input electricity
The voltage difference of pressure VIN and output voltage VO UT is more than to be judged a little into Current limited Control, then the first Current limited Control signal ILIMIT1 is
Logic high is logic low by the second Current limited Control signal ILIMIT2 that level displacement circuit 203 generates, then controls
The cut-off current that current limliting output circuit 204 processed generates gradually rises up to cut-off current, cut-off current and the electricity for flowing through current-limiting resistance R0
The charging current as output capacitance C0, second stage are the quickening charging process of output capacitance C0 to stream together；In the phase III,
Limit detection circuit 202 detects that the voltage difference of input voltage VIN and output voltage VO UT are less than and exits Current limited Control and judge a little,
Then the first Current limited Control signal ILIMIT1 is logic low, is believed by the second Current limited Control that level displacement circuit 203 generates
Number ILIMIT2 is logic high, then controls the cut-off current of the generation of current limliting output circuit 204 and flow through the electricity of current-limiting resistance R0
Stream is common to provide load current for load, and the phase III is that output capacitance C0 completes the process after charging.
With reference to figure 7, Fig. 7 shows the working signal waveform of physical circuit shown in Fig. 6.The signal for including in Fig. 7 has：Input
Voltage VIN, output voltage VO UT, internal power source voltage LVDD, the first Current limited Control signal ILIMIT1, time delayed signal IDELAY,
Second Current limited Control signal ILIMIT2, the first bias current IB1, the second bias current IB2 and cut-off current IOUT.
In conjunction with Fig. 5 to Fig. 7, the operation principle summary of the power charging circuit comprising Current limited Control of second embodiment is such as
Under：
Input voltage VIN is V1 when initial, and output voltage VO UT is 0, then electricity of the input voltage VIN with output voltage VO UT
Pressure difference is more than the Current limited Control determined by resistance R1 in limit detection circuit 202 and resistance R2 and judges point (V1-V2), then enters limit
Flow control；And the second Current limited Control signal ILIMIT2 is also 0, i.e. low level, then by the second Current limited Control signal ILIMIT2 controls
MOS transistor (such as PMOS transistor) M20 of system is connected, and the second bias current IB2 passes through MOS transistor pipe M21 and M22 shape
At current mirror generate the cut-off current IOUT from the input terminal of current-limiting control circuit 201 to output end, and flow through current-limiting resistance
The electric current of R0 starts current-limiting charge together as the charging current of output capacitance C0.But due to output voltage VO UT at this time
It is 0, MOS transistor (such as NMOS transistor) M4 shutdowns, then internal power source voltage LVDD is 0, such first bias current
IB1, the second bias current IB2 and cut-off current IOUT are also 0, then the charging current of output capacitance C0 only flows through current limliting
The electric current of resistance R0, but since the resistance value of current-limiting resistance R0 is larger so that charging current is smaller, then output voltage VO UT is slow
Rise；
It is the first stage above, i.e. output capacitance C0's starts to charge up process.
When output voltage VO UT rises to the cut-in voltage VGS4 of MOS transistor (such as NMOS transistor) M4, MOS is brilliant
The M4 conductings of body pipe, then internal power source voltage LVDD starts to increase, and rises as output voltage VO UT rises, then the first biasing
Electric current IB1, the second bias current IB2 and cut-off current IOUT also begin to increase, then the charging current of output capacitance C0 also with
Increase, then output voltage VO UT starts to accelerate to rise；
It is more than at this time by the electricity in limit detection circuit 202 with the voltage difference of output voltage VO UT due to input voltage VIN
The Current limited Control that resistance R1 and resistance R2 is determined judges point (V1-V2), then the voltage of the comparison signal ILIMIT0 after detecting relatively compared with
Small, then MOS transistor (such as NMOS transistor) M9 is turned off, the first Current limited Control signal ILIMIT1 is high level (its voltage
Equal to internal power source voltage LVDD), reversed output is low level (voltage 0), then MOS crystal in level displacement circuit 203
Manage (such as NMOS transistor) M16 conductings, MOS transistor (such as NMOS transistor) M15 shutdowns, such second Current limited Control letter
Number ILIMIT2 is pulled down by MOS transistor M16, is still low level (voltage 0), will continue to control MOS transistor (such as PMOS
Transistor) M20 conductings, the second bias current IB2 continues through the current mirror that MOS transistor M21 and M22 is formed and generates from current limliting
The input terminal of control circuit 201 flows to charging currents of the cut-off current IOUT of output end as output capacitance C0, that is, continue into
Row current-limiting charge；
When output voltage VO UT rises to the clamping voltag VZ1 of clamp diode D1, internal power source voltage LVDD is also
Reach clamping voltag LVDDclamp, then the first bias current IB1, the second bias current I2 and cut-off current IOUT also reach respectively
To cut-off current IB1limit, IB2limit, IOUTlimit, then the charging current of output capacitance C0 also reaches cut-off current, then it is defeated
It is also that fixed speed rises to go out voltage VOUT according to prestissimo；
Second stage above, i.e. the quickening charging process of output capacitance C0.It should be noted that if in cut-off current
IOUT rises to before cut-off current IOUTlimit, has completed to charge, has just been directly entered the phase III；If in cut-off current
IOUT rises to after cut-off current IOUTlimit, does not complete charging also, that cut-off current IOUT keeps cut-off current IOUTlimit
Continue to charge, the phase III is entered after completing to charge.
When output voltage VO UT rises to comparison point V2, the voltage difference of the voltage and input voltage VIN is less than by current limliting
The resistance R1 and resistance R2 current limlitings determined judge point (V1-V2) in detection circuit 202, then exit Current limited Control, and detection obtains
Comparison signal ILIMIT0 be more than MOS transistor (such as NMOS transistor) M9 cut-in voltage VGS9, then MOS transistor
M9 is connected, and the first Current limited Control signal ILIMIT1 is low level by high level (its voltage is internal electric source LVDDclamp) saltus step
(its voltage is 0), reversed output is that (its voltage is internal electric source to high level by low level (its voltage is 0) saltus step
LVDDclamp), then in level displacement circuit 203 MOS transistor (such as NMOS transistor) M16 shutdown, MOS transistor (such as
NMOS transistor) M15 conductings, such second Current limited Control signal ILIMIT2 is by MOS transistor (such as PMOS transistor) M18
Pull-up, is high level (its voltage is output voltage VO UT) by low level (its voltage is 0) saltus step, then by the second Current limited Control
MOS transistor (such as PMOS transistor) M20 shutdowns of signal ILIMIT2 controls, from the output end stream of current-limiting control circuit 201
The current mirror no longer formed to the cut-off current IOUT of output end by MOS transistor M21 and M22 by the second bias current IB2
Mirror image obtains, but by input voltage VIN by the voltage after resistance R6 and resistance R7 partial pressures control MOS transistor (such as
PMOS transistor) gate source voltage of M22 obtains IOUTmax, and the second bias current IB2 is also no longer by MOS transistor M5 and M19
The current mirror mirror image of formation obtains, but obtains end value IB2end by input voltage VIN divided by resistance R6 and resistance R7；This
When, cut-off current IOUT is together with the electric current for flowing through current-limiting resistance R0, in addition to the charging current as output capacitance C0, also conduct
The load current Iload to be powered by output voltage VO UT；
When output voltage VO UT is stepped up to the voltage V1 of input voltage VIN, internal power source voltage LVDD maintains pincers
Position voltage LVDDclamp, output voltage VO UT and input voltage VIN detection relatively after comparison signal ILIMIT0 voltage on
It rises to voltage value V3 and maintains, the first Current limited Control signal ILIMIT1 maintains low level (voltage 0), the second Current limited Control letter
Number ILIMIT2 maintains high level (voltage is output voltage VO UT), and the first bias current IB1 maintains cut-off current IB1limit, the
Two bias current I2 maintain end value IB2end, the cut-off current IOUT of output to maintain IOUTmax, and due to output capacitance C0's
Charging current is gradually decreased to 0, that is, completes charging, then cut-off current IOUT is all converted into the electric current for flowing through current-limiting resistance R0
Load current Iload；
It is the phase III above, i.e. the completion charging process of output capacitance C0 flows through the electric current and current limliting of current-limiting resistance R0
Electric current IOUT provides load current Iload for load jointly.It should be noted that, although cut-off current IOUT shown in Fig. 7 is
Maximum value IOUTmax, but this is merely representative of cut-off current IOUT with the ability more than cut-off current IOUTlimit, according to load
Actual demand, cut-off current IOUT can be more than in the phase III, be less than or equal to cut-off current IOUTlimit, and it is maximum
Value is IOUTmax, that is, possible net capability.
3rd embodiment
With reference to figure 8, Fig. 8 shows the electrical block diagram of the power charging circuit 200 of 3rd embodiment.Third is implemented
The power charging circuit 200 and first embodiment of example are essentially identical, and difference lies in the limit detection circuits 202 of 3rd embodiment
In current limliting hysteresis circuitry is omitted, this can find out from particular circuit configurations shown in Fig. 9.
The associated description of first embodiment is referred to about Fig. 8 and circuit structure shown in Fig. 9, which is not described herein again.
With reference to figure 10, Figure 10 shows the working signal waveform of physical circuit shown in Fig. 9.The signal for including in Figure 10 has：
Input voltage VIN, output voltage VO UT, internal power source voltage LVDD, the first Current limited Control signal ILIMIT1, time delayed signal
IDELAY, the second Current limited Control signal ILIMIT2, the first bias current IB1, the second bias current IB2 and cut-off current
IOUT。
In conjunction with Fig. 8 to Figure 10, the operation principle summary of the power charging circuit comprising Current limited Control of 3rd embodiment is such as
Under：
Input voltage VIN is V1 when initial, and output voltage VO UT is 0, then electricity of the input voltage VIN with output voltage VO UT
Pressure difference is more than the Current limited Control determined by the resistance R1 and resistance R2 in limit detection circuit 202 and judges point (V1-V2), then enters
Current limited Control；And the second Current limited Control signal ILIMIT2 is also 0, i.e. low level, then by the second Current limited Control signal ILIMIT2
MOS transistor (such as PMOS transistor) M20 of control is connected, and the second bias current IB2 passes through MOS transistor M21 and M22 shape
At current mirror generate and flow to from the input terminal of current-limiting control circuit 201 the cut-off current IOUT of output end, and flow through current limliting electricity
The electric current of R0 is hindered together as the charging current of output capacitance C0, that is, starts current-limiting charge；But due to output voltage at this time
VOUT is 0, MOS transistor (such as NMOS transistor) M4 shutdowns, then internal power source voltage LVDD is 0, such first biased electrical
It is all 0 to flow IB1, the second bias current IB2 and cut-off current IOUT also, then the charging current of output capacitance C0 only flows through limit
The electric current of leakage resistance R0, but since the resistance value of current-limiting resistance R0 is larger, charging current is smaller, then output voltage VO UT it is slow on
It rises；
It is the first stage above, i.e. output capacitance C0's starts to charge up process.
When output voltage VO UT rises to the cut-in voltage VGS4 of MOS transistor (such as NMOS transistor) M4, MOS is brilliant
The M4 conductings of body pipe, then internal power source voltage LVDD starts to increase, and rises as output voltage VO UT rises, then the first biasing
Electric current IB1, the second bias current IB2 and cut-off current IOUT also begin to increase, then the charging current of output capacitance C0 also with
Increase, then output voltage VO UT starts to accelerate to rise；
At this time input voltage VIN with output voltage VO UT voltage difference be more than by resistance R1 in limit detection circuit 202 with
The Current limited Control that resistance R2 is determined judges point (V1-V2), then the voltage of the comparison signal ILIMIT0 after detecting relatively is smaller, that
MOS transistor (such as NMOS transistor) M9 is turned off, and the first Current limited Control signal ILIMIT1 is that (its voltage is interior to high level
Portion supply voltage LVDD), then in current limliting delay circuit 205 MOS transistor (such as PMOS transistor) M11 shutdown, MOS crystal
(such as NMOS transistor) M12 conductings are managed, capacitance C1 is discharged by MOS transistor M12, since discharge current is unrestricted, delay
Time is very short, can be ignored, that is, the time delayed signal IDELAY exported is low level (voltage 0), then in level displacement circuit 203
MOS transistor (such as NMOS transistor) M15 shutdowns, MOS transistor (such as NMOS transistor) M16 conductings, such second limit
Flow control signals ILIMIT2 is pulled down by MOS transistor (such as NMOS transistor) M16, is still low level (voltage 0), will be after
Continuous control MOS transistor (such as PMOS transistor) M20 conductings, the second bias current IB2 continue through MOS transistor M21 and
The current mirror that M22 is formed generates from the input terminal of current-limiting control circuit and flow to the output current IO UT of output end as output capacitance
The charging current of C0, that is, continue current-limiting charge；
When output voltage VO UT rises to the clamping voltag VZ1 of clamp diode D1, internal power source voltage LVDD is also
Reach clamping voltag LVDDclamp, then the first bias current IB1, the second bias current I2 and cut-off current IOUT also reach respectively
To cut-off current IB1limit, IB2limit, IOUTlimit, then the charging current of output capacitance C0 also reaches cut-off current, then it is defeated
Go out voltage VOUT according to prestissimo and fixed speed to rise；
Second stage above, i.e. the quickening charging process of output capacitance C0.It should be noted that if in cut-off current
IOUT rises to before cut-off current IOUTlimit, has completed to charge, has just been directly entered the phase III；If in cut-off current
IOUT rises to after cut-off current IOUTlimit, does not complete charging also, that cut-off current IOUT keeps cut-off current IOUTlimit
Continue to charge, the phase III is entered after completing to charge.
When output voltage VO UT rises to comparison point V2, which is less than with the voltage difference of input voltage VIN by current limliting
The resistance R1 and resistance R2 current limlitings determined judge point (V1-V2) in detection circuit 202, then exit Current limited Control, and detection is compared
Output voltage ILIMIT0 afterwards is more than the cut-in voltage VGS9 of MOS transistor (such as NMOS transistor) M9, then MOS crystal
Pipe M9 conductings, the first Current limited Control signal ILIMIT1 are low electricity by high level (its voltage is internal electric source LVDDclamp) saltus step
(its voltage is 0) is put down, then MOS transistor (such as PMOS transistor) M11 conductings in current limliting delay circuit 205, MOS transistor
(such as NMOS transistor) M12 is turned off, and capacitance C1 is charged by MOS transistor M11, since charging current is by the first biased electrical
The electric current limit that the current mirror of current mirror, MOS transistor M7 and M10 formation that stream IB1 is formed by MOS transistor M5 and M6 obtains
System, produces delay time Td, that is, the time delayed signal IDELAY exported is jumped after Td time delays by low level (voltage 0)
Become high level (its voltage be internal electric source LVDDclamp), then (such as NMOS is brilliant for MOS transistor in level displacement circuit 203
Body pipe) M15 is just connected after also passing through Td time delays, MOS transistor (such as NMOS transistor) M16 is after Td time delays
Shutdown, such second Current limited Control signal ILIMIT2 is after Td time delays by MOS transistor (such as PMOS transistor)
M18 is pulled up, and is high level (its voltage is output voltage VO UT), such output capacitance C0 by low level (its voltage is 0) saltus step
Charging current continue to cut-off current, then output voltage VO UT also always according to prestissimo, be also fixed speed rise, this
Sample can accelerate the output voltage VO UT rates of climb, can also stabilize the output voltage VOUT；And as the second Current limited Control signal ILIMIT2
After saltus step, then by the MOS transistor M20 shutdowns of the second Current limited Control signal ILIMIT2 controls, from current-limiting control circuit 201
Input terminal flow to the cut-off current IOUT of output end MOS transistor M21 and M22 shape no longer passed through by the second bias current IB2
At current mirror mirror image obtain, but by input voltage VIN pass through the branch pressure voltage of resistance R6 and resistance R7 control MOS transistor
The gate source voltage of (such as PMOS transistor) M22 obtains IOUTmax, and the second bias current IB2 is also no longer by MOS transistor M5
It is obtained with the M19 current mirror mirror images formed, but end value is obtained by input voltage VIN divided by resistance R6 and resistance R7
IB2end；At this point, cut-off current IOUT is together with the electric current for flowing through current-limiting resistance R0, in addition to the charging electricity as output capacitance C0
Stream, also as the load current Iload to be powered by output voltage VO UT；
When output voltage VO UT gradually rises it is consistent with input voltage VIN when, internal power source voltage LVDD maintains clamp electricity
LVDDclamp, output voltage VO UT and input voltage VIN is pressed to detect the comparison signal ILIMIT0 raised voltages obtained more afterwards
Value V3 is simultaneously maintained, and the first Current limited Control signal ILIMIT1 maintains low level (voltage 0), time delayed signal IDELAY to maintain high electricity
Flat (voltage is internal electric source LVDDclamp), the second Current limited Control signal ILIMIT2 maintains high level, and (voltage is output voltage
VOUT), the first bias current IB1 maintains cut-off current IB1limit, the second bias current I2 to maintain end value IB2end, output electricity
It flows IOUT and maintains IOUTmax, and since the charging current of output capacitance C0 is gradually decreased to 0, that is, complete charging, then output current
IOUT all switchs to load current Iload with the electric current for flowing through current-limiting resistance R0；
It is the phase III above, i.e. the completion charging process of output capacitance C0 flows through the electric current and current limliting of current-limiting resistance R0
Electric current IOUT provides load current Iload for load jointly.It should be noted that, although cut-off current IOUT shown in Figure 10 is
Maximum value IOUTmax, but this is merely representative of cut-off current IOUT with the ability more than cut-off current IOUTlimit, according to load
Actual demand, cut-off current IOUT can be more than in the phase III, be less than or equal to cut-off current IOUTlimit, and it is maximum
Value is IOUTmax, that is, possible net capability.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.Cause
This, every content without departing from technical solution of the present invention is only made to the above embodiment according to the technical essence of the invention
Any simple modification, equivalent transformation, are still within the scope of the technical scheme of the invention.
Claims (22)
1. a kind of power charging circuit, including：
Current-limiting resistance, first end connect input voltage anode；
Output capacitance, first end connect the second end of the current-limiting resistance, and second end connection input voltage negative terminal is simultaneously grounded,
Voltage between the input voltage anode and input voltage negative terminal is input voltage, and the voltage at the output capacitance both ends is defeated
Go out voltage；
It is characterized in that, further including：
Current-limiting control circuit, input terminal connect the input voltage anode, and output end connects the first of the output capacitance
End, the output end output current limiting electric current of the current-limiting control circuit, the cut-off current is to the output capacitance charging complete
It is limited to less than before equal to preset cut-off current, the cut-off current is no longer limited after charging complete.
2. power charging circuit according to claim 1, which is characterized in that the power charging circuit is to output electricity
The charging process of appearance includes the first stage to connect successively, second stage and phase III, wherein
The first stage starts to charge up process for the output capacitance, and the cut-off current is zero in the first stage, only
It flows through the electric current of the current-limiting resistance and provides charging current for the output capacitance；
The second stage is the quickening charging process of the output capacitance, and the cut-off current gradually rises up in second stage
The cut-off current, the electric current and the cut-off current for flowing through the current-limiting resistance provide charging electricity for the output capacitance jointly
Stream；
The phase III is that the output capacitance completes the process after charging, flows through the electric current of the current-limiting resistance and the limit
Galvanic electricity stream provides load current for load jointly.
3. power charging circuit according to claim 2, which is characterized in that in the second stage, if the limit
Galvanic electricity stream rises to before the cut-off current, and the output capacitance has been completed to charge, then is directly entered the phase III；
In the second stage, if the cut-off current rises to after the cut-off current, the output capacitance does not complete charging, then
The cut-off current remains the cut-off current, until entering the phase III after completing charging.
4. power charging circuit according to claim 1, which is characterized in that the current-limiting control circuit includes：
Limit detection circuit is detected the voltage difference of the input voltage and output voltage, first is generated after relatively
Current limited Control signal；
Level displacement circuit directly or indirectly carries out level shift to generate the second current limliting to the first Current limited Control signal
Control signal；
Current limliting output circuit, it is in parallel with the current-limiting resistance, output institute is generated under the control of the second Current limited Control signal
State cut-off current.
5. power charging circuit according to claim 4, which is characterized in that the power charging circuit is to output electricity
The charging process of appearance includes the first stage to connect successively, second stage and phase III, wherein
In the first stage, the limit detection circuit detects that the output voltage is zero, the current limliting output circuit production
Raw cut-off current is zero, only flows through charging current of the electric current of the current-limiting resistance as the output capacitance, described
One stage started to charge up process for the output capacitance；
In the second stage, the limit detection circuit detect the voltage difference of the input voltage and output voltage be more than into
Enter Current limited Control to judge a little, then the first Current limited Control signal is logic high, the generated by level displacement circuit
Two Current limited Control signals are logic low, then control the cut-off current that the current limliting output circuit generates gradually rise up to it is described
Cut-off current, the cut-off current and flows through the electric current of the current-limiting resistance together as the charging current of output capacitance, and described the
Two-stage is the quickening charging process of the output capacitance；
In the phase III, the limit detection circuit detects that the voltage difference of the input voltage and output voltage is less than and moves back
Go out Current limited Control to judge a little, then the first Current limited Control signal is logic low, is generated by the level displacement circuit
The second Current limited Control signal be logic high, then control current limliting output circuit generation cut-off current and flow through the current limliting
The electric current of resistance provides load current for load jointly, and the phase III is that the output capacitance completes the process after charging.
6. power charging circuit according to claim 5, which is characterized in that in the second stage, if the limit
Galvanic electricity stream rises to before the cut-off current, and the output capacitance has been completed to charge, then is directly entered the phase III；
In the second stage, if the cut-off current rises to after the cut-off current, the output capacitance does not complete charging, then
The cut-off current remains the cut-off current, until entering the phase III after completing charging.
7. power charging circuit according to claim 4, which is characterized in that the current-limiting control circuit further includes：Current limliting
Delay circuit is delayed to generate time delayed signal to the first Current limited Control signal, and the level displacement circuit is to the delay
Signal carries out level shift to obtain the second Current limited Control signal.
8. power charging circuit according to claim 7, which is characterized in that the power charging circuit is to output electricity
The charging process of appearance includes the first stage to connect successively, second stage and phase III, wherein
In the first stage, the limit detection circuit detects that the output voltage is zero, the current limliting output circuit production
Raw cut-off current is zero, only flows through charging current of the electric current of the current-limiting resistance as the output capacitance, described
One stage started to charge up process for the output capacitance；
In the second stage, the limit detection circuit detect the voltage difference of the input voltage and output voltage be more than into
Enter Current limited Control to judge a little, then the first Current limited Control signal is logic high, is generated by the current limliting delay circuit
Time delayed signal be logic low, using the level displacement circuit generate the second Current limited Control signal be logic low electricity
It is flat, then it controls the cut-off current that the current limliting output circuit generates and gradually rises up to the cut-off current, the cut-off current and stream
The electric current of the current-limiting resistance charging current as the output capacitance together is crossed, the second stage is the output capacitance
Quickening charging process；
In the phase III, the limit detection circuit detects that the voltage difference of the input voltage and output voltage is less than and moves back
Go out Current limited Control to judge a little, then the first Current limited Control signal is logic low, is generated by the current limliting delay circuit
Time delayed signal be logic high, using the level displacement circuit generate the second Current limited Control signal be logically high electricity
It is flat, then it controls the cut-off current that the current limliting output circuit generates and is provided jointly for load with the electric current for flowing through the current-limiting resistance
Load current, the phase III are that the output capacitance completes the process after charging.
9. power charging circuit according to claim 8, which is characterized in that in the second stage, if the limit
Galvanic electricity stream rises to before the cut-off current, and the output capacitance has been completed to charge, then is directly entered the phase III；
In the second stage, if the cut-off current rises to after the cut-off current, the output capacitance does not complete charging, then
The cut-off current remains the cut-off current, until entering the phase III after completing charging.
10. the power charging circuit according to any one of claim 7 to 9, which is characterized in that the limit detection circuit
Including：
Internal power source voltage generative circuit receives the output voltage and is converted into internal power source voltage；
The internal power source voltage is converted to the first bias current by the first bias current generative circuit；
First voltage turns current circuit, and the input voltage is converted to the first electric current；
Second voltage turns current circuit, and the output voltage is converted to the second electric current；
First current mirror, input terminal receive first electric current, and output end receives second electric current, the current mirror pair
First electric current and the second electric current are compared to generate comparison signal；
9th MOS transistor, first bias current are transmitted to described after the second current mirror and third current mirror mirror image
The grid of the drain electrode of 9th MOS transistor, the 9th MOS transistor receives the comparison signal, the 9th MOS transistor
Source electrode ground connection, the drain electrode of the 9th MOS transistor exports the first Current limited Control signal.
11. power charging circuit according to claim 10, which is characterized in that the first voltage turns current circuit packet
It includes：
First resistor, first end receive the input voltage, and second end exports first electric current.
12. power charging circuit according to claim 10, which is characterized in that the second voltage turns current circuit packet
It includes：
Second resistance, first end receive the output voltage, and second end exports second electric current.
13. power charging circuit according to claim 10, which is characterized in that the second voltage turns current circuit packet
It includes：
Second resistance, first end receive the output voltage；
Current limliting hysteresis circuitry, input terminal connect the second end of the second resistance, and output end exports second electric current, institute
It states current limliting hysteresis circuitry and adjusts second electric current under the control of the second Current limited Control signal.
14. power charging circuit according to claim 13, which is characterized in that the current limliting hysteresis circuitry includes：
3rd resistor, first end connect the second end of the second resistance, and second end connects the defeated of first current mirror
Outlet；
Third MOS transistor, drain electrode connect the first end of the 3rd resistor, and source electrode connects the second of the 3rd resistor
End, grid receive the second Current limited Control signal.
15. power charging circuit according to claim 10, which is characterized in that the internal power source voltage generative circuit packet
It includes：
4th resistance, first end receive the output voltage；
First clamp diode, cathode connect the second end of the 4th resistance, plus earth；
4th MOS transistor, drain electrode receive the output voltage, and grid connects the second end of the 4th resistance, source
Pole exports the internal power source voltage.
16. power charging circuit according to claim 15, which is characterized in that the first bias current generative circuit packet
It includes：
5th resistance, first end connect the source electrode of the 4th MOS transistor, and second end exports first biased electrical
Stream.
17. power charging circuit according to claim 10, which is characterized in that the current limliting delay circuit includes：
Charge-discharge control circuit, first bias current are described via being transmitted to after the second current mirror and the 4th current mirror mirror image
The control terminal of the input terminal of charge-discharge control circuit, the charge-discharge control circuit receives the first Current limited Control signal；
Capacitance, first end connect the output end of the charge-discharge control circuit, second end ground connection, the charge and discharge control electricity
Road is charged or is discharged under the control of the first Current limited Control signal, to the capacitance, and the of the capacitance
One end exports the time delayed signal.
18. power charging circuit according to claim 17, which is characterized in that the charge-discharge control circuit includes：
11st MOS transistor, input terminal of the source electrode as the charge-discharge control circuit, grid receive first limit
Flow control signals, drain electrode connect the first end of the capacitance；
12nd MOS transistor, drain electrode connect the first end of the capacitance, and grid receives the first Current limited Control letter
Number, source electrode ground connection.
19. power charging circuit according to claim 7, which is characterized in that the level displacement circuit includes：
Phase inverter carries out reverse phase to the time delayed signal；
15th MOS transistor, grid receive the time delayed signal, source electrode ground connection；
16th MOS transistor, grid connect the output end of the phase inverter to receive the inversion signal of the time delayed signal,
Its source electrode is grounded；
17th MOS transistor, source electrode receive the output voltage, and drain electrode connects the leakage of the 15th MOS transistor
Pole；
18th MOS transistor, source electrode receive the output voltage, and drain electrode connects the grid of the 17th MOS transistor
The drain electrode of pole and the 16th MOS transistor, grid connect the drain electrode of the 17th MOS transistor；
Wherein, the drain electrode of the 16th MOS transistor and the 18th MOS transistor exports the second Current limited Control signal.
20. power charging circuit according to claim 4, which is characterized in that the level displacement circuit includes：
Phase inverter carries out reverse phase to the first Current limited Control signal；
15th MOS transistor, grid connect the output end of the phase inverter to receive the first Current limited Control signal
Inversion signal, source electrode ground connection；
16th MOS transistor, grid receive the first Current limited Control signal, source electrode ground connection；
17th MOS transistor, source electrode receive the output voltage, and drain electrode connects the leakage of the 15th MOS transistor
Pole；
18th MOS transistor, source electrode receive the output voltage, and drain electrode connects the grid of the 17th MOS transistor
The drain electrode of pole and the 16th MOS transistor, grid connect the drain electrode of the 17th MOS transistor；
Wherein, the drain electrode of the 16th MOS transistor and the 18th MOS transistor exports the second Current limited Control signal.
21. power charging circuit according to claim 10, which is characterized in that the current limliting output circuit includes：
5th current mirror carries out mirror image to obtain the second bias current to first bias current；
20th MOS transistor, grid receive the second Current limited Control signal；
7th resistance, first end connect the drain electrode of the 20th MOS transistor, and second end connects the 5th current mirror
Output end；
21st MOS transistor, source electrode connect the input terminal of the current-limiting control circuit, drain electrode connection the described 20th
The source electrode of MOS transistor, grid connect the drain electrode of the 20th MOS transistor；
22nd MOS transistor, source electrode connect the input terminal of the current-limiting control circuit, and drain electrode connects the current limliting control
The output end of circuit processed, grid connect the grid of the 21st MOS transistor, flow through the 22nd MOS crystal
The electric current of pipe is the cut-off current；
6th resistance, first end connect the input terminal of the current-limiting control circuit, and second end connects the 21st MOS
The first end of the grid of transistor and the 7th resistance；
Second clamp diode, cathode connect the input terminal of the current-limiting control circuit, anode connection the described 22nd
The grid of MOS transistor.
22. power charging circuit according to claim 21, which is characterized in that when the 20th MOS transistor is connected
When, the 21st MOS transistor and the 22nd MOS transistor form current mirror, and second bias current is via this
The cut-off current is obtained after current mirror mirror image, which is used as described defeated together with the electric current for flowing through the current-limiting resistance
Go out the charging current of capacitance；When the 20th MOS transistor turns off, the input voltage passes through the 6th resistance and the 7th
Resistance generate branch pressure voltage as the 22nd MOS transistor gate source voltage to obtain the cut-off current, the limit
Galvanic electricity stream and the electric current of the current-limiting resistance is flowed through together as the load current of supplying power for outside.
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| CN201510727461.3A CN105186636B (en) | 2015-10-30 | 2015-10-30 | power charging circuit |
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| CN108155903B (en) * | 2017-11-22 | 2020-10-09 | 中山大学 | High-speed high-voltage level conversion circuit applied to GaN grid drive |
| CN110134176B (en) * | 2018-09-05 | 2024-05-28 | 江西联智集成电路有限公司 | LDO circuit and wireless charging system |
| CN110932531A (en) * | 2019-11-26 | 2020-03-27 | 上海军陶电源设备有限公司 | Drive circuit and power supply control circuit |
| CN111884293B (en) * | 2020-07-31 | 2021-03-23 | 珠海智融科技有限公司 | Two-way dual-port power control system, mobile power supply and power adapter |
| CN114977146A (en) * | 2022-01-28 | 2022-08-30 | 青岛经济技术开发区海尔热水器有限公司 | a protective device |
| CN115719993B (en) * | 2023-01-10 | 2023-05-02 | 深圳市思远半导体有限公司 | Charging circuit, power supply device, charged device, charging system and chip |
| CN117895775B (en) * | 2024-03-14 | 2024-10-25 | 成都市易冲半导体有限公司 | Quick-charging chip and soft start method thereof |
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| CN103095127A (en) * | 2013-01-22 | 2013-05-08 | 上海艾为电子技术有限公司 | Charge pump circuit and electronic equipment |
| CN104142701B (en) * | 2013-05-06 | 2016-08-24 | 意法半导体研发(深圳)有限公司 | Current-limiting circuit |
| CN203708099U (en) * | 2013-12-30 | 2014-07-09 | 上海五零盛同信息科技有限公司 | Current-limiting high-voltage startup circuit for switching power supply with ultra-wide input voltage range |
| CN103872883B (en) * | 2014-04-15 | 2016-03-02 | 武汉中原电子集团有限公司 | A kind of pressure-limit current-limit control device of flyback power supply |
| CN104536507B (en) * | 2014-12-05 | 2016-08-24 | 芯原微电子(上海)有限公司 | Returning type current limiting circuit and there is the linear stable of this returning type current limiting circuit |
| CN205081517U (en) * | 2015-10-30 | 2016-03-09 | 杭州士兰微电子股份有限公司 | Power charging circuit |
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