CN114816817B

CN114816817B - Fault reporting output integrated circuit

Info

Publication number: CN114816817B
Application number: CN202210389353.XA
Authority: CN
Inventors: 李秉纬; 张焕云
Original assignee: Shenzhen Simi Semiconductor Co ltd
Current assignee: Shenzhen Simi Semiconductor Co ltd
Priority date: 2022-04-13
Filing date: 2022-04-13
Publication date: 2024-10-22
Anticipated expiration: 2042-04-13
Also published as: CN114816817A

Abstract

The embodiment of the application belongs to the technical field of integrated circuits and relates to a fault error-reporting output integrated circuit, which comprises a signal input circuit, an interlocking circuit, a high-voltage driving circuit, a low-voltage driving circuit, a fault detection circuit, an error-reporting circuit and a fault output circuit, wherein the signal input circuit is connected to the interlocking circuit, and the interlocking circuit is respectively connected with the high-voltage driving circuit and the low-voltage driving circuit and is used for controlling the output end of the interlocking circuit to output a low-level signal; the fault detection circuit is connected to the fault reporting circuit and is used for detecting faults, generating fault feedback signals and sending the fault feedback signals to the fault reporting circuit; the fault reporting circuit is used for generating a fault signal according to the fault feedback signal and sending the fault signal to the fault output circuit, and simultaneously sending an enabling signal to the high-voltage driving circuit and the low-voltage driving circuit; the fault output circuit is used for determining a fault output port according to the fault type of the fault feedback signal and outputting a fault signal. The technical scheme provided by the application can clearly output the fault type and shorten the time for positioning and analyzing the fault.

Description

Fault reporting output integrated circuit

Technical Field

The application relates to the technical field of high-voltage integrated circuits, in particular to a fault error-reporting output integrated circuit.

Background

Under the traction of emerging industries such as smart grids, mobile communication, and new energy automobiles, power electronics application systems require further improvements in efficiency, miniaturization, and increased functionality of the systems, particularly requiring the system to be equipped with micro-inverters that trade-off between size, quality, power, and efficiency, such as server power management, battery chargers, and solar farm. To accommodate some high voltage, high temperature, high efficiency, and high power density applications, high voltage integrated circuits (High Voltage Integrated Circuit, HVICs) have been developed.

HVIC is a high voltage integrated circuit product that converts MCU (Microcontroller Unit, micro control unit) signals into drive IGBT (Insulated Gate Bipolar Transistor ), MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide semiconductor field effect transistor) signals. On one hand, the HVIC receives a control signal of the MCU (Microcontroller Unit, a micro control unit) to drive the subsequent IGBT or MOSFET to work, and on the other hand, sends a fault state detection signal of the system back to the MCU, which is a key chip inside the intelligent power module (INTELLIGENT POWER MODULE, IPM).

At present, when the HVIC is applied, under-voltage protection, over-current protection and over-temperature protection are excited, two paths of fault signals are output through an internal fault reporting circuit, one path of control logic input port is invalid, the other path of control logic input port outputs the three types of fault signals to an external MCU, and the MCU detects the fault signals to report faults. Because the fault signal is output only through one path of signal, when the HVIC is triggered to fail, the specific fault type cannot be judged, a great deal of time is required for positioning and analyzing the specific fault, and the analysis and positioning efficiency is low.

Disclosure of Invention

The embodiment of the application aims to solve the technical problems that in the related art, only one path of fault signal is output, so that when a high-voltage integrated circuit is triggered to fail to judge the specific type of the fault, and a great amount of time is required for positioning and analyzing the fault.

In order to solve the above technical problems, an embodiment of the present application provides a fault error-reporting output integrated circuit, which adopts the following technical scheme:

The fault detection circuit comprises a signal input circuit, an interlocking circuit, a high-voltage driving circuit, a low-voltage driving circuit, a fault detection circuit, an error reporting circuit and a fault output circuit which are in one-to-one correspondence with fault types;

The signal input circuit is connected to the interlocking circuit and is used for receiving a driving signal;

The interlocking circuit is respectively connected with the high-voltage driving circuit and the low-voltage driving circuit, and is used for determining whether to turn off the driving signal according to the level of the driving signal and controlling the output ends of the high-voltage driving circuit and the low-voltage driving circuit to output a low-level signal;

the high-voltage driving circuit is connected with the error reporting circuit and is used for receiving the enabling signal transmitted by the error reporting circuit and sending the enabling signal to the interlocking circuit;

The low-voltage driving circuit is connected with the error reporting circuit and is used for receiving the enabling signal transmitted by the error reporting circuit and sending the enabling signal to the interlocking circuit;

the fault detection circuit is connected to the fault reporting circuit and is used for detecting faults, generating fault feedback signals according to the faults and sending the fault feedback signals to the fault reporting circuit;

The fault reporting circuit is respectively connected with the high-voltage driving circuit, the low-voltage driving circuit and the fault output circuit and is used for generating a fault signal according to the fault feedback signal and sending the fault signal to the fault output circuit and simultaneously sending the enabling signal to the high-voltage driving circuit and the low-voltage driving circuit;

the fault output circuit is used for determining a fault output port according to the fault type of the fault feedback signal and transmitting a fault signal corresponding to the fault type to the fault output port.

Further, the fault detection circuit includes at least two of an under-voltage detection circuit, a temperature detection circuit, and an over-current detection circuit.

Further, when the fault detection circuit includes an under-voltage detection circuit, a temperature detection circuit, and an over-current detection circuit, the fault output port includes a first fault port, a second fault port, and a third fault port, wherein:

The undervoltage detection circuit is connected to the error reporting circuit and is used for detecting whether the power supply voltage is lower than a preset voltage value, and if yes, an undervoltage signal is output to the error reporting circuit;

The temperature detection circuit is connected to the error reporting circuit and is used for detecting whether the temperature of the integrated circuit is higher than a preset temperature value, and if so, an over-temperature signal is output to the error reporting circuit;

The overcurrent detection circuit is connected to the error reporting circuit and is used for detecting whether the external current is higher than a preset current value, and if so, outputting an overcurrent signal to the error reporting circuit;

The fault output circuit is connected with the fault reporting circuit and is respectively connected to the first fault port, the second fault port and the third fault port, and is used for transmitting the fault signal to the first fault port for output when receiving the fault signal output by the fault reporting circuit according to the overcurrent signal; transmitting fault signals to the first fault port and the second fault port to be output when receiving the fault signals output by the fault reporting circuit according to the over-temperature signals; and when receiving a fault signal output by the fault reporting circuit according to the undervoltage signal, transmitting the fault signal to the first fault port, the second fault port and the third fault port for output.

Further, the fault output circuit includes an overcurrent signal receiving circuit, a first output circuit, an overtemperature signal receiving circuit, a second output circuit, an undervoltage signal receiving circuit, a third output circuit, a first diode and a second diode, wherein:

The overcurrent signal receiving circuit is connected between the error reporting circuit and the first output circuit, and the first output circuit is connected to the first fault port;

the over-temperature signal receiving circuit is connected between the error reporting circuit and the second output circuit, and the second output circuit is connected between the second fault ports;

the undervoltage signal receiving circuit is connected between the error reporting circuit and the third output circuit, and the third output circuit is connected between the third fault ports;

The cathode of the first diode is connected between the overcurrent signal receiving circuit and the first output circuit, and the anode of the first diode is connected between the overtemperature signal receiving circuit and the second output circuit;

The cathode of the second diode is connected between the over-temperature signal receiving circuit and the second output circuit, and the anode of the second diode is connected between the under-voltage signal receiving circuit and the third output circuit.

Further, the overcurrent signal receiving circuit is a first resistor, the first output circuit is a first MOS tube, the overtemperature signal receiving circuit is a second resistor, the second output circuit is a second MOS tube, the undervoltage signal receiving circuit is a third resistor, the third output circuit is a third MOS tube, wherein:

the first resistor is connected between the error reporting circuit and the grid electrode of the first MOS tube;

the source electrode of the first MOS tube is grounded, and the drain electrode of the first MOS tube is connected to the first fault port;

the second resistor is connected between the error reporting circuit and the grid electrode of the second MOS tube;

the source electrode of the second MOS tube is grounded, and the drain electrode of the second MOS tube is connected to the second fault port;

The third resistor is connected between the error reporting circuit and the grid electrode of the third MOS tube;

the source electrode of the third MOS tube is grounded, and the drain electrode of the third MOS tube is connected to the third fault port.

Further, the undervoltage detection circuit includes a first protection circuit, a first schmitt circuit, a first filter, and an undervoltage detection unit, wherein:

One end of the first protection circuit is connected with the first Schmitt circuit, and the other end of the first protection circuit is grounded and used for releasing static electricity generated in the circuit;

The first Schmitt circuit is connected to the first filter circuit and is used for filtering interference signals;

The first filter circuit is connected to the undervoltage detection unit and is used for filtering spike voltage signals in input signals;

The undervoltage detection unit is connected to the error reporting circuit and is used for detecting the power supply voltage, and transmitting an undervoltage signal to the error reporting circuit when the power supply voltage is lower than a preset voltage value.

Further, the overcurrent detection circuit includes a second protection circuit, a second schmitt circuit, a second filter, and a first level conversion unit, wherein:

One end of the second protection circuit is connected with the second Schmitt circuit, and the other end of the second protection circuit is grounded and used for releasing static electricity generated in the circuit;

the second Schmitt circuit is connected to the second filter and is used for detecting a current signal acquired by the external sampling circuit, and generating an overcurrent signal to be transmitted to the second filter when the current signal is larger than a preset current value;

the second filter is connected to the first level conversion unit and is used for filtering peak voltage signals in the overcurrent signals;

The first level conversion unit is connected to the error reporting circuit and is used for level converting the received power supply voltage and transmitting the overcurrent signal to the error reporting circuit.

Further, the integrated circuit further includes an enabling circuit, where the enabling circuit is connected to the error reporting circuit and is configured to determine whether the received voltage signal is lower than a preset threshold, and if yes, generate a low level signal and transmit the low level signal to the error reporting circuit.

Further, the enabling circuit includes a third protection circuit, a third schmitt circuit, a third filter, and a second level conversion unit, wherein:

one end of the third protection circuit is connected with the third Schmitt circuit, and the other end of the third protection circuit is grounded and used for releasing static electricity generated in the circuit;

The third schmitt circuit is connected to the third filter and is used for judging whether the received voltage signal is lower than a preset threshold value or not, and outputting the low-level signal to the third filter when the voltage signal is lower than the preset threshold value;

the third filter is connected to the second level conversion unit and is used for filtering peak voltage signals in the low-level signals;

The second level conversion unit is connected to the error reporting circuit and is used for level converting the received power supply voltage and transmitting the low-level signal to the error reporting circuit.

Further, the signal input circuit comprises an upper bridge input circuit and a lower bridge input circuit;

The upper bridge input circuit comprises a fourth protection circuit, a fourth Schmitt circuit, a fourth filter and a third level conversion unit, one end of the fourth protection circuit is connected between an upper bridge input port and the fourth Schmitt circuit, and the other end of the fourth protection circuit is grounded; the fourth Schmitt circuit is connected between an upper bridge input port and the fourth filter, the fourth filter is connected to the third level conversion unit, and the third level conversion unit is connected to the interlocking circuit;

the lower bridge input circuit comprises a fifth protection circuit, a fifth Schmitt circuit, a fifth filter and a fourth level conversion unit, one end of the fifth protection circuit is connected between a lower bridge input port and the fifth Schmitt circuit, and the other end of the fifth protection circuit is grounded; the fifth schmitt circuit is connected between the lower bridge input port and the fifth filter, the fifth filter is connected to the fourth level conversion unit, and the fourth level conversion unit is connected to the interlocking circuit.

Compared with the prior art, the embodiment of the application has the following main beneficial effects:

The application provides a fault error reporting output integrated circuit, which comprises a signal input circuit, an interlocking circuit, a high-voltage driving circuit, a low-voltage driving circuit, a fault detection circuit, an error reporting circuit and a fault output circuit which corresponds to a fault type one by one, wherein the signal input circuit is connected to the interlocking circuit and is used for receiving driving signals; the interlocking circuit is respectively connected with the high-voltage driving circuit and the low-voltage driving circuit, and is used for determining whether to turn off the driving signal according to the level of the driving signal and controlling the output ends of the high-voltage driving circuit and the low-voltage driving circuit to output low-level signals; the high-voltage driving circuit is connected with the error reporting circuit and is used for receiving the enabling signal transmitted by the error reporting circuit and sending the enabling signal to the interlocking circuit; the low-voltage driving circuit is connected with the error reporting circuit and is used for receiving the enabling signal transmitted by the error reporting circuit and sending the enabling signal to the interlocking circuit; the fault detection circuit is connected to the fault reporting circuit and is used for detecting faults, generating fault feedback signals according to the faults and sending the fault feedback signals to the fault reporting circuit; the fault reporting circuit is respectively connected with the high-voltage driving circuit, the low-voltage driving circuit and the fault output circuit and is used for generating a fault signal according to the fault feedback signal and sending the fault signal to the fault output circuit and simultaneously sending an enabling signal to the high-voltage driving circuit and the low-voltage driving circuit; the fault output circuit is used for determining a fault output port according to the fault type of the fault feedback signal and transmitting a fault signal corresponding to the fault type to the fault output port; according to the application, by setting the fault output circuits corresponding to the fault types one by one, when the circuits trigger faults, the corresponding fault output ports are determined according to the fault types, and the fault signals are output, so that the fault types can be clearly output, the time for positioning and analyzing the faults is shortened, and the efficiency is improved.

Drawings

In order to more clearly illustrate the solution of the present application, a brief description will be given below of the drawings required for the description of the embodiments, it being obvious that the drawings in the following description are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a fault-reporting output integrated circuit according to an embodiment of the present application.

Detailed Description

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having" and any variations thereof in the description of the application and the claims and the description of the drawings above are intended to cover a non-exclusive inclusion. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In order to make the person skilled in the art better understand the solution of the present application, the technical solution of the embodiment of the present application will be clearly and completely described below with reference to the accompanying drawings.

The embodiment of the application provides a fault error-reporting output integrated circuit which comprises a signal input circuit 1, an interlocking circuit 2, a high-voltage driving circuit 3, a low-voltage driving circuit 4, a fault detection circuit 5, an error-reporting circuit 6 and a fault output circuit 7 which is in one-to-one correspondence with fault types.

Wherein the signal input circuit 1 is connected to the interlock circuit 2 for receiving the drive signal.

The interlock circuit 2 is respectively connected with the high-voltage driving circuit 3 and the low-voltage driving circuit 4, and is used for determining whether to turn off the driving signal according to the level of the driving signal and controlling the output ends of the high-voltage driving circuit 3 and the low-voltage driving circuit 4 to output low-level signals.

The high-voltage driving circuit 3 is connected with the error reporting circuit 6 and is used for receiving the enabling signal transmitted by the error reporting circuit 6 and sending the enabling signal to the interlocking circuit 2; the low-voltage driving circuit 4 is connected with the error reporting circuit 6, and is used for receiving the enabling signal transmitted by the error reporting circuit 6 and sending the enabling signal to the interlocking circuit 2.

The fault detection circuit 5 is connected to the fault reporting circuit 6, and is configured to detect a fault, generate a fault feedback signal according to the fault, and send the fault feedback signal to the fault reporting circuit 6.

The fault reporting circuit 6 is respectively connected with the high-voltage driving circuit 3, the low-voltage driving circuit 4 and the fault output circuit 7, and is used for generating a fault signal according to the fault feedback signal and sending the fault signal to the fault output circuit 7, and simultaneously sending an enabling signal to the high-voltage driving circuit 3 and the low-voltage driving circuit 4.

And the fault output circuit 7 is used for determining a fault output port according to the fault type of the fault feedback signal and transmitting the fault signal corresponding to the fault type to the fault output port.

In the present embodiment, the fault detection circuit 5 includes at least two of an under-voltage detection circuit 51, a temperature detection circuit 52, and an over-current detection circuit 53, and the fault detection circuits of different types each have their corresponding fault output circuits and fault output ports.

As a specific implementation manner, referring to fig. 1, three kinds of FAULT output may be selected in this embodiment, and the FAULT detection circuit 5 includes an under-voltage detection circuit 51, a temperature detection circuit 52, and an over-current detection circuit 53, and the corresponding FAULT output ports include a first FAULT port FAULT1, a second FAULT port FAULT2, and a third FAULT port FAULT3.

The under-voltage detection circuit 51 is connected to the error reporting circuit 6, and is configured to detect whether the power supply voltage VCC is lower than a preset voltage value, and if yes, output an under-voltage signal to the error reporting circuit 6; the temperature detection circuit 52 is connected to the error reporting circuit 6, and is configured to detect whether the temperature of the integrated circuit is higher than a preset temperature value, and if yes, output an over-temperature signal to the error reporting circuit 6; the overcurrent detection circuit 53 is connected to the fault detection circuit 6, and is configured to detect whether the external current ITRIP is higher than a preset current value, and if yes, output an overcurrent signal to the fault detection circuit 6.

The FAULT output circuit 7 is connected to the FAULT reporting circuit 6 and to the first FAULT port FAULT1, the second FAULT port FAULT2 and the third FAULT port FAULT3, respectively.

When the FAULT reporting circuit 6 receives the overcurrent signal sent by the overcurrent detection circuit 53, a corresponding FAULT signal is generated according to the overcurrent signal and is transmitted to the FAULT output circuit 7, and the FAULT output circuit 7 transmits the FAULT signal to the first FAULT port FAULT1 for output;

when the FAULT reporting circuit 6 receives the over-temperature protection signal sent by the over-temperature detection circuit 52, generating a corresponding FAULT signal according to the over-temperature signal and transmitting the FAULT signal to the FAULT output circuit 7, and the FAULT output circuit 7 transmits the FAULT signal to the first FAULT port FAULT1 and the second FAULT port FAULT2 for outputting;

When the FAULT reporting circuit 6 receives the overvoltage/undervoltage signal sent by the undervoltage detecting circuit 51, a corresponding FAULT signal is generated according to the undervoltage signal and transmitted to the FAULT output circuit 7, and the FAULT output circuit 7 transmits the FAULT signal to the first FAULT port FAULT1, the second FAULT port FAULT2 and the third FAULT port FAULT3 for output.

In this embodiment, the fault signal is output from the corresponding fault output port by the fault reporting circuit 6, and meanwhile, an Enable signal is transmitted to the high voltage driving circuit 3 and the low voltage driving circuit 4, so that the switch of each channel is controlled by the Enable signal, that is, when the fault detection circuit 5 detects a fault, the Enable signal Enable1 output by the fault reporting circuit 6 is at a high level, and when the Enable1 is at a high level, the upper bridge driving signal and the lower bridge driving signal of the signal input circuit 1 are locked no matter whether the upper bridge driving signal and the lower bridge driving signal are at a high level or a low level, and the corresponding signal output ends are all output as low level signals.

In some alternative implementations, the fault output circuit 7 includes an over-current signal receiving circuit 71, a first output circuit 72, an over-temperature signal receiving circuit 73, a second output circuit 74, an under-voltage signal receiving circuit 75, a third output circuit 76, a first diode D1, and a second diode D2, wherein:

the overcurrent signal receiving circuit 71 is connected between the error reporting circuit 6 and the first output circuit 72, and the first output circuit 72 is connected to the first FAULT port FAULT1;

The over-temperature signal receiving circuit 73 is connected between the error reporting circuit 6 and the second output circuit 74, and the second output circuit 74 is connected between the second FAULT ports FAULT 2;

The undervoltage signal receiving circuit 75 is connected between the error reporting circuit 6 and the third output circuit 76, and the third output circuit 76 is connected between the third FAULT ports FAULT 3;

The cathode of the first diode D1 is connected between the overcurrent signal receiving circuit 71 and the first output circuit 72, and the anode of the first diode D1 is connected between the overtemperature signal receiving circuit 73 and the second output circuit 74;

the cathode of the second diode D2 is connected between the over-temperature signal receiving circuit 73 and the second output circuit 74, and the anode of the second diode D2 is connected between the under-voltage signal receiving circuit 75 and the third output circuit 76.

In this embodiment, the overcurrent signal receiving circuit 71 receives the FAULT signal generated by the FAULT signal receiving circuit 6 according to the overcurrent signal, the FAULT signal is a high-level signal, the high-level signal drives the first output circuit 72 to be turned on, a low-level signal is output through the FAULT1 port, the external MCU detects the FAULT low-level signal, and at the same time, the FAULT protection is triggered, and the driving signal of each channel is set to be low level for FAULT protection.

The overtemperature signal receiving circuit 73 receives a FAULT signal generated by the FAULT signal generating circuit 6 according to the overtemperature signal, the FAULT signal is a high level signal, the high level signal drives the second output circuit 72 to be conducted, the first diode D1 is conducted, and the voltage drop of the diode is small because the overtemperature signal receiving circuit 73 outputs the high level signal, so that the high level signal is transmitted to the first output circuit 72, the first output circuit 72 is driven to be conducted, the low level signal is output through a FAULT1 port and a FAULT2 port, the external MCU detects the FAULT low level signal, meanwhile, the FAULT protection is triggered, and the driving signal of each channel is set to be low level for FAULT protection.

Similarly, the undervoltage signal receiving circuit 75 receives a FAULT signal generated by the error reporting circuit 6 according to the undervoltage signal, the FAULT signal is a high level signal, the high level signal drives the third output circuit 76 to be turned on, because the undervoltage signal receiving circuit 75 outputs the high level signal, the second diode D2 is turned on, and the voltage drop of the diode is usually small, so that the high level signal transmitted to the second output circuit 74 drives the second output circuit 74 to be turned on, the high level signal transmitted to the second output circuit 74 triggers the first diode D1 to be turned on, the high level signal transmitted to the first output circuit 72 drives the first output circuit 72 to be turned on, the low level signal is output through the FAULT1 port, the FAULT2 port and the FAULT3 port, the external MCU detects the FAULT low level signal and triggers the FAULT protection, and the driving signal of each channel is set to be low level for FAULT protection.

It should be noted that, the output ports of the faults of different fault types can be selected by themselves, and the present invention is not limited herein.

In this embodiment, the over-current signal receiving circuit 71 is a first resistor R1, the first output circuit 72 is a first MOS transistor, the over-temperature signal receiving circuit 73 is a second resistor R2, the second output circuit 74 is a second MOS transistor, the under-voltage signal receiving circuit 75 is a third resistor R3, and the third output circuit 76 is a third MOS transistor.

The first resistor R1 is connected between the error reporting circuit 6 and the grid electrode of the first MOS tube; the source electrode of the first MOS tube is grounded, and the drain electrode of the first MOS tube is connected to a first FAULT port FAULT1; the second resistor R2 is connected between the error reporting circuit and the grid electrode of the second MOS tube; the source electrode of the second MOS tube is grounded, and the drain electrode of the second MOS tube is connected to a second FAULT port FAULT2; the third resistor R3 is connected between the error reporting circuit 6 and the grid electrode of the third MOS tube; the source electrode of the third MOS tube is grounded, and the drain electrode of the third MOS tube is connected to a third FAULT port FAULT3.

The first resistor R1, the second resistor R2 and the third resistor R3 are driving resistors and are respectively connected with the grid electrodes of the first MOS tube, the second MOS tube and the third MOS tube; the overcurrent detection circuit 53 triggers a FAULT, the FAULT reporting circuit 6 outputs a high-level signal through the first resistor R1, triggers the first MOS tube to be conducted, and the FAULT1 port outputs a low-level FAULT signal; when the over-temperature detection circuit 52 triggers a FAULT, the FAULT reporting circuit 6 outputs a high-level signal through the second resistor R2, triggers the second MOS tube and the first MOS tube to be conducted, and outputs a low-level FAULT signal through the FAULT1 port and the FAULT2 port; when the under-voltage detection circuit 51 triggers a FAULT, the FAULT reporting circuit 6 outputs a high-level signal through the third resistor R3, and triggers the third MOS transistor, the second MOS transistor and the first MOS transistor to be turned on, and the FAULT1 port, the FAULT2 port and the FAULT3 port output low-level FAULT signals.

In the present embodiment, the brown-out detection circuit 51 includes a first protection circuit 511, a first schmitt circuit 512, a first filter 513, and a brown-out detection unit 514.

One end of the first protection circuit 511 is connected between the input port VCC and the first schmitt circuit 512, and the other end of the first protection circuit 511 is grounded for discharging static electricity generated in the circuit; the first schmitt circuit 512 is connected to the first filtering circuit 513 for filtering the interference signal; the first filter circuit 513 is connected to the under-voltage detection unit 514, and is configured to filter out spike voltage signals in the input signal; the under-voltage detection unit 514 is connected to the error reporting circuit 6, and is configured to detect a supply voltage, and transmit an under-voltage signal to the error reporting circuit 6 when the supply voltage is lower than a preset voltage value.

Specifically, the VCC port receives a supply voltage signal transmitted by the power supply, and sequentially transmits the supply voltage signal to the first schmitt circuit 512, the first filter 513, and the brown-out detection unit 514 for detection.

In the present embodiment, the overcurrent detection circuit 53 includes a second protection circuit 531, a second schmitt circuit 532, a second filter 533, and a first level conversion unit 534.

One end of the second protection circuit 531 is connected between the input port ITRIP and the second schmitt circuit 532, and the other end of the second protection circuit 531 is grounded for discharging static electricity generated in the circuit; the second schmitt circuit 532 is connected to the second filter 533 and is configured to detect a current signal collected by the external sampling circuit, and the collected current signal is transmitted to the second schmitt circuit 532 through the ITRIP port, and when the current signal is greater than a preset current value, an overcurrent signal is generated and transmitted to the second filter 533; the second filter 533 is connected to the first level shifter 534 for filtering out spike voltage signals in the filtered signal; the first level conversion unit 534 is connected to the error reporting circuit 6, and is configured to level-convert the received power supply voltage and transmit the over-current signal to the error reporting circuit 6.

Because the threshold voltage of the schmitt circuit is low, in order for the subsequent circuit to work normally, the voltage is converted into the working voltage for the subsequent circuit to work through level conversion. For example, the threshold voltage of the schmitt circuit is 5V, the subsequent circuit needs 15V working voltage, and the level conversion unit converts the 5V voltage into 15V.

In some alternative implementations, the fault error-reporting output integrated circuit further includes an enable circuit 8, where the enable circuit 8 is connected to the error-reporting circuit 6 and configured to determine whether the received voltage signal is below a preset threshold, and if so, generate a low-level signal for transmitting to the error-reporting circuit 6.

MCU can directly transmit the signal to Enable circuit 8 through the EN port, if the voltage signal who receives is EN low level signal, transmit it to the error reporting circuit 6, error reporting circuit 6 receives low level signal, then output Enable high level signal, enable high level signal transmission is to the switch of high voltage drive circuit 3 and low voltage drive circuit 4 control every passageway, when Enable1 is high level, upper and lower bridge drive signal is in high and low level, all locked, the signal output part that corresponds all outputs and is low level signal.

In the present embodiment, the enable circuit 8 includes a third protection circuit 81, a third schmitt circuit 82, a third filter 83, and a second level conversion unit 84.

One end of the third protection circuit 81 is connected between the input port EN and the third schmitt circuit 82, and the other end of the third protection circuit 81 is grounded for discharging static electricity generated in the circuit; the third schmitt circuit 82 is connected to the third filter 83, and is configured to determine whether the received voltage signal is lower than a preset threshold, and output a low-level signal to the third filter 83 when the voltage signal is lower than the preset threshold; the third filter 83 is connected to the second level conversion unit 84, and is used for filtering spike voltage signals in the low level signals; the second level conversion unit 84 is connected to the error reporting circuit 6, and is configured to level-convert the received power supply voltage and transmit a low-level signal to the error reporting circuit 6.

Specifically, the first protection circuit 511, the second protection circuit 531 and the third protection circuit 81 are pull-down resistors, so that the pins are not suspended for preventing static electricity from being damaged, and the pull-down resistors generally provide a load-discharging path, and meanwhile, the pins are prevented from being suspended and subject to external electromagnetic interference.

In this embodiment, the enabling circuit and the fault reporting circuit perform fault protection for the fault reporting output integrated circuit.

In the present embodiment, the signal input circuit 1 is a half-bridge signal input circuit including an upper-bridge input circuit 11 and a lower-bridge input circuit 12.

The upper bridge input circuit 11 includes a fourth protection circuit 111, a fourth schmitt circuit 112, a fourth filter 113, and a third level conversion unit 114, wherein one end of the fourth protection circuit 111 is connected between the upper bridge input port HIN1 and the fourth schmitt circuit 112, and the other end of the fourth protection circuit 111 is grounded; the fourth schmitt circuit 112 is connected between the upper bridge input port HIN1 and the fourth filter 113, the fourth filter 113 is connected to the third level converting unit 114, and the third level converting unit 114 is connected to the interlock circuit 2.

The lower bridge input circuit 12 includes a fifth protection circuit 121, a fifth schmitt circuit 122, a fifth filter 123, and a fourth level conversion unit 124, one end of the fifth protection circuit 121 is connected between the lower bridge input port LIN1 and the fifth schmitt circuit 122, and the other end of the fifth protection circuit 121 is grounded; the fifth schmitt circuit 122 is connected between the lower bridge input port LIN1 and the fifth filter 123, the fifth filter 123 is connected to the fourth level converting unit 124, and the fourth level converting unit 124 is connected to the interlock circuit 2.

The fourth protection circuit 111 and the fifth protection circuit 121 are specifically pull-down resistors, and the working principle is the same as that of the first protection circuit 511, the second protection circuit 531 and the third protection circuit 81, and are not described herein again.

The third level converting unit 114 and the fourth level converting unit 124 also operate in the same manner as the first level converting unit 534.

In the present embodiment, the high voltage driving circuit 3 includes a pulse generator 31, an LDMOS 32, an LDMOS33, a filter 34, a UV detection filter 35, an RS flip-flop 36, and a high voltage driving output circuit 37.

Wherein a first input end of the pulse generator 31 is connected with the interlocking circuit 2, a second input end of the pulse generator 31 is connected with the low-voltage driving circuit 4, a first output end of the pulse generator 31 is connected to the grid electrode of the LDMOS 32, and a second output end of the pulse generator 31 is connected to the grid electrode of the LDMOS 33; the drain electrode of the LDMOS 32 is connected with one end of the resistor R4, and the source electrode of the LDMOS 32 is grounded; the drain electrode of the LDMOS 33 is connected with one end of the resistor R5, and the source electrode of the LDMOS 33 is grounded; a first input terminal of the filter 34 is connected between the drain of the LDMOS 32 and the resistor R4, a second input terminal of the filter 34 is connected between the drain of the LDMOS 33 and the resistor R5, a first output terminal of the filter 34 is connected to the R terminal of the RS flip-flop 36, and a second output terminal of the filter 34 is connected to the S terminal of the RS flip-flop 36; the other end of the resistor R4 is connected with the VB1 end, and the other end of the resistor R5 is connected with the VB1 end; the UV detection filter 35 is respectively connected with the VB1 end and the R end of the RS trigger 36; the Q terminal of the RS flip-flop 36 is connected to a high-voltage drive output circuit 37.

The high-voltage driving output circuit 37 includes an output pair transistor MOS transistor Q1, a MOS transistor Q2, a resistor R6 and a resistor R7, specifically, a drain electrode of Q1 is connected to a terminal VB1, a gate electrode of Q1 is connected to a Q terminal of the RS flip-flop 36, a source electrode of Q1 is connected to the resistor R6, the resistor R6 is connected to the resistor R7 in series, and then connected to a drain electrode of Q2, a gate electrode of Q2 is connected to a Q terminal of the RS flip-flop 36, a source electrode of Q2 is connected to a terminal VS1, and a common connection point of the resistor R6 and the resistor R7 is connected to the output terminal HO1.

The pulse generator 31 receives the upper bridge driving signal transmitted by the upper bridge input circuit 11 through the interlocking circuit 2, converts the upper bridge driving signal into a pulse signal, transmits the pulse signal to the filter 34 through the LDMOS 32 and the LDMOS 33 to filter out the interference signal, and then transmits the pulse signal to the RS trigger 36, and outputs the pulse signal to the common connection point of the resistor R6 and the resistor R7, and then distributes the driving signal to the Q1 and the Q2 through the resistor R6 and the resistor R7.

In the present embodiment, the low voltage driving circuit 4 includes a delay circuit 41, a logic circuit 42, and a low voltage driving output circuit 43, wherein the delay circuit 41 is connected to the interlock circuit 2 and the logic circuit 42, respectively, and the logic circuit 42 is connected to the second input terminal of the pulse generator 31 and the low voltage driving output circuit 43, respectively.

In the present embodiment, the delay circuit 41 is used to ensure that the high-voltage drive circuit 3 and the low-voltage drive circuit 4 can output at the same time.

Specifically, the logic circuit 42 is a nand gate, the input terminal a of which is connected to the second input terminal of the pulse generator 31, the input terminal B of which is connected to the delay circuit 41, and the output terminal Y of which is connected to the low-voltage drive output circuit 43.

The low-voltage driving output circuit 43 includes an output pair transistor MOS transistor Q3, a MOS transistor Q4, a resistor R8 and a resistor R9, specifically, a drain electrode of Q3 is connected to a VCC terminal, a gate electrode of Q3 is connected to an output terminal Y of the nand gate, a source electrode of Q3 is connected to the resistor R8, the resistor R8 is connected to the drain electrode of Q4 after being connected in series with the resistor R9, a gate electrode of Q4 is connected to the output terminal Y of the nand gate, a source electrode of Q4 is connected to a NU terminal, and a common connection point of the resistor R8 and the resistor R8 is connected to the output terminal LO1.

In this embodiment, if the driving signals output by the upper bridge input circuit 11 and the lower bridge input circuit 12 are both high level signals, the interlocking circuit 2 locks the upper bridge driving signal and the lower bridge driving signal, and the corresponding signal output terminals are both low level signals, so as to avoid short circuit caused by that the output terminals HO1 and LO1 output high level signals at the same time.

Based on the fault error-reporting output integrated circuit, by arranging the fault output circuits corresponding to the fault types one by one, when the circuit triggers the fault, the corresponding fault output ports are determined according to the fault types, and fault signals are output, so that the fault types can be defined, the time for positioning and analyzing the fault is shortened, and the efficiency is improved.

It is apparent that the above-described embodiments are only some embodiments of the present application, but not all embodiments, and the preferred embodiments of the present application are shown in the drawings, which do not limit the scope of the patent claims. This application may be embodied in many different forms, but rather, embodiments are provided in order to provide a thorough and complete understanding of the present disclosure. Although the application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing description, or equivalents may be substituted for elements thereof. All equivalent structures made by the content of the specification and the drawings of the application are directly or indirectly applied to other related technical fields, and are also within the scope of the application.

Claims

1. A fault-reporting output integrated circuit, comprising:

The fault detection circuit comprises a signal input circuit, an interlocking circuit, a high-voltage driving circuit, a low-voltage driving circuit, a fault detection circuit, an error reporting circuit and a fault output circuit which corresponds to the fault type one by one;

the fault output circuit is used for determining a fault output port according to the fault type of the fault feedback signal and transmitting a fault signal corresponding to the fault type to the fault output port;

the fault detection circuit comprises at least two of an undervoltage detection circuit, a temperature detection circuit and an overcurrent detection circuit;

When the fault detection circuit includes an under-voltage detection circuit, a temperature detection circuit, and an over-current detection circuit, the fault output port includes a first fault port, a second fault port, and a third fault port, wherein:

2. The fault-finding output integrated circuit of claim 1, wherein the fault output circuit comprises an over-current signal receiving circuit, a first output circuit, an over-temperature signal receiving circuit, a second output circuit, an under-voltage signal receiving circuit, a third output circuit, a first diode, and a second diode, wherein:

3. The fault-reporting output integrated circuit of claim 2, wherein the over-current signal receiving circuit is a first resistor, the first output circuit is a first MOS transistor, the over-temperature signal receiving circuit is a second resistor, the second output circuit is a second MOS transistor, the under-voltage signal receiving circuit is a third resistor, and the third output circuit is a third MOS transistor, wherein:

4. The fault-finding output integrated circuit of claim 1, wherein the brown-out detection circuit comprises a first protection circuit, a first schmitt circuit, a first filter circuit, and a brown-out detection unit, wherein:

5. The fault-finding output integrated circuit of claim 1, wherein the overcurrent detection circuit comprises a second protection circuit, a second schmitt circuit, a second filter, and a first level shift unit, wherein:

6. The fault-reporting output integrated circuit of claim 1, further comprising an enable circuit coupled to the fault-reporting circuit for determining whether the received voltage signal is below a predetermined threshold, and if so, generating a low-level signal for transmission to the fault-reporting circuit.

7. The fault-finding output integrated circuit of claim 6, wherein the enabling circuit comprises a third protection circuit, a third schmitt circuit, a third filter, and a second level shifting unit, wherein:

8. The fault-reporting output integrated circuit of claim 1, wherein the signal input circuit comprises an upper bridge input circuit and a lower bridge input circuit;