CN114816817A

CN114816817A - Fault reporting and outputting integrated circuit

Info

Publication number: CN114816817A
Application number: CN202210389353.XA
Authority: CN
Inventors: 李秉纬; 张焕云
Original assignee: Shenzhen Simi Semiconductor Co ltd
Current assignee: Shenzhen Simi Semiconductor Co ltd
Priority date: 2022-04-13
Filing date: 2022-04-13
Publication date: 2022-07-29
Anticipated expiration: 2042-04-13
Also published as: CN114816817B

Abstract

The embodiment of the application belongs to the technical field of integrated circuits, and relates to a fault error reporting output integrated circuit which comprises a signal input circuit, an interlocking circuit, a high-voltage driving circuit, a low-voltage driving circuit, a fault detection circuit, an error reporting circuit and a fault output circuit, wherein the signal input circuit is connected to the interlocking circuit, and the interlocking circuit is respectively connected with the high-voltage driving circuit and the low-voltage driving circuit and used for controlling the output end of the interlocking circuit to output a low-level signal; the fault detection circuit is connected to the error reporting circuit and used for detecting faults, generating fault feedback signals and sending the fault feedback signals to the error reporting circuit; the fault reporting circuit is used for generating a fault signal according to the fault feedback signal and sending the fault signal to the fault output circuit, and sending an enable signal to the high-voltage driving circuit and the low-voltage driving circuit; and the fault output circuit is used for determining a fault output port according to the fault type of the fault feedback signal and outputting a fault signal. The technical scheme provided by the application can clearly output the fault type and shorten the time for positioning and analyzing the fault.

Description

Fault reporting and outputting integrated circuit

Technical Field

The present disclosure relates to the field of high voltage integrated circuit technologies, and more particularly, to an error reporting output integrated circuit.

Background

Under the traction of emerging industries such as smart grids, mobile communication, new energy automobiles and the like, power electronic application systems require further improvement of efficiency, miniaturization and added functions of the systems, and particularly require trade-offs among size, quality, power and efficiency of system equipment, such as server power management, battery chargers and micro-inverters of solar farms. In order to accommodate High Voltage, High temperature, High efficiency and High power density applications, High Voltage Integrated Circuits (HVICs) have been developed.

An HVIC is a high voltage integrated circuit product that converts MCU (micro controller Unit) signals into signals that drive IGBTs (Insulated Gate Bipolar transistors) and MOSFETs (Metal-Oxide-Semiconductor Field Effect transistors). On one hand, the HVIC receives a control signal of an MCU (Microcontroller Unit) to drive a subsequent IGBT or MOSFET to operate, and on the other hand, sends a fault state detection signal of the system back to the MCU, which is a key chip inside an Intelligent Power Module (IPM).

At present, when an HVIC is applied, undervoltage protection, overcurrent protection and overtemperature protection of the HVIC are excited, two paths of fault signals are output through an internal fault reporting circuit, one path of fault signals is invalid in a control logic input port, the other path of fault signals is output to an external MCU, and the MCU detects the fault signals to report faults. Because the fault signal is output through only one path of signal, when the HVIC is triggered to fail, the specific fault type cannot be judged, a large amount of time is needed to locate and analyze the specific fault, and the analysis and location efficiency is low.

Disclosure of Invention

The technical problem to be solved by the embodiment of the application is that only one path of fault signal output exists in the related technology, so that when a high-voltage integrated circuit is triggered to have a fault, the specific type of the fault cannot be judged, and a large amount of time is needed for positioning and analyzing the fault.

In order to solve the above technical problem, an embodiment of the present application provides a fault error reporting output integrated circuit, which adopts the following technical solutions:

the fault detection circuit comprises a signal input circuit, an interlocking circuit, a high-voltage driving circuit, a low-voltage driving circuit, a fault detection circuit, an error reporting circuit and a fault output circuit which corresponds to fault types one to one;

the signal input circuit is connected to the interlocking circuit and used for receiving a driving signal;

the interlocking circuit is respectively connected with the high-voltage driving circuit and the low-voltage driving circuit and used for determining whether to turn off the driving signal according to the level of the driving signal and controlling the output ends of the high-voltage driving circuit and the low-voltage driving circuit to output low-level signals;

the high-voltage driving circuit is connected with the error reporting circuit and used for receiving an enabling signal transmitted by the error reporting circuit and sending the enabling signal to the interlocking circuit;

the low-voltage driving circuit is connected with the error reporting circuit and used for receiving an enabling signal transmitted by the error reporting circuit and sending the enabling signal to the interlocking circuit;

the fault detection circuit is connected to the error reporting circuit and used for detecting faults and generating fault feedback signals according to the faults and sending the fault feedback signals to the error reporting circuit;

the fault reporting circuit is respectively connected with the high-voltage driving circuit, the low-voltage driving circuit and the fault output circuit, and is used for generating a fault signal according to the fault feedback signal, sending the fault signal to the fault output circuit, and sending the enable signal to the high-voltage driving circuit and the low-voltage driving circuit;

and the fault output circuit is used for determining a fault output port according to the fault type of the fault feedback signal and transmitting the fault signal corresponding to the fault type to the fault output port.

Further, the fault detection circuit comprises at least two of an under-voltage detection circuit, a temperature detection circuit and an over-current detection circuit.

Further, when the fault detection circuit includes an under-voltage detection circuit, a temperature detection circuit, and an over-current detection circuit, the fault output port includes a first fault port, a second fault port, and a third fault port, wherein:

the undervoltage detection circuit is connected to the error reporting circuit and is used for detecting whether the power supply voltage is lower than a preset voltage value, and if so, outputting an undervoltage signal to the error reporting circuit;

the temperature detection circuit is connected to the error reporting circuit and is used for detecting whether the temperature of the integrated circuit is higher than a preset temperature value or not, and if so, outputting an over-temperature signal to the error reporting circuit;

the overcurrent detection circuit is connected to the error reporting circuit and is used for detecting whether the external current is higher than a preset current value, and if so, outputting an overcurrent signal to the error reporting circuit;

the fault output circuit is connected with the error reporting circuit, is respectively connected to the first fault port, the second fault port and the third fault port, and is used for transmitting a fault signal to the first fault port for output when receiving the fault signal output by the error reporting circuit according to the overcurrent signal; when a fault signal output by the error reporting circuit according to an over-temperature signal is received, transmitting the fault signal to the first fault port and the second fault port for output; and when receiving a fault signal output by the error reporting circuit according to the undervoltage signal, transmitting the fault signal to the first fault port, the second fault port and the third fault port for output.

Further, the fault output circuit includes an overcurrent signal receiving circuit, a first output circuit, an overtemperature signal receiving circuit, a second output circuit, an undervoltage signal receiving circuit, a third output circuit, a first diode and a second diode, wherein:

the overcurrent signal receiving circuit is connected between the error reporting circuit and the first output circuit, and the first output circuit is connected to the first fault port;

the over-temperature signal receiving circuit is connected between the error reporting circuit and the second output circuit, and the second output circuit is connected between the second fault ports;

the undervoltage signal receiving circuit is connected between the error reporting circuit and the third output circuit, and the third output circuit is connected between the third fault ports;

the cathode of the first diode is connected between the over-current signal receiving circuit and the first output circuit, and the anode of the first diode is connected between the over-temperature signal receiving circuit and the second output circuit;

the cathode of the second diode is connected between the over-temperature signal receiving circuit and the second output circuit, and the anode of the second diode is connected between the under-voltage signal receiving circuit and the third output circuit.

Further, the over-current signal receiving circuit is a first resistor, the first output circuit is a first MOS transistor, the over-temperature signal receiving circuit is a second resistor, the second output circuit is a second MOS transistor, the under-voltage signal receiving circuit is a third resistor, and the third output circuit is a third MOS transistor, wherein:

the first resistor is connected between the error reporting circuit and the grid electrode of the first MOS tube;

the source electrode of the first MOS tube is grounded, and the drain electrode of the first MOS tube is connected to the first fault port;

the second resistor is connected between the error reporting circuit and the grid electrode of the second MOS tube;

the source electrode of the second MOS tube is grounded, and the drain electrode of the second MOS tube is connected to the second fault port;

the third resistor is connected between the error reporting circuit and the grid electrode of the third MOS tube;

the source electrode of the third MOS tube is grounded, and the drain electrode of the third MOS tube is connected to the third fault port.

Further, the under-voltage detection circuit includes a first protection circuit, a first schmitt circuit, a first filter and an under-voltage detection unit, wherein:

one end of the first protection circuit is connected with the first Schmitt circuit, and the other end of the first protection circuit is grounded and used for releasing static electricity generated in the circuit;

the first Schmitt circuit is connected to the first filter circuit and is used for filtering interference signals;

the first filter circuit is connected to the undervoltage detection unit and is used for filtering spike voltage signals in input signals;

the undervoltage detection unit is connected to the error reporting circuit and used for detecting the power supply voltage and transmitting an undervoltage signal to the error reporting circuit when the power supply voltage is lower than a preset voltage value.

Further, the over-current detection circuit includes a second protection circuit, a second schmitt circuit, a second filter, and a first level shift unit, wherein:

one end of the second protection circuit is connected with the second Schmitt circuit, and the other end of the second protection circuit is grounded and used for releasing static electricity generated in the circuit;

the second Schmitt circuit is connected to the second filter and used for detecting a current signal acquired by an external sampling circuit, and when the current signal is greater than a preset current value, an overcurrent signal is generated and transmitted to the second filter;

the second filter is connected to the first level conversion unit and is used for filtering spike voltage signals in the overcurrent signals;

the first level conversion unit is connected to the error reporting circuit and used for performing level conversion on the received power supply voltage and transmitting the overcurrent signal to the error reporting circuit.

Furthermore, the integrated circuit further includes an enable circuit, where the enable circuit is connected to the error reporting circuit and is configured to determine whether the received voltage signal is lower than a preset threshold, and if so, generate a low level signal and transmit the low level signal to the error reporting circuit.

Further, the enabling circuit includes a third protection circuit, a third schmitt circuit, a third filter, and a second level shifting unit, wherein:

one end of the third protection circuit is connected with the third Schmitt circuit, and the other end of the third protection circuit is grounded and used for releasing static electricity generated in the circuit;

the third Schmitt circuit is connected to the third filter and used for judging whether the received voltage signal is lower than a preset threshold value or not, and when the voltage signal is smaller than the preset threshold value, outputting the low-level signal to the third filter;

the third filter is connected to the second level conversion unit and is used for filtering spike voltage signals in the low-level signals;

the second level conversion unit is connected to the error reporting circuit, and is configured to perform level conversion on the received power supply voltage and transmit the low level signal to the error reporting circuit.

Further, the signal input circuit comprises an upper bridge input circuit and a lower bridge input circuit;

the upper bridge input circuit comprises a fourth protection circuit, a fourth Schmitt circuit, a fourth filter and a third level conversion unit, one end of the fourth protection circuit is connected between the upper bridge input port and the fourth Schmitt circuit, and the other end of the fourth protection circuit is grounded; the fourth schmitt circuit is connected between an upper bridge input port and the fourth filter, the fourth filter is connected to the third level shift unit, and the third level shift unit is connected to the interlock circuit;

the lower bridge input circuit comprises a fifth protection circuit, a fifth Schmitt circuit, a fifth filter and a fourth level conversion unit, one end of the fifth protection circuit is connected between the lower bridge input port and the fifth Schmitt circuit, and the other end of the fifth protection circuit is grounded; the fifth schmitt circuit is connected between a lower bridge input port and the fifth filter, the fifth filter is connected to the fourth level shift unit, and the fourth level shift unit is connected to the interlock circuit.

Compared with the prior art, the embodiment of the application mainly has the following beneficial effects:

the fault error reporting output integrated circuit comprises a signal input circuit, an interlocking circuit, a high-voltage driving circuit, a low-voltage driving circuit, a fault detection circuit, an error reporting circuit and a fault output circuit which corresponds to fault types one to one, wherein the signal input circuit is connected to the interlocking circuit and used for receiving driving signals; the interlocking circuit is respectively connected with the high-voltage driving circuit and the low-voltage driving circuit and used for determining whether to turn off the driving signal according to the level of the driving signal and controlling the output ends of the high-voltage driving circuit and the low-voltage driving circuit to output a low-level signal; the high-voltage driving circuit is connected with the error reporting circuit and used for receiving the enabling signal transmitted by the error reporting circuit and sending the enabling signal to the interlocking circuit; the low-voltage driving circuit is connected with the error reporting circuit and used for receiving the enabling signal transmitted by the error reporting circuit and sending the enabling signal to the interlocking circuit; the fault detection circuit is connected to the error reporting circuit and used for detecting faults, generating fault feedback signals according to the faults and sending the fault feedback signals to the error reporting circuit; the fault reporting circuit is respectively connected with the high-voltage driving circuit, the low-voltage driving circuit and the fault output circuit, and is used for generating a fault signal according to the fault feedback signal, sending the fault signal to the fault output circuit and sending an enabling signal to the high-voltage driving circuit and the low-voltage driving circuit; the fault output circuit is used for determining a fault output port according to the fault type of the fault feedback signal and transmitting a fault signal corresponding to the fault type to the fault output port; according to the method and the device, the fault output circuits are in one-to-one correspondence with the fault types, when the circuit triggers a fault, the corresponding fault output ports are determined according to the fault types, fault signals are output, the fault types can be definitely output, the time for positioning and analyzing the fault is shortened, and the efficiency is improved.

Drawings

In order to illustrate the solution of the present application more clearly, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.

Fig. 1 is a schematic structural diagram of a fault error reporting output integrated circuit according to an embodiment of the present application.

Detailed Description

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "including" and "having," and any variations thereof, in the description and claims of this application and the description of the above figures are intended to cover non-exclusive inclusions. The terms "first," "second," and the like in the description and claims of this application or in the above-described drawings are used for distinguishing between different objects and not for describing a particular order.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

The embodiment of the application provides a fault error reporting output integrated circuit, which comprises a signal input circuit 1, an interlocking circuit 2, a high-voltage driving circuit 3, a low-voltage driving circuit 4, a fault detection circuit 5, an error reporting circuit 6 and a fault output circuit 7 which is in one-to-one correspondence with fault types.

Wherein, the signal input circuit 1 is connected to the interlock circuit 2 for receiving the driving signal.

The interlock circuit 2 is respectively connected with the high-voltage driving circuit 3 and the low-voltage driving circuit 4, and is used for determining whether to turn off the driving signal according to the level of the driving signal and controlling the output ends of the high-voltage driving circuit 3 and the low-voltage driving circuit 4 to output low-level signals.

The high-voltage driving circuit 3 is connected with the error reporting circuit 6 and used for receiving the enabling signal transmitted by the error reporting circuit 6 and sending the enabling signal to the interlocking circuit 2; the low-voltage driving circuit 4 is connected with the error reporting circuit 6, and is used for receiving the enabling signal transmitted by the error reporting circuit 6 and sending the enabling signal to the interlock circuit 2.

The fault detection circuit 5 is connected to the error reporting circuit 6, and is configured to detect a fault, generate a fault feedback signal according to the fault, and send the fault feedback signal to the error reporting circuit 6.

The error reporting circuit 6 is respectively connected with the high-voltage driving circuit 3, the low-voltage driving circuit 4 and the fault output circuit 7, and is configured to generate a fault signal according to the fault feedback signal, send the fault signal to the fault output circuit 7, and send an enable signal to the high-voltage driving circuit 3 and the low-voltage driving circuit 4.

And the fault output circuit 7 is used for determining a fault output port according to the fault type of the fault feedback signal and transmitting the fault signal corresponding to the fault type to the fault output port.

In the present embodiment, the fault detection circuit 5 includes at least two of the undervoltage detection circuit 51, the temperature detection circuit 52 and the overcurrent detection circuit 53, and the fault detection circuits of different types have their corresponding fault output circuits and fault output ports.

As a specific implementation manner, referring to fig. 1, the present embodiment may select three FAULT output categories, where the FAULT detection circuit 5 includes an under-voltage detection circuit 51, a temperature detection circuit 52, and an over-current detection circuit 53, and correspondingly, the FAULT output ports include a first FAULT port FAULT1, a second FAULT port FAULT2, and a third FAULT port FAULT 3.

The undervoltage detection circuit 51 is connected to the error reporting circuit 6, and configured to detect whether the power supply voltage VCC is lower than a preset voltage value, and if so, output an undervoltage signal to the error reporting circuit 6; the temperature detection circuit 52 is connected to the error reporting circuit 6, and is configured to detect whether the temperature of the integrated circuit is higher than a preset temperature value, and if so, output an over-temperature signal to the error reporting circuit 6; the over-current detection circuit 53 is connected to the error reporting circuit 6, and is configured to detect whether the external current ITRIP is higher than a preset current value, and if so, output an over-current signal to the error reporting circuit 6.

The FAULT output circuit 7 is connected to the FAULT reporting circuit 6 and to the first FAULT port FAULT1, the second FAULT port FAULT2 and the third FAULT port FAULT3, respectively.

When the error reporting circuit 6 receives the overcurrent signal sent by the overcurrent detection circuit 53, a corresponding FAULT signal is generated according to the overcurrent signal and transmitted to the FAULT output circuit 7, and the FAULT output circuit 7 transmits the FAULT signal to the first FAULT port FAULT1 for output;

when the error reporting circuit 6 receives the over-temperature protection signal sent by the over-temperature detection circuit 52, a corresponding FAULT signal is generated according to the over-temperature signal and transmitted to the FAULT output circuit 7, and the FAULT output circuit 7 transmits the FAULT signal to the first FAULT port FAULT1 and the second FAULT port FAULT2 for output;

when the FAULT reporting circuit 6 receives the over-voltage and under-voltage signal sent by the under-voltage detection circuit 51, a corresponding FAULT signal is generated according to the under-voltage signal and transmitted to the FAULT output circuit 7, and the FAULT output circuit 7 transmits the FAULT signal to the first FAULT port FAULT1, the second FAULT port FAULT2, and the third FAULT port FAULT3 for output.

In this embodiment, the error reporting circuit 6 transmits an Enable signal to the high voltage driving circuit 3 and the low voltage driving circuit 4 while outputting the fault signal from the corresponding fault output port, so that when the switch of each channel is controlled by the Enable signal, i.e. the fault detection circuit 5 detects a fault, the Enable signal Enable1 output by the error reporting circuit 6 is at a high level, and when the Enable1 is at a high level, the upper and lower bridge driving signals of the signal input circuit 1 are locked regardless of being at the high and low levels, and the corresponding signal output terminals all output low level signals.

In some optional implementations, the fault output circuit 7 includes an over-current signal receiving circuit 71, a first output circuit 72, an over-temperature signal receiving circuit 73, a second output circuit 74, a under-voltage signal receiving circuit 75, a third output circuit 76, a first diode D1, and a second diode D2, wherein:

the overcurrent signal receiving circuit 71 is connected between the error reporting circuit 6 and the first output circuit 72, and the first output circuit 72 is connected to the first FAULT port FAULT 1;

the over-temperature signal receiving circuit 73 is connected between the error reporting circuit 6 and the second output circuit 74, and the second output circuit 74 is connected between the second FAULT port FAULT 2;

the under-voltage signal receiving circuit 75 is connected between the error reporting circuit 6 and the third output circuit 76, and the third output circuit 76 is connected between the third FAULT port FAULT 3;

a cathode of the first diode D1 is connected between the overcurrent signal receiving circuit 71 and the first output circuit 72, and an anode of the first diode D1 is connected between the overtemperature signal receiving circuit 73 and the second output circuit 74;

the cathode of the second diode D2 is connected between the over-temperature signal receiving circuit 73 and the second output circuit 74, and the anode of the second diode D2 is connected between the under-voltage signal receiving circuit 75 and the third output circuit 76.

In this embodiment, the over-current signal receiving circuit 71 receives a FAULT signal generated by the error reporting circuit 6 according to the over-current signal, where the FAULT signal is a high-level signal, the high-level signal drives the first output circuit 72 to be turned on, and a low-level signal is output through a FAULT1 port, the external MCU detects a FAULT low-level signal and triggers FAULT protection, and the driving signal of each channel is set to a low level for FAULT protection.

The over-temperature signal receiving circuit 73 receives a FAULT signal generated by the error reporting circuit 6 according to the over-temperature signal, the FAULT signal is a high-level signal, the high-level signal drives the second output circuit 72 to be conducted, the high-level signal is output by the over-temperature signal receiving circuit 73, the first diode D1 is conducted, and the voltage drop of the diode is usually small, so that the high-level signal is transmitted to the first output circuit 72 to drive the first output circuit 72 to be conducted, the low-level signal is output through the FAULT1 port and the FAULT2 port, the external MCU detects the FAULT low-level signal and triggers FAULT protection, and the driving signal of each channel is set to be at a low level to perform FAULT protection.

Similarly, the under-voltage signal receiving circuit 75 receives the fault signal generated by the error reporting circuit 6 according to the under-voltage signal, the fault signal is a high level signal, the high level signal drives the third output circuit 76 to be conducted, since the undervoltage signal receiving circuit 75 outputs a high level signal, the second diode D2 is conducted, the voltage drop of the diode is usually small, therefore, the high signal transmitted to the second output circuit 74 drives the second output circuit 74 to be turned on, the high signal transmitted to the second output circuit 74 triggers the first diode D1 to be turned on, the high signal transmitted to the first output circuit 72 also drives the first output circuit 72 to be turned on, the low signals are output through the FAULT1 port, the FAULT2 port and the FAULT3 port, the external MCU detects the FAULT low signal, and simultaneously triggering fault protection, and setting the driving signal of each channel to be at a low level to perform fault protection.

It should be noted that the output port of the fault of different fault types may be selected by itself, and is not limited herein.

In this embodiment, the over-current signal receiving circuit 71 is a first resistor R1, the first output circuit 72 is a first MOS transistor, the over-temperature signal receiving circuit 73 is a second resistor R2, the second output circuit 74 is a second MOS transistor, the under-voltage signal receiving circuit 75 is a third resistor R3, and the third output circuit 76 is a third MOS transistor.

The first resistor R1 is connected between the error reporting circuit 6 and the gate of the first MOS transistor; the source electrode of the first MOS tube is grounded, and the drain electrode of the first MOS tube is connected to the first FAULT port FAULT 1; the second resistor R2 is connected between the error reporting circuit and the grid of the second MOS tube; the source electrode of the second MOS tube is grounded, and the drain electrode of the second MOS tube is connected to the second FAULT port FAULT 2; the third resistor R3 is connected between the error reporting circuit 6 and the gate of the third MOS transistor; the source of the third MOS transistor is grounded, and the drain of the third MOS transistor is connected to the third FAULT port FAULT 3.

The first resistor R1, the second resistor R2 and the third resistor R3 are driving resistors and are respectively connected with the gates of the first MOS transistor, the second MOS transistor and the third MOS transistor; when the overcurrent detection circuit 53 triggers a FAULT, the error reporting circuit 6 outputs a high-level signal through the first resistor R1 to trigger the first MOS transistor to be conducted, and the FAULT port FAULT1 outputs a low-level FAULT signal; when the over-temperature detection circuit 52 triggers a FAULT, the error reporting circuit 6 outputs a high-level signal through the second resistor R2 to trigger the conduction of the second MOS transistor and the first MOS transistor, and the FAULT1 port and the FAULT2 port output low-level FAULT signals; when the under-voltage detection circuit 51 triggers a FAULT, the error reporting circuit 6 outputs a high-level signal through the third resistor R3 to trigger the third MOS transistor, the second MOS transistor and the first MOS transistor to be conducted, and the FAULT port FAULT1, the FAULT port FAULT2 and the FAULT port FAULT3 output low-level FAULT signals.

In the present embodiment, the brown-out detection circuit 51 includes a first protection circuit 511, a first Schmitt circuit 512, a first filter 513 and a brown-out detection unit 514.

One end of the first protection circuit 511 is connected between the input port VCC and the first schmitt circuit 512, and the other end of the first protection circuit 511 is grounded and used for releasing static electricity generated in the circuit; the first schmitt circuit 512 is connected to the first filter circuit 513, and is configured to filter the interference signal; the first filter circuit 513 is connected to the under-voltage detection unit 514, and is configured to filter out a spike voltage signal in the input signal; the under-voltage detection unit 514 is connected to the error reporting circuit 6, and is configured to detect the power supply voltage, and transmit an under-voltage signal to the error reporting circuit 6 when the power supply voltage is lower than a predetermined voltage value.

Specifically, the VCC port receives a power supply voltage signal transmitted by the power supply, and sequentially transmits the power supply voltage signal to the first schmitt circuit 512, the first filter 513 and the under-voltage detection unit 514 for detection.

In the present embodiment, the overcurrent detection circuit 53 includes a second protection circuit 531, a second schmitt circuit 532, a second filter 533, and a first level shift unit 534.

One end of the second protection circuit 531 is connected between the input port ITRIP and the second schmitt circuit 532, and the other end of the second protection circuit 531 is grounded and used for releasing static electricity generated in the circuit; the second schmitt circuit 532 is connected to the second filter 533, and is configured to detect a current signal collected by the external sampling circuit, transmit the collected current signal to the second schmitt circuit 532 through the ITRIP port, and generate an overcurrent signal to transmit to the second filter 533 when the current signal is greater than a preset current value; the second filter 533 is connected to the first level shifting unit 534, and is configured to filter a spike voltage signal in the overcurrent signal; the first level shifting unit 534 is connected to the error reporting circuit 6, and is configured to perform level shifting on the received power supply voltage and transmit the overcurrent signal to the error reporting circuit 6.

Because the threshold voltage of the Schmitt circuit is low, in order to ensure that the subsequent circuit can work normally, the voltage needs to be converted into working voltage for the subsequent circuit to work through level conversion. For example, if the threshold voltage of the schmitt circuit is 5V and the subsequent circuits require 15V of operating voltage, the 5V voltage is converted into 15V by the level conversion unit.

In some optional implementations, the fault error reporting output integrated circuit further includes an enabling circuit 8, and the enabling circuit 8 is connected to the error reporting circuit 6 and configured to determine whether the received voltage signal is lower than a preset threshold, and if so, generate a low level signal to be transmitted to the error reporting circuit 6.

The MCU can directly transmit signals to the enabling circuit 8 through the EN port, if the received voltage signals are EN low-level signals, the EN low-level signals are transmitted to the error reporting circuit 6, the error reporting circuit 6 receives the low-level signals and outputs Enable high-level signals, the Enable high-level signals are transmitted to the high-voltage driving circuit 3 and the low-voltage driving circuit 4 to control the switch of each channel, when the Enable1 is high-level, the upper and lower bridge driving signals are locked no matter in high-low level, and the corresponding signal output ends all output low-level signals.

In the present embodiment, the enable circuit 8 includes a third protection circuit 81, a third schmitt circuit 82, a third filter 83, and a second level shift unit 84.

One end of the third protection circuit 81 is connected between the input port EN and the third schmitt circuit 82, and the other end of the third protection circuit 81 is grounded and used for releasing static electricity generated in the circuit; the third schmitt circuit 82 is connected to the third filter 83, and is configured to determine whether the received voltage signal is lower than a preset threshold, and output a low level signal to the third filter 83 when the voltage signal is smaller than the preset threshold; the third filter 83 is connected to the second level conversion unit 84, and is configured to filter out a spike voltage signal in the low level signal; the second level conversion unit 84 is connected to the error reporting circuit 6, and is configured to perform level conversion on the received power supply voltage and transmit a low level signal to the error reporting circuit 6.

Specifically, the first protection circuit 511, the second protection circuit 531, and the third protection circuit 81 are pull-down resistors, and in order to prevent damage caused by static electricity, the pins that are not used cannot be suspended, and are generally connected with the pull-down resistors to provide a load relief path, and meanwhile, the pins are prevented from being suspended and being subjected to external electromagnetic interference.

In this embodiment, the enabling circuit and the error reporting circuit jointly perform the fault protection for the fault error reporting output integrated circuit.

In the present embodiment, the signal input circuit 1 is a half-bridge signal input circuit, and includes an upper bridge input circuit 11 and a lower bridge input circuit 12.

The upper bridge input circuit 11 includes a fourth protection circuit 111, a fourth schmitt circuit 112, a fourth filter 113 and a third level shifter 114, one end of the fourth protection circuit 111 is connected between the upper bridge input port HIN1 and the fourth schmitt circuit 112, and the other end of the fourth protection circuit 111 is grounded; the fourth schmitt circuit 112 is connected between the upper bridge input port HIN1 and the fourth filter 113, the fourth filter 113 is connected to the third level shift unit 114, and the third level shift unit 114 is connected to the interlock circuit 2.

The lower bridge input circuit 12 includes a fifth protection circuit 121, a fifth schmitt circuit 122, a fifth filter 123, and a fourth level shift unit 124, one end of the fifth protection circuit 121 is connected between the lower bridge input port LIN1 and the fifth schmitt circuit 122, and the other end of the fifth protection circuit 121 is grounded; the fifth schmitt circuit 122 is connected between the lower bridge input port LIN1 and the fifth filter 123, the fifth filter 123 is connected to the fourth level-converting unit 124, and the fourth level-converting unit 124 is connected to the interlock circuit 2.

The fourth protection circuit 111 and the fifth protection circuit 121 are specifically pull-down resistors, and the working principle is the same as that of the first protection circuit 511, the second protection circuit 531, and the third protection circuit 81, which is not described herein again.

The third level shift unit 114 and the fourth level shift unit 124 also operate according to the same principle as the first level shift unit 534.

In the present embodiment, the high voltage driving circuit 3 includes a pulse generator 31, an LDMOS 32, an LDMOS33, a filter 34, a UV detection filter 35, an RS flip-flop 36, and a high voltage driving output circuit 37.

Wherein, a first input terminal of the pulse generator 31 is connected with the interlock circuit 2, a second input terminal of the pulse generator 31 is connected with the low voltage driving circuit 4, a first output terminal of the pulse generator 31 is connected to the gate of the LDMOS 32, and a second output terminal of the pulse generator 31 is connected to the gate of the LDMOS 33; the drain of the LDMOS 32 is connected with one end of a resistor R4, and the source of the LDMOS 32 is grounded; the drain of the LDMOS33 is connected with one end of a resistor R5, and the source of the LDMOS33 is grounded; a first input terminal of the filter 34 is connected between the drain of the LDMOS 32 and the resistor R4, a second input terminal of the filter 34 is connected between the drain of the LDMOS33 and the resistor R5, a first output terminal of the filter 34 is connected to the R terminal of the RS flip-flop 36, and a second output terminal of the filter 34 is connected to the S terminal of the RS flip-flop 36; the other end of the resistor R4 is connected with the VB1 end, and the other end of the resistor R5 is connected with the VB1 end; the UV detection filter 35 is respectively connected with a VB1 terminal and an R terminal of the RS trigger 36; the Q terminal of the RS flip-flop 36 is connected to the high voltage drive output circuit 37.

The high-voltage driving output circuit 37 includes an output pair transistor MOS transistor Q1, a transistor MOS Q2, a resistor R6 and a resistor R7, specifically, a drain of Q1 is connected to a VB1 terminal, a gate of Q1 is connected to a Q terminal of the RS flip-flop 36, a source of Q1 is connected to the resistor R6, the resistor R6 is connected in series with the resistor R7 and then connected to a drain of Q2, a gate of Q2 is connected to the Q terminal of the RS flip-flop 36, a source of Q2 is connected to a VS1 terminal, and a common connection point of the resistor R6 and the resistor R7 is connected to the output terminal HO 1.

The pulse generator 31 receives an upper bridge driving signal transmitted by the upper bridge input circuit 11 through the interlock circuit 2, converts the upper bridge driving signal into a pulse signal, transmits the pulse signal to the filter 34 through the LDMOS 32 and the LDMOS33 to filter out an interference signal, then transmits the pulse signal to the RS flip-flop 36, outputs the pulse signal to a common connection point of the resistor R6 and the resistor R7, and distributes a driving signal to the Q1 and the Q2 through the resistor R6 and the resistor R7.

In the present embodiment, the low voltage driving circuit 4 includes a delay circuit 41, a logic circuit 42 and a low voltage driving output circuit 43, wherein the delay circuit 41 is connected to the interlock circuit 2 and the logic circuit 42, respectively, and the logic circuit 42 is connected to the second input terminal of the pulse generator 31 and the low voltage driving output circuit 43, respectively.

In this embodiment, the delay circuit 41 is used to ensure that the high voltage driving circuit 3 and the low voltage driving circuit 4 can output simultaneously.

Specifically, the logic circuit 42 is a nand gate, an input a of the nand gate is connected to the second input of the pulse generator 31, an input B of the nand gate is connected to the delay circuit 41, and an output Y of the nand gate is connected to the low-voltage driving output circuit 43.

The low-voltage driving output circuit 43 comprises an output pair transistor MOS transistor Q3, a transistor MOS Q4, a resistor R8 and a resistor R9, specifically, the drain of Q3 is connected to the VCC terminal, the gate of Q3 is connected to the output terminal Y of the nand gate, the source of Q3 is connected to the resistor R8, the resistor R8 is connected to the drain of Q4 after being connected in series with the resistor R9, the gate of Q4 is connected to the output terminal Y of the nand gate, the source of Q4 is connected to the NU terminal, and the common connection point of the resistor R8 and the resistor R8 is connected to the output terminal LO 1.

In this embodiment, if the driving signals output by the upper bridge input circuit 11 and the lower bridge input circuit 12 are both high level signals, the interlock circuit 2 locks the upper and lower bridge driving signals, and the corresponding signal output terminals all output low level signals, so as to avoid the output terminals HO1 and LO1 from outputting high levels at the same time, which may cause a short circuit.

Based on the fault error reporting output integrated circuit, the fault output circuits corresponding to the fault types one by one are arranged, when the circuit triggers a fault, the corresponding fault output ports are determined according to the fault types, and the fault signals are output, so that the fault types can be determined, the time for positioning and analyzing the fault is shortened, and the efficiency is improved.

It is to be understood that the above-described embodiments are merely illustrative of some, but not restrictive, of the broad invention, and that the appended drawings illustrate preferred embodiments of the invention and do not limit the scope of the invention. This application is capable of embodiments in many different forms and is provided for the purpose of enabling a thorough understanding of the disclosure of the application. Although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to one skilled in the art that modifications can be made to the embodiments described in the foregoing detailed description, or equivalents can be substituted for some of the features described therein. All equivalent structures made by using the contents of the specification and the drawings of the present application are directly or indirectly applied to other related technical fields and are within the protection scope of the present application.

Claims

1. A fault error reporting output integrated circuit, comprising:

the fault detection circuit comprises a signal input circuit, an interlocking circuit, a high-voltage driving circuit, a low-voltage driving circuit, a fault detection circuit, an error reporting circuit and fault output circuits corresponding to fault types one to one;

2. The fault error reporting output integrated circuit of claim 1, wherein the fault detection circuit comprises at least two of an under-voltage detection circuit, a temperature detection circuit, and an over-current detection circuit.

3. The fault error reporting output integrated circuit of claim 2, wherein when the fault detection circuit comprises an under-voltage detection circuit, a temperature detection circuit, and an over-current detection circuit, the fault output port comprises a first fault port, a second fault port, and a third fault port, wherein:

4. The fault error reporting output integrated circuit of claim 3, wherein the fault output circuit comprises an over-current signal receiving circuit, a first output circuit, an over-temperature signal receiving circuit, a second output circuit, an under-voltage signal receiving circuit, a third output circuit, a first diode, and a second diode, wherein:

5. The fault-reporting output integrated circuit of claim 4, wherein the over-current signal receiving circuit is a first resistor, the first output circuit is a first MOS transistor, the over-temperature signal receiving circuit is a second resistor, the second output circuit is a second MOS transistor, the under-voltage signal receiving circuit is a third resistor, and the third output circuit is a third MOS transistor, wherein:

6. The fault error reporting output integrated circuit of claim 2, wherein the brown-out detection circuit comprises a first protection circuit, a first schmitt circuit, a first filter, and a brown-out detection unit, wherein:

7. The fault error reporting output integrated circuit of claim 2, wherein the over-current detection circuit comprises a second protection circuit, a second schmitt circuit, a second filter, and a first level shift unit, wherein:

8. The fault error reporting output integrated circuit of claim 1, further comprising an enable circuit coupled to the error reporting circuit for determining whether the received voltage signal is below a predetermined threshold, and if so, generating a low level signal for transmission to the error reporting circuit.

9. The fault-reporting output integrated circuit of claim 8, wherein the enabling circuit comprises a third protection circuit, a third schmitt circuit, a third filter, and a second level shifting unit, wherein:

the third filter is connected to the second level conversion unit and is used for filtering spike voltage signals in the low level signals;

10. The fault-reporting output integrated circuit of claim 1, wherein the signal input circuit comprises an upper bridge input circuit and a lower bridge input circuit;