CN114005907A

CN114005907A - A kind of manufacturing method of Topcon battery

Info

Publication number: CN114005907A
Application number: CN202111332211.1A
Authority: CN
Inventors: 白玉磐; 陈园; 付少剑; 张明明
Original assignee: Shangrao Jietai New Energy Technology Co ltd
Current assignee: Shangrao Jietai New Energy Technology Co ltd
Priority date: 2021-11-11
Filing date: 2021-11-11
Publication date: 2022-02-01

Abstract

The invention discloses a manufacturing method of a Topcon battery, which includes S1, alkali-texturing an N-type single crystal silicon wafer; S2, performing boron diffusion on the front surface of the N-type single-crystal silicon wafer after the alkali-texturing; S3, using The alkaline solution with additives is used for cleaning, and the area of the oxide layer is directionally protected and isolated from the reaction of OH- and silicon oxide. Backside polishing; S4, after removing the BSG layer on the front side, the surface grows an ultra-thin silicon dioxide layer, a doped amorphous silicon film layer and a mask layer in turn; S5, groove the front side to obtain a slotted line, which is used for the slotted line It is used to isolate the surrounding inner area from the outer back side plating on the front side; S6, perform double-sided coating to form a front side coating layer and a back side coating layer; S7, screen printing silver paste, and then form electrodes by sintering. Through the laser treatment, the isolation reduces the leakage, and the current wet de-wound plating process is omitted, and the manufacturing efficiency of the battery is improved.

Description

Manufacturing method of Topcon battery

Technical Field

The invention relates to the technical field of photovoltaic cells, in particular to a manufacturing method of a Topcon cell.

Background

TOPCon cells (Tunnel Oxide Passivated Contacts) are tunneling oxidation Passivated contact cells, and the initial preparation method is as follows:

an N-type silicon wafer is adopted, firstly, an ultrathin oxide layer (1-1.5nm) is grown on the back surface of the silicon wafer by a chemical method to form a tunneling layer, secondly, a phosphorus-doped amorphous silicon film (20nm) is deposited on the oxide layer to be used as a back field, and then, the annealing is carried out at high temperature, so that the deposited amorphous silicon film is crystallized to strengthen the passivation effect. The open-circuit voltage of the battery reaches 700mV, the fill factor is 82%, the efficiency reaches 24%, and the efficiency of the double-sided battery reaches 26.0% by 2021, 4 months and 28 days.

The key point of the passivation contact technology is that depending on doping, one carrier (e.g., electrons) can pass through a structural layer (i.e., contact effect), and the other carrier (e.g., holes) is prevented from passing through (i.e., passivation effect).

The PERC battery preparation process is compared with several TOPCon battery preparation processes. Topcon only needs to add back passivation film preparation and cleaning equipment at PERC basic upgrading, and the added equipment is slightly different according to different technical routes.

The LPCVD scheme is relatively early and mature, but the yield is greatly influenced because the plating winding is relatively serious, and on the other hand, the yield of the LPCVD in-situ doping route is low, which are two important factors restricting the industrialization of the LPCVD. The PECVD has the advantages of high in-situ doping deposition speed, slight plating winding and the like, and a plurality of enterprises are in industrial development. The shape and size of the plating can be controlled to a great extent by depositing poly on the PECVD route, but due to the fact that the poly is doped in situ in the PECVD mode, the doped poly is deposited on the side edge, PN junctions on the front side and the back side can be conducted, electric leakage is generated, and therefore the plating is still required to be removed for cleaning after deposition.

Disclosure of Invention

The invention aims to provide a manufacturing method of a Topcon battery, which reduces electric leakage. The yield of the product is improved.

In order to solve the above technical problems, an embodiment of the present invention provides a method for manufacturing a Topcon battery, including

S1, alkali texturing is carried out on the N-type monocrystalline silicon piece;

s2, performing boron diffusion on the front side of the N-type monocrystalline silicon wafer subjected to alkali texturing;

s3, cleaning the N-type monocrystalline silicon wafer by using an alkaline solution with an additive, directionally protecting the area of an oxide layer to isolate OH & lt- & gt from reacting with silicon oxide, accelerating the OH & lt- & gt reaction on the area without the oxide layer, increasing the corrosion rate of the {111}/{100} surface, and realizing back polishing;

s4, after removing the BSG layer on the front surface of the N-type monocrystalline silicon wafer, sequentially growing an ultrathin silicon dioxide layer, an amorphous silicon-doped thin film layer and a mask layer on the surface of the N-type monocrystalline silicon wafer;

s5, grooving the front surface of the N-type monocrystalline silicon wafer to obtain a grooving line, wherein the grooving line is used for isolating the surrounded inner side region and the outer side of the back surface of the N-type monocrystalline silicon wafer on the front surface in a plating manner;

s6, performing double-sided coating on the N-type monocrystalline silicon wafer to form a front coating layer and a back coating layer;

and S7, screen-printing silver paste on the N-type monocrystalline silicon piece, and sintering to form an electrode.

Wherein the S1 includes:

and texturing the N-type monocrystalline silicon wafer by adopting NaOH solution or KOH solution.

Wherein the S1 includes:

primarily polishing in NaOH solution or KOH solution with the temperature of 70-75 ℃ and the mass concentration of 3-5% to remove a damaged layer on the surface of the N-type monocrystalline silicon piece;

texturing the N-type monocrystalline silicon wafer in NaOH solution or KOH solution alkali liquor with additives at the temperature of 80-85 ℃, and forming textured surfaces on two surfaces of the N-type monocrystalline silicon wafer;

cleaning the N-type monocrystalline silicon wafer in an acid solution to remove surface impurities;

wherein, the thinning amount of the N-type monocrystalline silicon piece texturing is 0.5-0.6g, and the reflectivity is controlled at 11-12%.

Wherein, between the S2 and the S3, further comprising:

and cleaning the N-type monocrystalline silicon wafer by adopting an HF solution to remove the BSG layer on the back surface.

Wherein, between the S4 and the S5, further comprising:

and annealing the N-type monocrystalline silicon wafer in the nitrogen atmosphere at 850-950 ℃, activating phosphorus atoms in the doped amorphous silicon thin film layer, and propelling the phosphorus atoms to further crystallize the amorphous silicon in the doped amorphous silicon thin film layer and convert the amorphous silicon into polycrystalline silicon.

And growing the ultrathin silicon dioxide layer on the surface of the N-type monocrystalline silicon wafer by adopting an atomic layer deposition mode, or growing the ultrathin silicon dioxide layer on the surface of the N-type monocrystalline silicon wafer by adopting a thermal oxidation mode.

And depositing the doped amorphous silicon thin film layer on the surface of the N-type monocrystalline silicon wafer by adopting PECVD or MOCVD.

The thickness of the ultrathin silicon dioxide layer is 1-2nm, and the thickness of the amorphous silicon thin film layer is 80-120 nm.

Wherein the distance between the grooving line and the positive edge of the N-type monocrystalline silicon piece is 0.5-1 mm.

Wherein the S6 includes:

depositing a front passivated aluminum oxide layer and a front silicon nitride layer on the front surface of the N-type monocrystalline silicon wafer as front coating layers;

depositing a back silicon nitride layer on the back of the surface of the N-type monocrystalline silicon wafer as a back film coating layer;

wherein the thickness of the front passivation aluminum oxide layer and the thickness of the back tunneling aluminum oxide layer are 4-5nm, the thickness of the front silicon nitride layer is 70-80nm, and the thickness of the back silicon nitride layer is 80-85 nm.

Compared with the prior art, the manufacturing method of the Topcon battery provided by the embodiment of the invention has the following advantages:

according to the manufacturing method of the Topcon battery provided by the embodiment of the invention, before the deposition of the coating layer, the front surface of the N-type monocrystalline silicon wafer is grooved to obtain the grooved line, and the grooved line is used for isolating the surrounded inner side area from the outside of the back surface of the N-type monocrystalline silicon wafer on the front surface in a winding and plating way, so that the electric leakage is reduced. Therefore, the existing wet method decoating plating process can be saved, and the manufacturing efficiency of the battery is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic flow chart illustrating a process of a specific embodiment of a method for manufacturing a Topcon cell according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic step flow diagram of a specific implementation of a manufacturing method of a Topcon battery according to an embodiment of the present invention.

In one embodiment, the Topcon battery is manufactured by a method comprising

s4, after removing the BSG layer on the front surface of the N-type monocrystalline silicon wafer, sequentially growing an ultrathin silicon dioxide layer, an amorphous silicon-doped thin film layer and a mask layer on the surface of the N-type monocrystalline silicon wafer; after the back polishing is finished, the BSG layer formed by the diffusion of the boron on the front surface is removed, so that in the polishing process, the alkali solution protects the front surface of the silicon wafer due to the existence of the BSG layer on the front surface, and the front surface cannot be polished.

Before the film coating layer is deposited, grooving is carried out on the front side of the N-type monocrystalline silicon wafer to obtain a grooving line, and the grooving line is used for isolating the surrounded inner side area and the outer side of the back side of the N-type monocrystalline silicon wafer on the front side in a winding and plating mode, so that electric leakage is reduced. Thereby saving the prior wet method decoating and plating process and improving the manufacturing efficiency of the battery

In a crystalline silicon solar cell, reflection of front surface light is considered to be an important factor influencing efficiency, and the surface of the solar cell is generally made into a textured structure by adopting a surface texturing (texturing) technology to reduce reflection of the surface light, so that the process can reduce light reflectivity, improve short-circuit current (Isc) and finally improve photoelectric conversion efficiency of the cell.

Single crystal silicon texturing takes advantage of the expensive anisotropic etch characteristics. The anisotropic etching characteristics mean that different crystal planes of silicon have different etching rates. The most common anisotropic corrosive agent of silicon is NaOH or KOH, different corrosion speeds on different crystal faces of the silicon are realized by controlling the concentration of alkali liquor, a pyramid-shaped structure is formed on the silicon surface, and the reflection of incident light is realized.

The texturing process is not limited in this application, and in one embodiment, the S1 includes:

To further improve the texturing quality such that the texturing process becomes standardized, in one embodiment, the S1 includes:

The reaction equation in the alkaline solution is

Si+6OH-→SiO32-+3H2O+4e

4H++4e→2H2

The overall reaction equation is

Si+2OH-+H2O＝SiO32-+2H2

For a silicon wafer with the surface in the (100) crystal orientation, due to different reaction rates of different crystal orientations, an illustrated structure is obtained by utilizing the anisotropic etching of silicon in alkali, the reaction is finally stopped on a (111) plane with the lowest reaction speed, four intersected (111) planes form four side surfaces of a pyramid, and thus the texture of the monocrystalline silicon is generally called as a pyramid structure,

specifically, in conventional monocrystal texture etching equipment, firstly, a damaged layer is primarily removed in a KOH solution with the temperature of 75 ℃ and the concentration of 3%, then, texture etching is performed in an alkali liquor and additive system with the temperature of 85 ℃, texture surfaces are formed on two sides of a silicon wafer, and then, the silicon wafer is cleaned in an acid solution to remove surface impurities; generally, the thinning amount of the monocrystalline silicon texturing process is controlled to be 0.5-0.6g, and the reflectivity is controlled to be 11-12%.

In the present application, after the texturing process of the silicon wafer is completed, the front-side boron diffusion is required, and the process is not limited in the present application.

The deposition and diffusion of B in silicon is an oxidation and diffusion process, and the main reaction is BCl₃And O₂React to form boron oxide (B)₂O₃) Chemical deposition on the surface of a silicon wafer: 4BCl₃+3O₂＝2B₂O₃+6Cl₂(ii) a Reacting boron oxide with Si to generate silicon oxide and B atoms: 2B₂O₃+3Si＝3SiO₂+4B。B₂O₃With the SiO formed₂The mixed materials are mixed and deposited on the surface of a silicon wafer to form borosilicate glass (BSG), and deposited B atoms can diffuse into Si to form a BSG layer on the surface of the silicon wafer.

In the application, because a back BSG layer may be formed during the front boron diffusion, the back BSG layer needs to be removed, generally, the back highly-compounded non-BSG layer exists after the silicon wafer diffusion is removed mainly through acid cleaning (HF), and the front BSG layer remains.

HF is a colorless, transparent liquid with relatively weak acidity, volatility and strong corrosivity, but HF has a very important property in that it can dissolve silica. This property of HF is mainly used in cleaning and etching processes in semiconductor manufacturing to remove the BSG layer (silicon dioxide layer) from the silicon wafer surface.

The main reactions at the back of the silicon wafer are as follows:

6HF+SiO₂＝H₂[SiF₆]+H₂O

the basic process of removing BSG is as follows: protecting water film → acid washing to remove BSG on back face → spraying pure water → drying.

In one embodiment, between the S2 and the S3, further comprising:

The concentration of the HF solution, the duration of the cleaning, the solution temperature, and the like are not limited in the present application.

In order to further improve the performance of the device, in the present application, after the front side boron diffusion is completed, the back side polishing needs to be performed, specifically, the back side polishing is mainly performed by alkali polishing, and the present application does not limit the specific process.

The process mainly carries out directional protection on the area of the silicon wafer with the oxide layer through an alkali and additive system to isolate OH < - > from reacting with silicon oxide; accelerating OH & lt- & gt to react with the area without the oxide layer (the back of the silicon wafer), increasing the corrosion rate of the {111}/{100} surface, and polishing; the alkali polishing can obtain good back surface smoothness, greatly reduce the specific surface area of the back surface, increase the reflectivity of the back surface and improve the passivation effect of the back surface. And the N-type diffusion layer on the back can be removed, the formation of a P + layer is promoted, and the minority carrier lifetime is prolonged.

The silicon wafer back side reaction is as follows:

2NaOH+H2O+Si＝Na₂SiO₃+2H₂↑

in order to further improve the performance of the battery cell, so that the doped ions are diffused more uniformly, in one embodiment, between S4 and S5, the method further includes:

Through adopting under the high temperature nitrogen atmosphere, right N type monocrystalline silicon piece carries out annealing treatment, activates and impels the phosphorus atom in the doping amorphous silicon thin layer for the phosphorus atom can diffuse more depths, avoids appearing the too high and too low condition of depth carrier concentration of local carrier concentration, improves the performance of product, simultaneously, can also make amorphous silicon in the doping amorphous silicon thin layer further crystallizes, will amorphous silicon turns into polycrystalline silicon to improve the crystallization quality of the silicon atom layer in the doping amorphous silicon thin layer, go on and improve the quality of whole battery piece.

The present application is not limited to the nitrogen atmosphere, and other gases, such as inert gases, etc., may be used, and the pressure, temperature and duration to be maintained are not limited, and the process conditions may be used, or other process conditions may be used, which are not limited in the present application.

This application is owing to need prepare the Topcon structure, consequently need prepare ultra-thin silicon dioxide layer upon layer not do the zinc ingot to preparation process and specific thickness, generally adopt atomic layer deposition's mode to be in N type monocrystalline silicon piece surface growth ultra-thin silicon dioxide layer, or adopt the mode of thermal oxidation to be in N type monocrystalline silicon piece surface growth ultra-thin silicon dioxide layer.

The ultrathin silicon dioxide layer is grown on the surface of the N-type monocrystalline silicon wafer in an atomic layer deposition mode, and the method has the advantages that the deposition thickness can be accurately controlled, and has the defects of low deposition speed and high process cost. The advantage of using thermal oxidation is that the deposition rate is fast, but the accuracy is low. And atomic layer deposition is to increase ultra-thin silica layer on original basis, and well thickness can increase, and the thermal oxidation is to form ultra-thin silica layer through oxidizing on the basis of original silicon chip, and thickness can not increase, and the staff can select suitable ultra-thin silica layer mode according to technology precision and needs.

And the doped amorphous silicon thin film layer rich in forming Topcon is generally deposited on the surface of the N-type monocrystalline silicon wafer by adopting PECVD or MOCVD.

The structure of each functional layer of the Topcon is not limited in the application, and generally, the thickness of the ultrathin silicon dioxide layer is 1-2nm, and the thickness of the amorphous silicon thin film layer is 80-120 nm.

In one embodiment, for growing an ultra-thin silicon dioxide layer, depositing an amorphous silicon thin film:

the first scheme is as follows: the first step is atomic layer deposition, the nature of the first step has self-limiting property and saturation, the first step is reaction deposition silicon source, the silicon source belongs to organosilicon Si (CH) chemisorption on the surface of a silicon wafer, saturation is carried out after a layer is paved, and no redeposition is carried out, at the moment, -O-Si (CH) is generated, then argon gas sweeps out (sweeps) excessive silicon source and by-product, the third step is carried out, the introduced oxygen gas is electrified through a radio frequency power supply to ionize the oxygen gas into plasma O to react with Si (CH) deposited in the first step, silicon oxide is generated, the first step is self-saturated due to the saturation of the chemical adsorption of the silicon source, the silicon source chemisorbed in the first step cannot react, and the fourth step is carried out, argon gas blows out the excessive product and the by-product from a cavity, and the steps are repeated for several times, so that a 1-2nm tunneling SiO2 layer is generated. Adopting a PECVD mode, using Ar carrying SiH4 and PH3 to deposit an 80-120nm doped amorphous silicon film on the surface of a silicon wafer under the condition of plasma starting, and then using Ar carrying N2O to deposit a layer of mask about 1nm on the amorphous silicon film under the condition of plasma starting.

Scheme II: by adopting a thermal oxidation mode, oxygen is introduced at the temperature of 600-900 ℃, and a 1-2nmSiO2 tunneling layer is formed on the surface of the silicon wafer. Then, doped polysilicon is produced by adopting a PECVD mode, which comprises the following steps: firstly, using H2 to carry SiH4 and PH3, and depositing an 80-120nm doped amorphous silicon film on the surface of a silicon wafer under the condition of starting plasma, and introducing CH4 gas at the beginning of deposition in order to improve film explosion. A mask is then deposited over the amorphous silicon film with the plasma turned on with N2O turned on.

The core of the application is that a grooving line is used for surrounding an inner side region and an outer side in a grooving mode, the back of the N-type monocrystalline silicon piece is isolated in a positive winding and plating mode, the grooving and specific grooving parameters are not limited at the time of the grooving, and generally, the distance between the grooving line and the positive edge of the N-type monocrystalline silicon piece is 0.5-1 mm.

In one embodiment, the front surface of the cell is subjected to a grooving process by using laser with the wavelength of 532nm, and the grooving line is controlled to be 1mm away from the edge, namely within the back surface electroplating range, so that the isolation purpose is achieved.

In the application, the front side and the back side need to be touched before the final electrode preparation, and the application limits the type, the thickness and the coating mode of the film layer.

In one embodiment, the S6 includes:

preferably, the thickness of the front passivation aluminum oxide layer and the thickness of the back tunneling aluminum oxide layer are 4-5nm, the thickness of the front silicon nitride layer is 70-80nm, and the thickness of the back silicon nitride layer is 80-85 nm.

One is in the embodiment:

the first step is atomic layer deposition, the nature of the first step is self-limiting and saturable, the first step is reaction to deposit a silicon source, TMA is chemically adsorbed on the surface of a silicon wafer, saturation is carried out after a layer is paved, and redeposition cannot occur, at the moment, -O-Al-is generated, -then argon gas is swept out (swept) the redundant TMA and byproducts, the third step is that the introduced oxygen gas is electrified by a radio frequency power supply to be ionized into plasma O to react with-Al-deposited in the first step, so that alumina is generated, because the first step is the saturable of the silicon source chemical adsorption, the first step is self-saturable, the silicon source chemically adsorbed in the first step cannot react after being oxidized, and the fourth step is that the argon gas blows the redundant products and byproducts out of a cavity, and the steps are repeated for more than several times to generate a 4-5nm tunneling alumina layer. Introducing SiH4 and NH3 in a PECVD mode under the condition of starting plasma, and depositing 70-80nm of silicon nitride on the surface of a silicon wafer to serve as a front antireflection layer of the cell; and (3) introducing SiH4 and NH3 on the back of the silicon wafer by using PECVD equipment under the condition of starting plasma, and depositing 80-85nm of silicon nitride on the surface of the silicon wafer to serve as a back antireflection layer of the cell.

And finally, respectively printing silver paste on the back surface and the front surface of the battery by using a screen printing mode. The silver grid lines are printed on the back surface of the battery, and the silicon nitride passivation layer is deposited on the back surface of the battery, so that the shading proportion of a back electrode is reduced, the light inlet quantity of the back surface of the battery piece is improved, and the battery has the characteristic of double-sided power generation.

It should be noted that, in the present application, the outline of the front screen pattern is controlled within the laser grooving pattern.

And (3) sintering: the process of this step is intended to connect the electrodes on the silicon wafer together by the process of high temperature alloying. The process principle is as follows: the silicon atoms originally dissolved in the metal material of the electrode are crystallized out again in solid state, i.e. an epitaxial layer is grown on the interface between the metal and the crystal. If the epitaxial layer contains a sufficient amount of impurity components having the same conductivity type as the original crystalline material, an ohmic contact formed by alloying is obtained; the PN junction formed by the alloying process is obtained if the crystalline layer contains a sufficient amount of impurity components that are hetero-shaped in conductivity type with the original crystalline material. The sintering function and purpose are that the electrode printed on the silicon chip is sintered into a cell at high temperature, and finally the electrode and the silicon chip form ohmic contact, so that the open-circuit voltage and the fill factor of the cell are improved by 2 key factor parameters, the contact of the electrode has resistance characteristics, and the purpose of producing the cell with high conversion efficiency is achieved.

Set up the fluting through the front and obtain the fluting line in this application, realize keeping apart, reduce to go around the use of plating process chemicals, reduce the piece and improve the yield. The investment of wet decoating equipment can be saved.

In summary, in the manufacturing method of the Topcon cell provided by the embodiment of the invention, before the deposition of the plating layer, the front surface of the N-type monocrystalline silicon wafer is grooved to obtain the grooved lines, and the grooved lines are used for isolating the surrounded inner region from the outside of the back surface of the N-type monocrystalline silicon wafer on the front surface in the plating process, so as to reduce the leakage current. Therefore, the existing wet method decoating plating process can be saved, and the manufacturing efficiency of the battery is improved.

The manufacturing method of the Topcon battery provided by the invention is described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims

1. a manufacture method of Topcon battery, is characterized in that, comprises

S1, alkali-texturing the N-type single crystal silicon wafer;

S2, performing boron diffusion on the front surface of the N-type single crystal silicon wafer after alkali texturing;

S3, the N-type single crystal silicon wafer is cleaned with an alkaline solution with additives, the area of the oxide layer is directionally protected and isolated from the reaction of OH- and silicon oxide, and the reaction of OH- is accelerated in the area without the oxide layer, increasing { 111}/{100} surface corrosion rate to achieve backside polishing;

S4, after removing the BSG layer on the front of the N-type single crystal silicon wafer, grow an ultra-thin silicon dioxide layer, a doped amorphous silicon thin film layer and a mask layer on the surface of the N-type single crystal silicon wafer in sequence;

S5 , the front side of the N-type single crystal silicon wafer is slotted to obtain a slotted line, and the slotted line is used to isolate the enclosed inner area from the outer side of the N-type single crystal silicon wafer. ;

S6, performing double-sided coating on the N-type single crystal silicon wafer to form a front coating layer and a back coating layer;

S7, screen printing silver paste on the N-type single crystal silicon wafer, and then forming electrodes by sintering.

2. The manufacturing method of the Topcon battery as claimed in claim 1, wherein the S1 comprises:

The N-type single crystal silicon wafer is textured by using a NaOH solution or a KOH solution.

3. The manufacturing method of the Topcon battery as claimed in claim 2, wherein the S1 comprises:

Perform initial polishing in a NaOH solution or a KOH solution with a mass concentration of 3% to 5% at a temperature of 70 to 75° C. to remove the damaged layer on the surface of the N-type single crystal silicon wafer;

The N-type single crystal silicon wafer is textured in NaOH solution or KOH solution alkali solution with additives at a temperature of 80-85°C, and textured surfaces are formed on both sides of the N-type single crystal silicon wafer;

cleaning the N-type single crystal silicon wafer in an acidic solution to remove surface impurities;

Wherein, the thinning amount of the N-type single crystal silicon wafer for texturing is 0.5-0.6 g, and the reflectivity is controlled at 11-12%.

4. The method for manufacturing a Topcon battery according to claim 3, characterized in that, between said S2 and said S3, further comprising:

The N-type single crystal silicon wafer is cleaned with HF solution to remove the BSG layer on the backside.

5. The method for manufacturing a Topcon battery according to claim 4, wherein between the S4 and the S5, the method further comprises:

Under a nitrogen atmosphere at 850-950° C., the N-type single crystal silicon wafer is annealed to activate the phosphorus atoms in the doped amorphous silicon thin film layer and push the phosphorus atoms, so that the doped non-crystalline silicon The amorphous silicon in the crystalline silicon thin film layer is further crystallized to convert the amorphous silicon into polycrystalline silicon.

6. The method for manufacturing a Topcon battery according to claim 5, wherein the ultra-thin silicon dioxide layer is grown on the surface of the N-type single crystal silicon wafer by atomic layer deposition, or by thermal oxidation. The ultra-thin silicon dioxide layer is grown on the surface of the N-type single crystal silicon wafer.

7 . The method for manufacturing a Topcon cell according to claim 6 , wherein the doped amorphous silicon thin film layer is deposited on the surface of the N-type single crystal silicon wafer by PECVD or MOCVD. 8 .

8 . The method for manufacturing a Topcon battery according to claim 7 , wherein the thickness of the ultra-thin silicon dioxide layer is 1-2 nm, and the thickness of the amorphous silicon thin film layer is 80-120 nm. 9 .

9 . The method for manufacturing a Topcon battery according to claim 8 , wherein the distance between the slot line and the positive edge of the N-type single crystal silicon wafer is 0.5-1 mm. 10 .

10. The method for manufacturing a Topcon battery according to claim 9, wherein the S6 comprises:

A front-side passivation aluminum oxide layer and a front-side silicon nitride layer are deposited on the front side of the surface of the N-type single crystal silicon wafer as a front-side coating layer;

A backside silicon nitride layer is deposited on the surface and backside of the N-type single crystal silicon wafer as a backside coating layer;

The thickness of the front passivation aluminum oxide layer and the backside tunneling aluminum oxide layer is 4-5 nm, the thickness of the front silicon nitride layer is 70-80 nm, and the thickness of the back silicon nitride layer is 70-80 nm. The thickness is 80-85nm.