CN114005826B

CN114005826B - Preparation method of semiconductor device and semiconductor device

Info

Publication number: CN114005826B
Application number: CN202111274291.XA
Authority: CN
Inventors: 石艳伟
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2025-09-16
Anticipated expiration: 2041-10-29
Also published as: CN114005826A

Abstract

The present invention discloses a method for preparing a semiconductor device and a semiconductor device, comprising forming a substrate, forming a first gate and a second gate located on the substrate, and forming a first sidewall and a second sidewall on the sidewalls of the first gate and the second gate, respectively. A high-voltage well region and a low-voltage well region are formed in the substrate, the first gate and the second gate correspond to the high-voltage well region and the low-voltage well region, respectively, and the height of the first gate is greater than the height of the second gate, and the width of the first sidewall is greater than the width of the second sidewall. Since the height of the first gate and the width of the first sidewall corresponding to the high-voltage well region are larger, the performance of the device can be improved, such as reducing damage to the gate oxide layer and hot carrier effects. At the same time, since the height of the second gate and the width of the second sidewall corresponding to the low-voltage well region are smaller, the speed of the device can be increased and the area of the device can be reduced.

Description

Preparation method of semiconductor device and semiconductor device

Technical Field

The present invention relates generally to electronic devices and, more particularly, to a method of manufacturing a semiconductor device and a semiconductor device.

Background

A low voltage metal oxide semiconductor transistor (Low Voltage Metal Oxide Semiconductor, LVMOS) and a high voltage metal oxide semiconductor transistor (How Voltage Metal Oxide Semiconductor, HVMOS) are present in the complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, COMS) at the same time.

Because the ion implantation energy of the low doping structure forming the HVMOS is larger, the gate cannot meet certain requirements, so that the gate is penetrated to damage the gate oxide layer, and meanwhile, the widths of the side walls on two sides of the gate cannot meet certain requirements, so that hot carrier injection (Hot Carrier Injection, HCI) effect is caused, and further the performance of the device is damaged. However, for LVMOS, too thick a gate reduces the device speed and too wide a sidewall reduces the device speed. Because the side wall of the LVMOS needs to be separated from the contact point on the grid electrode by a certain distance, the wider the side wall is, the more limited the space of the contact point is under the condition of a certain area of the device, and if the side wall is kept separated from the contact point by a certain distance, the area of the device is increased due to the fact that the width of the side wall is increased, the area of the device is lost due to the fact that the width of the side wall of the LVMOS is too wide.

However, for the memory, as the memory density increases, it is an unavoidable requirement to reduce the area of CMOS.

Disclosure of Invention

The invention aims to provide a preparation method of a semiconductor device and the semiconductor device, aiming at forming double side walls with different heights and different widths so as to give consideration to the gate height and the side wall width of HVMOS and LVMOS, thereby improving the performance of the device and reducing the area of the device.

In one aspect, the present invention provides a method for manufacturing a semiconductor device, including:

providing a substrate, wherein a high-voltage well region and a low-voltage well region which are arranged at intervals are formed in the substrate;

forming a first grid electrode and a second grid electrode which are positioned on the substrate, wherein the first grid electrode corresponds to the high-voltage well region, the second grid electrode corresponds to the low-voltage well region, and the height of the first grid electrode is larger than that of the second grid electrode;

And forming a first side wall positioned on the first grid side wall and a second side wall positioned on the second grid side wall, wherein the width of the first side wall in the direction away from the first grid side wall is larger than that of the second side wall in the direction away from the second grid side wall.

Further preferably, the step of forming a first gate and a second gate on the substrate includes:

forming a gate layer on the substrate, wherein the gate layer is positioned above the high-voltage well region and the low-voltage well region;

Removing part of the gate layer above the low-voltage well region to enable the height of the gate layer above the low-voltage well region to be smaller than that of the gate layer above the high-voltage well region;

And forming the first grid electrode corresponding to the high-voltage well region and the second grid electrode corresponding to the low-voltage well region by adopting a photoetching process, wherein the height of the first grid electrode is larger than that of the second grid electrode.

Further preferably, the width of the first gate is greater than the width of the second gate.

Further preferably, the step of forming a first sidewall located on the first gate sidewall and a second sidewall located on the second gate sidewall includes:

Forming an insulating layer covering the first gate, the second gate and the substrate;

Etching the insulating layers to form a first insulating layer positioned on the side wall of the first grid electrode and a second insulating layer positioned on the side wall of the second grid electrode, wherein the first side wall comprises the first insulating layer, and the second side wall comprises the second insulating layer.

Further preferably, the widths of the first side wall and the second side wall are gradually reduced along the direction away from the substrate.

Further preferably, the step of forming a first sidewall located on the first gate sidewall and a second sidewall located on the second gate sidewall further includes:

Forming a first oxide layer and a second oxide layer respectively covering the first gate electrode and the second gate electrode before the step of forming the insulating layer;

Forming a first nitride layer on the outer surface of the first oxide layer on the side wall of the first grid electrode, and forming a second nitride layer on the outer surface of the second oxide layer on the side wall of the second grid electrode;

the first side wall comprises the first oxide layer, the first nitride layer and the first insulating layer which are positioned on the side wall of the first grid electrode, and the second side wall comprises the second oxide layer, the second nitride layer and the second insulating layer which are positioned on the side wall of the second grid electrode.

forming a third oxide layer, a third nitride layer and a fourth oxide layer which cover the horizontal surfaces and the side walls of the first grid electrode and the second grid electrode in sequence;

Removing the fourth oxide layer on horizontal surfaces of the first gate electrode and the second gate electrode;

Removing the fourth oxide layer on the side wall of the second grid electrode;

removing the third nitride layer on horizontal surfaces of the first gate electrode and the second gate electrode;

The first side wall comprises a first oxide layer, a first nitride layer, a third oxide layer, a third nitride layer, a fourth oxide layer and a first insulating layer which are sequentially positioned on the side wall of the first grid electrode, and the second side wall comprises a second oxide layer, a second nitride layer, a third oxide layer, a third nitride layer and a second insulating layer which are sequentially positioned on the side wall of the second grid electrode.

Further preferably, the method further comprises:

forming a first source region and a first drain region in the high-voltage well region;

Forming a second source region and a second drain region in the low-voltage well region;

After the steps of forming the first gate and the second gate, forming a first lightly doped region and a second lightly doped region in the high voltage well region adjacent to the first source region and the first drain region, respectively.

In another aspect, the present invention provides a semiconductor device comprising:

a substrate, wherein a high-voltage well region and a low-voltage well region are formed in the substrate at intervals;

The first grid electrode and the second grid electrode are positioned on the substrate, the first grid electrode corresponds to the high-voltage well region, the second grid electrode corresponds to the low-voltage well region, and the height of the first grid electrode is larger than that of the second grid electrode;

The first side wall is located on the first grid side wall, the second side wall is located on the second grid side wall, and the width of the first side wall in the direction away from the first grid side wall is larger than the width of the second side wall in the direction away from the second grid side wall.

Further preferably, the first side wall includes a first insulating layer located on the first gate side wall, the second side wall includes a second insulating layer located on the second gate side wall, and widths of the first side wall and the second side wall are gradually reduced along a direction away from the substrate, respectively.

Further preferably, the first side wall includes a first oxide layer and a first nitride layer sequentially located on the side wall of the first gate and the first insulating layer, and the second side wall includes a second oxide layer, a second nitride layer and the second insulating layer sequentially located on the side wall of the first gate.

Further preferably, the first side wall includes the first oxide layer, the first nitride layer, the third oxide layer, the third nitride layer, the fourth oxide layer and the first insulating layer sequentially located on the first gate side wall, and the second side wall includes the second oxide layer, the second nitride layer, the third oxide layer, the third nitride layer and the second insulating layer sequentially located on the second gate side wall.

Further preferably, the method further comprises:

a first source region and a first drain region located in the high-voltage well region;

A second source region and a second drain region located in the low-voltage well region;

And the first lightly doped region and the second lightly doped region are positioned in the high-voltage well region and are respectively adjacent to the first source region and the first drain region.

The invention has the beneficial effects that the preparation method of the semiconductor device and the semiconductor device are provided, and the preparation method comprises the steps of forming a substrate, forming a first grid electrode and a second grid electrode which are positioned on the substrate, and forming a first side wall and a second side wall which are respectively formed on the side wall of the first grid electrode and the side wall of the second grid electrode. The substrate is provided with a high-voltage well region and a low-voltage well region which are arranged at intervals, the first grid electrode and the second grid electrode respectively correspond to the high-voltage well region and the low-voltage well region, the height of the first grid electrode is larger than that of the second grid electrode, and the width of the first side wall is larger than that of the second side wall. The high-voltage well region is provided with a first grid electrode, a second grid electrode and a first side wall, wherein the first grid electrode is arranged on the first side wall, the second grid electrode is arranged on the second side wall, the first side wall is arranged on the second side wall, and the second side wall is arranged on the second side wall.

Drawings

The technical solution and other advantageous effects of the present invention will be made apparent by the following detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

Fig. 2a-2i are schematic structural views of a semiconductor device according to a first embodiment of the present invention during a manufacturing process;

fig. 3 is a schematic flow chart of forming a first sidewall and a second sidewall according to a second embodiment of the present invention;

Fig. 4a to 4e are schematic structural diagrams during the process of forming the first sidewall and the second sidewall according to the second embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another element. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present invention.

It will be understood that when an element is referred to as being "on," "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar fashion.

As used herein, the term "layer" refers to a portion of material that includes regions having a height. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layers may extend over the entire underlying or overlying structure, or may have a range less than the range of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a height less than the height of the continuous structure. For example, the layers may be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along tapered surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductive layers and a contact layer (in which contacts, interconnect lines, and one or more dielectric layers are formed).

As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate, and "vertical" refers to a direction perpendicular to the substrate.

It should be noted that, the illustrations provided in the embodiments of the invention are merely schematic illustrations of the basic concepts of the invention, and only the components related to the invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Referring to fig. 2a-2i, fig. 2a-2i are schematic structural diagrams of a semiconductor device according to a first embodiment of the present invention during a manufacturing process. The preparation method of the semiconductor device comprises the following steps S1-S3.

Please refer to step S1 in fig. 1 and fig. 2a.

Step S1, providing a substrate 10, wherein a high-voltage well region 101 and a low-voltage well region 102 which are arranged at intervals are formed in the substrate 10.

The substrate 10 may be a semiconductor substrate, for example, may be silicon (Si), germanium (Ge), siGe substrate, silicon-on-insulator (Silicon On Insulator, SOI), germanium-on-insulator (Germanium On Insulator, GOI), or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, and may also be a stacked structure, such as Si/SiGe, or the like.

In this embodiment, the substrate 10 may be etched to form an isolation trench, then the isolation trench is filled with an insulating material to form an isolation structure 103, and then the high-voltage well region 101 and the low-voltage well region 102 which are arranged at intervals are formed by performing ion implantation on the substrate 10 using a suitable mask plate, where the isolation structure 103 is used to separate the high-voltage well region 101 and the low-voltage well region 102. The device operation voltage corresponding to the high-voltage well region 101 is higher, and the device operation voltage corresponding to the low-voltage well region 102 is lower. The order of preparation of the high-voltage well region 101 and the low-voltage well region 102 and the isolation structure 103 is not limited by the present embodiment.

Please refer to steps S2-S4 in fig. 1 and fig. 2a-2e.

Step S2, forming a gate layer 12 on the substrate 10, wherein the gate layer 12 is located above the high-voltage well region 101 and the low-voltage well region 102.

In one embodiment, as shown in fig. 2a, step S2 may include forming a gate insulating layer 11 on a substrate 10 using a suitable deposition process, and then depositing a gate layer 12 on the gate insulating layer 11, wherein the gate insulating layer 11 may include silicon oxide and the gate layer 12 may include polysilicon.

Step S3, removing part of the gate layer 12 above the low-voltage well region 102, so that the height of the gate layer 12 above the low-voltage well region 102 is smaller than the height of the gate layer 12 above the high-voltage well region 101.

In a specific embodiment, as shown in fig. 2b, photoresist is spin-coated on the gate layer 12, then a mask is used to pattern the photoresist to form a patterned photoresist layer 13 as shown in fig. 2b, the patterned photoresist layer 13 corresponds to the upper portion of the high-voltage well region 101, and as shown in fig. 2c, the patterned photoresist layer 13 is used to etch the gate layer 12 to remove a portion of the gate layer 12 above the low-voltage well region 102, so that the height of the gate layer 12 above the low-voltage well region 102 is smaller than the height of the gate layer 12 above the high-voltage well region 101, and in particular, the etching depth can be controlled by controlling the etching rate and time, thereby precisely controlling the height of the gate layer 12 above the low-voltage well region 102.

When the photoresist is a positive photoresist, the mask plate has an opening above the corresponding low-voltage well region 102 and the isolation structure 103, and after exposure and development, the photoresist is removed above the corresponding low-voltage well region 102 and the isolation structure 103, i.e. the patterned photoresist layer 13 above the corresponding high-voltage well region 101 is formed.

Step S4, forming the first gate 121 corresponding to the high-voltage well region 101 and the second gate 122 corresponding to the low-voltage well region 102 by photolithography, wherein the height of the first gate 121 is greater than the height of the second gate 122.

In one embodiment, as shown in fig. 2d, a composite hard mask layer 14 and a photoresist layer 15 are sequentially deposited on the etched gate layer 12, wherein the composite hard mask layer includes an amorphous carbon layer (a-C) 141 sequentially formed, and a silicon oxynitride (SiON) layer 142 formed on the surface of the amorphous carbon layer 141, the amorphous carbon layer 141 serves as a light absorption layer, the silicon oxynitride layer 142 serves as an anti-reflection layer, and as shown in fig. 2e, the photoresist layer 15 is exposed and developed by using a mask plate, a patterned hard mask layer is formed by using the photoresist layer 15, and the gate layer 12 is etched by using the patterned hard mask layer to form the first gate 121 and the second gate 122 as shown in fig. 2 e. Preferably, the width of the first gate 121 formed is greater than the width of the second gate 122 by changing the pattern of the mask, so that the process of forming the first gate 121 and the second gate 122 having different widths is simple and does not require additional process steps.

Please refer to step S5 in fig. 1 and fig. 2f-2i.

Step S5, forming a first sidewall 1210 located on the sidewall of the first gate 121 and a second sidewall 1220 located on the sidewall of the second gate 122, where the width of the first sidewall 1210 in the direction away from the sidewall of the first gate 121 is greater than the width of the second sidewall 1220 in the direction away from the sidewall of the second gate 122.

In a specific embodiment, step S5 may include:

1) The first oxide layer 1211 and the second oxide layer 1221 covering the first gate electrode 121 and the second gate electrode 122, respectively, are formed, specifically, an oxide layer may be deposited first and then the oxide layer on the gate insulating layer 11 may be removed to form the first oxide layer 1211 covering the first gate electrode 121 and the second oxide layer 1221 covering the second gate electrode as shown in fig. 2 f.

2) A first nitride layer 1212 is formed on the sidewall of the first gate 121 and located on the outer surface of the first oxide layer 1211, and a second nitride layer 1222 is formed on the sidewall of the second gate 122 and located on the outer surface of the second oxide layer 1221, specifically, the nitride layer may be deposited first, and then the nitride layer located on the horizontal surface may be removed by dry etching (isotropic etching) to form the first nitride layer 1212 and the second nitride layer 1222 as shown in fig. 2 f.

3) As shown in fig. 2h, the insulating layer 16 is formed to cover the first gate electrode 121, the second gate electrode 122 and the substrate 10 (or the gate insulating layer 11), and when the insulating layer 16 is deposited, the insulating layer 16 deposited at the corners of the bottoms of the first gate electrode 121 and the second gate electrode 122 is more and less in a direction away from the substrate 10. Since the height of the first gate electrode 121 is greater than the height of the second gate electrode 122, in order for the insulating layer 16 to cover the first gate electrode 121 higher than the second gate electrode 122, a thicker insulating layer 16 is formed on the sidewall of the first gate electrode 121 than the second gate electrode 122, so that the width of the insulating layer 16 formed gradually decreases in a direction away from the substrate 10, and the insulating layer 16 on the sidewall of the first gate electrode 121 is wider than the insulating layer 16 on the sidewall of the second gate electrode 122 (the corresponding positions of the two are compared, for example, the bottom of the first gate electrode 121 is compared with the bottom of the second gate electrode 122).

4) As shown in fig. 2i, the insulating layer 16 is etched to form a first insulating layer 161 located on a sidewall of the first gate 121 as the first sidewall 1210, and a second insulating layer 162 located on a sidewall of the second gate 122 as the second sidewall 1220, where widths of the first sidewall 1210 and the second sidewall 1220 are gradually reduced in a direction away from the substrate 10, respectively. Specifically, the insulating layer 16 may be etched along the direction perpendicular to the substrate 10 by dry etching, so as to remove the insulating layer 16 on the horizontal surface, leaving the first insulating layer 161 on the sidewall of the first gate 121 and the second insulating layer 162 on the sidewall of the second gate 122, where the first sidewall 1210 includes the first oxide layer 1211, the first nitride layer 1212 and the first insulating layer 161 on the sidewall of the first gate 121, and the second sidewall 1220 includes the second oxide layer 1221, the second nitride layer 1222 and the second insulating layer 162 on the sidewall of the second gate 122. In the etching process, the width of the first sidewall 1210 formed after etching in a direction away from the sidewall of the first gate electrode 121 is greater than the width of the second sidewall 1220 in a direction away from the sidewall of the second gate electrode 122 due to the thicker insulating layer 16 of the sidewall of the first gate electrode 121, and the widths of the first and second sidewalls 1210 and 1220 formed gradually decrease in a direction away from the substrate 10 due to the gradual decrease in width of the insulating layer 16 from the bottom to the top of the gate electrode.

In a modification, the insulating layer 16 may be directly formed, and then the first insulating layer 161 and the second insulating layer 162 may be etched to form the first sidewall 1210 and the second sidewall 1220, respectively, that is, an oxide layer and a nitride layer may not be formed. In this embodiment, the first oxide layer 1211 and the first nitride layer 1212 are formed between the first gate electrode 121 and the first sidewall 1210, so that the first gate electrode 121 can be more effectively protected, and the second oxide layer 1221 and the second nitride layer 1222 are formed between the second gate electrode 122 and the second sidewall 1220, so that the second gate electrode 122 can be more effectively protected.

The method for manufacturing a semiconductor device provided in this embodiment may further include, after forming the high-voltage well region 101 and the low-voltage well region 102, forming a first source region and a first drain region (not shown in the figure) in the high-voltage well region 101, and forming a second source region and a second drain region (not shown in the figure) in the low-voltage well region 102. Further, after forming the first nitride layer 1212 and the second nitride layer 1222 (fig. 2 f), as shown in fig. 2g, photoresist is formed to cover the isolation structure 103 and the low-voltage well region 102, and a first lightly doped region 1011 and a second lightly doped region 1012 are formed in the high-voltage well region 101 adjacent to the first source region and the first drain region, respectively. Specifically, the first lightly doped region 1011 is formed by ion implantation of the high voltage well region 101 beside the first source region, and the second lightly doped region 1012 is formed by ion implantation of the high voltage well region 101 beside the first drain region, and the first lightly doped region 1011 and the second lightly doped region 1012 are formed in the high voltage well region 101, so that the first lightly doped region 1011 and the second lightly doped region 1012 are also subjected to partial voltages, which can prevent HCI effect. Because the ion implantation energy is larger, the thickness of the first gate 121 corresponding to the high-voltage well region 101 is set thicker in this embodiment, so that the first gate 121 can be prevented from being penetrated to damage the gate insulating layer 11, thereby ensuring the performance of the device.

In the method for manufacturing a semiconductor device according to the first embodiment of the present invention, a substrate 10 having a high-voltage well region 101 and a low-voltage well region 102 which are arranged at intervals is formed, and then a first gate 121 and a second gate 122 corresponding to the high-voltage well region 101 and the low-voltage well region 102 are formed on the substrate, and a first sidewall 1210 and a second sidewall 1220 are formed on sidewalls of the first gate 121 and the second gate 122, respectively. Wherein the height of the first gate 121 is greater than the height of the second gate 122, and the width of the first sidewall 1210 is greater than the width of the second sidewall 1220. Because the height of the first gate 121 corresponding to the high-voltage well region 101 is higher, the first gate 121 can be protected from being penetrated and the gate oxide layer can be protected from being damaged when the first lightly doped region 1011 and the second lightly doped region 1012 are formed, and because the width of the first sidewall 1210 of the sidewall of the first gate 121 is larger, the hot carrier injection effect can be reduced. Meanwhile, the height of the second grid electrode 122 and the width of the second side wall 1220 corresponding to the low-voltage well region 102 are smaller, so that the speed of the device can be improved, and the area of the device can be reduced.

Referring to fig. 3, fig. 3 is a schematic flow chart of forming a first sidewall and a second sidewall according to a second embodiment of the present invention. Referring to fig. 4a-4e, fig. 4a-4e are schematic structural diagrams of a process of forming a first sidewall and a second sidewall according to a second embodiment of the present invention. For ease of understanding, the same reference numerals are used for the same structures in this embodiment as in the first embodiment. In this embodiment, the steps of forming the first sidewall and the second sidewall include the following steps S51 to S56.

Step S51, forming a first oxide layer 1211 and a second oxide layer 1221 covering the first gate electrode 121 and the second gate electrode 122, respectively.

Step S52, forming a first nitride layer 1212 on the outer surface of the first oxide layer 1211 on the sidewall of the first gate 121, and forming a second nitride layer 1222 on the outer surface of the second oxide layer 1221 on the sidewall of the second gate 122.

In this embodiment, step S51 is the same as step S5 in the first embodiment, step S52 is 2) in the first embodiment, the process of step S51 and step S52 is not specifically described in this embodiment, and the completed structure is shown in fig. 2f in the first embodiment.

Step S53, forming a third oxide layer 17, a third nitride layer 18 and a fourth oxide layer 19 in sequence, which cover the horizontal surfaces and sidewalls of the first gate electrode 121 and the second gate electrode 122.

On the basis of fig. 2f, a third oxide layer 17, a third nitride layer 18 and a fourth oxide layer 19 are sequentially deposited, and as shown in fig. 4a, the third oxide layer 17, the third nitride layer 18 and the fourth oxide layer 19 cover the horizontal surfaces and sidewalls of the first gate electrode 121 and the second gate electrode 122 and the gate insulating layer 11.

Step S54 is to remove the fourth oxide layer 19 on the horizontal surfaces of the first gate electrode 121 and the second gate electrode 122.

In this embodiment, a dry etching process may be used to etch the fourth oxide layer 19 along a direction perpendicular to the substrate 10 to form a fourth oxide layer 191 on the sidewall of the first gate electrode 121 and a fourth oxide layer 192 on the sidewall of the second gate electrode 122 (as shown in fig. 4 b).

Step S55, removing the fourth oxide layer 192 on the sidewall of the second gate 122 (as shown in fig. 4 c).

In this embodiment, the mask used in step S3 in the first embodiment may be used, and since both step S55 and step S3 are etching the device in the low-voltage well region 102, the number of masks may be saved and the cost may be saved by using the same mask as step S3.

Step S56 is to remove the third nitride layer 18 on the horizontal surfaces of the first gate electrode 121 and the second gate electrode 122.

In the present embodiment, the third nitride layer 18 may be etched in a direction perpendicular to the substrate 10 by dry etching to remove the third nitride layer 18 located on the horizontal surfaces of the first gate electrode 121 and the second gate electrode 122, forming the third nitride layer 181 located on the sidewall of the first gate electrode 121 and the third nitride layer 182 located on the sidewall of the second gate electrode 122 (as shown in fig. 4 d).

In this embodiment, step S56 may further include removing the oxide layers (including the first oxide layer 1211 and the third oxide layer 17) of the horizontal surfaces of the first gate electrode 121 and the second gate electrode 122. Specifically, the oxide layer on top of the first gate electrode 121 and the oxide layer on top of the second gate electrode 122, and the third oxide layer 17 on the surface of the gate insulating layer 11 may be removed by dry etching, leaving the third oxide layer 171 on the sidewall of the first gate electrode 121 and the third oxide layer 172 on the sidewall of the second gate electrode 122 (as shown in fig. 4 e).

In this embodiment, the first insulating layer located on the sidewall of the first gate 121 and the second insulating layer located on the sidewall of the second gate 122 (see the first insulating layer 161 and the second insulating layer 162 in fig. 2i in the first embodiment) are continuously formed on the basis of fig. 4e, so that the first sidewall 1210 provided in this embodiment includes the first oxide layer 1211, the first nitride layer 1212, the third oxide layer 171, the third nitride layer 181, the fourth oxide layer 191 and the first insulating layer located on the sidewall of the first gate 121 in this order, and the second sidewall 1220 includes the second oxide layer 1221, the second nitride layer 1222, the third oxide layer 172, the third nitride layer 182 and the second insulating layer located on the sidewall of the second gate 122 in this order.

Compared with the first embodiment, the method for forming the first side wall 1210 and the second side wall 1220 according to the second embodiment of the present invention further forms the third oxide layer 171, the third nitride layer 181 and the fourth oxide layer 191 located on the side wall of the first gate 121 between the first insulating layer and the first nitride layer 1212, and forms the third oxide layer 172 and the third nitride layer 182 located on the side wall of the second gate 122 between the second insulating layer and the second nitride layer 1222, so that not only the first insulating layer and the second insulating layer can increase the width difference between the first side wall 1210 and the second side wall 1220, but also the first side wall 1210 is further increased by one layer of the fourth oxide layer 191 located on the side wall of the first gate compared with the second side wall 1220, thereby further meeting the HCI requirements of the high-voltage well 101 device and reducing the area of the low-voltage well 102 device. In addition, the number of layers formed by the side wall of the grid electrode is larger, so that the protection effect of the side wall on the grid electrode can be better, but the process steps of the first embodiment are fewer compared with those of the second embodiment.

The third embodiment of the present invention further provides a semiconductor device, as shown in fig. 2i, where the semiconductor device includes a substrate 10, a high-voltage well region 101 and a low-voltage well region 102 are formed in the substrate 10 at intervals, a first gate 121 and a second gate 122 located on the substrate 10, the first gate 121 corresponds to the high-voltage well region 101, the second gate 122 corresponds to the low-voltage well region 102, and the height of the first gate 121 is greater than the height of the second gate 122, and a first sidewall 1210 located on a sidewall of the first gate 121 and a second sidewall 1220 located on a sidewall of the second gate 122, and the width of the first sidewall 1210 in a direction away from the sidewall of the first gate 121 is greater than the width of the second sidewall 1220 in a direction away from the sidewall of the second gate 122. In this embodiment, the high-voltage well region 101, the first gate 121 and the first sidewall 1210 are devices in HVMOS, and the low-voltage well region 102, the second gate 122 and the second sidewall 1220 are devices in LVMOS.

Preferably, the width of the first gate electrode 121 is greater than the width of the second gate electrode 122.

Optionally, the first sidewall 1210 includes a first insulating layer 161 located on a sidewall of the first gate 121, the second sidewall 1220 includes a second insulating layer 162 located on a sidewall of the second gate 122, and widths of the first sidewall 1210 and the second sidewall 1220 are gradually reduced in a direction away from the substrate 10, respectively.

Further, the first sidewall 1210 includes a first oxide layer 1211, a first nitride layer 1212, and the first insulating layer 161 sequentially located on the sidewall of the first gate 121, and the second sidewall 1220 includes a second oxide layer 1221, a second nitride layer 1222, and the second insulating layer 162 sequentially located on the sidewall of the second gate 122.

In a further embodiment, referring to fig. 4e, the first sidewall 1210 includes the first oxide layer 1211, the first nitride layer 1212, the third oxide layer 171, the third nitride layer 181, the fourth oxide layer 191 and the first insulating layer sequentially located on the sidewall of the first gate 121, and the second sidewall 1220 includes the second oxide layer 1221, the second nitride layer 1222, the third oxide layer 172, the third nitride layer 182 and the second insulating layer sequentially located on the sidewall of the second gate 122.

The semiconductor device may further include a first source region and a first drain region in the high-voltage well region 101, a second source region and a second drain region in the low-voltage well region 102, and a first lightly doped region 1011 and a second lightly doped region 1012 in the high-voltage well region 101 adjacent to the first source region and the first drain region, respectively. The semiconductor device is formed by the method for manufacturing a semiconductor device provided in the above embodiment, so that the semiconductor device has the same advantages as those of the above embodiment, and the description thereof is omitted.

The foregoing description of the embodiments is only for the purpose of aiding in the understanding of the technical solutions of the present invention and the core ideas thereof, and it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalents may be substituted for some of the technical features thereof, and these modifications or substitutions do not depart from the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming an insulating layer covering the first grid electrode, the second grid electrode and the substrate by adopting a deposition process, wherein the width of the insulating layer formed by the deposition process gradually decreases along the direction away from the substrate, and the width of the insulating layer on the side wall of the first grid electrode formed by the deposition process is larger than that of the insulating layer on the side wall of the second grid electrode;

And removing the insulating layers on the surface of the substrate, the top of the first grid electrode and the top of the second grid electrode, and leaving the first insulating layer on the side wall of the first grid electrode as a first side wall and the second insulating layer on the side wall of the second grid electrode as a second side wall, wherein the width of the first side wall in the direction away from the side wall of the first grid electrode is larger than that of the second side wall in the direction away from the side wall of the second grid electrode.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the first gate electrode and the second gate electrode on the substrate comprises:

3. The method of manufacturing a semiconductor device according to claim 2, wherein a width of the first gate is larger than a width of the second gate.

4. The method of manufacturing a semiconductor device according to claim 1, wherein widths of the first and second sidewalls are gradually reduced in a direction away from the substrate, respectively.

5. The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming a first sidewall located on the first gate sidewall and a second sidewall located on the second gate sidewall further comprises:

6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming a first sidewall located on the first gate sidewall and a second sidewall located on the second gate sidewall further comprises:

Removing the fourth oxide layer on the side wall of the second grid electrode;

7. The method for manufacturing a semiconductor device according to claim 1, further comprising:

8. A semiconductor device, comprising:

The first side wall is located on the first grid side wall, the second side wall is located on the second grid side wall, the width of the first side wall in the direction away from the first grid side wall is larger than the width of the second side wall in the direction away from the second grid side wall, the widths of the first side wall and the second side wall are gradually reduced along the direction away from the substrate respectively, wherein the insulating layer deposited on the first grid side wall serves as the first side wall, and the insulating layer deposited on the second grid side wall serves as the second side wall.

9. The semiconductor device according to claim 8, wherein a width of the first gate is larger than a width of the second gate.

10. The semiconductor device of claim 8, wherein the first sidewall comprises a first insulating layer on the first gate sidewall and the second sidewall comprises a second insulating layer on the second gate sidewall.

11. The semiconductor device of claim 10, wherein the first sidewall comprises a first oxide layer and a first nitride layer and the first insulating layer sequentially located on the first gate sidewall, and the second sidewall comprises a second oxide layer, a second nitride layer and the second insulating layer sequentially located on the first gate sidewall.

12. The semiconductor device of claim 11, wherein the first sidewall includes the first oxide layer, the first nitride layer, a third oxide layer, a third nitride layer, a fourth oxide layer, and the first insulating layer sequentially located on the first gate sidewall, and the second sidewall includes the second oxide layer, the second nitride layer, the third oxide layer, the third nitride layer, and the second insulating layer sequentially located on the second gate sidewall.

13. The semiconductor device according to claim 8, further comprising: