CN114005826A

CN114005826A - Preparation method of semiconductor device and semiconductor device

Info

Publication number: CN114005826A
Application number: CN202111274291.XA
Authority: CN
Inventors: 石艳伟
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2022-02-01
Anticipated expiration: 2041-10-29
Also published as: CN114005826B

Abstract

The invention discloses a preparation method of a semiconductor device and the semiconductor device, which comprises a substrate, a first grid and a second grid which are formed on the substrate, and a first side wall and a second side wall which are respectively formed on the side wall of the first grid and the side wall of the second grid. The substrate is provided with a high-voltage well region and a low-voltage well region which are arranged at intervals, the first grid and the second grid correspond to the high-voltage well region and the low-voltage well region respectively, the height of the first grid is larger than that of the second grid, and the width of the first side wall is larger than that of the second side wall. Because the height of the first grid electrode corresponding to the high-voltage well region and the width of the first side wall are larger, the performance of the device can be improved, such as the damage of a grid electrode oxidation layer and the hot carrier effect are reduced, and simultaneously, because the height of the second grid electrode corresponding to the low-voltage well region and the width of the second side wall are smaller, the speed of the device can be improved, and the area of the device is reduced.

Description

Preparation method of semiconductor device and semiconductor device

Technical Field

The present invention relates generally to electronic devices, and more particularly, to a method of manufacturing a semiconductor device and a semiconductor device.

Background

A Low Voltage Metal Oxide Semiconductor (LVMOS) transistor and a High Voltage Metal Oxide Semiconductor (HVMOS) transistor are both present in a Complementary Metal Oxide Semiconductor (COMS).

Because the energy of the ion implantation for forming the low-doped structure of the HVMOS is large, the gate height does not reach a certain requirement, the gate is broken through, and then a gate oxide layer is damaged, and meanwhile, the widths of the side walls at the two sides of the gate do not reach a certain requirement, a Hot Carrier Injection (HCI) effect is caused, and the performance of a device is damaged. However, for LVMOS, too thick a gate will slow down the device speed, and too wide a sidewall will slow down the device speed. Because the side wall of the LVMOS and the contact point on the grid need to be separated by a certain distance, the wider the side wall is, the more the space of the contact point is limited under the condition of a certain device area; if the sidewall is spaced from the contact at a certain distance and the width of the sidewall is increased, the area of the device is increased, and therefore, the area of the device is lost due to the fact that the width of the sidewall of the LVMOS is too wide.

However, for the memory, as the memory density increases, the area of the CMOS is inevitably required to be reduced.

Disclosure of Invention

The invention aims to provide a preparation method of a semiconductor device and the semiconductor device, aiming at forming double gates with different heights and double side walls with different widths so as to give consideration to the gate height and the side wall width of an HVMOS and an LVMOS, thereby improving the performance of the device and reducing the area of the device.

In one aspect, the present invention provides a method for manufacturing a semiconductor device, including:

providing a substrate, wherein a high-voltage well region and a low-voltage well region which are arranged at intervals are formed in the substrate;

forming a first grid and a second grid on the substrate, wherein the first grid corresponds to the high-voltage well region, the second grid corresponds to the low-voltage well region, and the height of the first grid is greater than that of the second grid;

and forming a first side wall positioned on the side wall of the first grid electrode and a second side wall positioned on the side wall of the second grid electrode, wherein the width of the first side wall in the direction far away from the side wall of the first grid electrode is larger than that of the second side wall in the direction far away from the side wall of the second grid electrode.

Further preferably, the step of forming the first gate and the second gate on the substrate includes:

forming a gate layer on the substrate, wherein the gate layer is positioned above the high-voltage well region and the low-voltage well region;

removing a part of the gate layer above the low-voltage well region to enable the height of the gate layer above the low-voltage well region to be smaller than that of the gate layer above the high-voltage well region;

and forming the first grid electrode corresponding to the high-voltage well region and the second grid electrode corresponding to the low-voltage well region by adopting a photoetching process, wherein the height of the first grid electrode is greater than that of the second grid electrode.

Further preferably, the width of the first gate is larger than the width of the second gate.

Further preferably, the step of forming the first sidewall spacer located on the first gate sidewall and the second sidewall spacer located on the second gate sidewall includes:

forming an insulating layer covering the first grid, the second grid and the substrate;

and etching the insulating layer to form a first insulating layer positioned on the side wall of the first grid electrode and a second insulating layer positioned on the side wall of the second grid electrode, wherein the first side wall comprises the first insulating layer, and the second side wall comprises the second insulating layer.

Preferably, the widths of the first side wall and the second side wall are gradually reduced along a direction away from the substrate.

Further preferably, the step of forming the first sidewall spacer located on the first gate sidewall and the second sidewall spacer located on the second gate sidewall further includes:

forming a first oxide layer and a second oxide layer covering the first gate and the second gate, respectively, before the step of forming the insulating layer;

forming a first nitride layer on the outer surface of the first oxide layer on the side wall of the first grid, and simultaneously forming a second nitride layer on the outer surface of the second oxide layer on the side wall of the second grid;

the first sidewall comprises the first oxide layer, the first nitride layer and the first insulating layer which are positioned on the first grid sidewall, and the second sidewall comprises the second oxide layer, the second nitride layer and the second insulating layer which are positioned on the second grid sidewall.

sequentially forming a third oxide layer, a third nitride layer and a fourth oxide layer which cover the horizontal surfaces and the side walls of the first grid and the second grid;

removing the fourth oxide layer on the horizontal surfaces of the first grid and the second grid;

removing the fourth oxide layer on the side wall of the second grid electrode;

removing the third nitride layer on the horizontal surfaces of the first grid and the second grid;

the first side wall comprises a first oxidation layer, a first nitridation layer, a third oxidation layer, a third nitridation layer, a fourth oxidation layer and a first insulation layer which are sequentially located on the first grid side wall, and the second side wall comprises a second oxidation layer, a second nitridation layer, a third oxidation layer, a third nitridation layer and a second insulation layer which are sequentially located on the second grid side wall.

Further preferably, the method further comprises the following steps:

forming a first source region and a first drain region in the high-voltage well region;

forming a second source region and a second drain region in the low-voltage well region;

after the step of forming the first gate electrode and the second gate electrode, a first lightly doped region and a second lightly doped region are formed in the high voltage well region adjacent to the first source region and the first drain region, respectively.

In another aspect, the present invention provides a semiconductor device comprising:

the semiconductor device comprises a substrate, wherein a high-voltage well region and a low-voltage well region which are arranged at intervals are formed in the substrate;

the first grid and the second grid are positioned on the substrate, the first grid corresponds to the high-voltage well region, the second grid corresponds to the low-voltage well region, and the height of the first grid is greater than that of the second grid;

the width of the first side wall in the direction far away from the first grid side wall is larger than that of the second side wall in the direction far away from the second grid side wall.

Preferably, the first sidewall includes a first insulating layer located on the first gate sidewall, the second sidewall includes a second insulating layer located on the second gate sidewall, and widths of the first sidewall and the second sidewall are respectively gradually reduced along a direction away from the substrate.

Further preferably, the first sidewall includes a first oxide layer and a first nitride layer sequentially located on the first gate sidewall, and the first insulating layer, and the second sidewall includes a second oxide layer, a second nitride layer sequentially located on the first gate sidewall, and the second insulating layer.

Preferably, the first sidewall comprises the first oxide layer, the first nitride layer, the third oxide layer, the third nitride layer, the fourth oxide layer and the first insulating layer which are sequentially located on the first gate sidewall, and the second sidewall comprises the second oxide layer, the second nitride layer, the third oxide layer, the third nitride layer and the second insulating layer which are sequentially located on the second gate sidewall.

Further preferably, the method further comprises the following steps:

a first source region and a first drain region located in the high voltage well region;

a second source region and a second drain region located in the low-voltage well region;

and the first lightly doped region and the second lightly doped region are positioned in the high-voltage well region and are respectively adjacent to the first source region and the first drain region.

The invention has the beneficial effects that: the method comprises the steps of forming a substrate, forming a first grid and a second grid which are positioned on the substrate, and forming a first side wall and a second side wall which are respectively formed on the side wall of the first grid and the side wall of the second grid. The substrate is provided with a high-voltage well region and a low-voltage well region which are arranged at intervals, the first grid and the second grid correspond to the high-voltage well region and the low-voltage well region respectively, the height of the first grid is larger than that of the second grid, and the width of the first side wall is larger than that of the second side wall. Because the height of the first grid electrode corresponding to the high-voltage well region and the width of the first side wall are larger, the performance of the device can be improved, such as the damage of a grid electrode oxidation layer and the hot carrier effect are reduced, and simultaneously, because the height of the second grid electrode corresponding to the low-voltage well region and the width of the second side wall are smaller, the speed of the device can be improved, and the area of the device is reduced.

Drawings

The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.

Fig. 1 is a schematic flow chart of a manufacturing method of a semiconductor device provided in a first embodiment of the present invention;

fig. 2a-2i are schematic structural diagrams of a semiconductor device provided in a first embodiment of the present invention during a manufacturing process;

fig. 3 is a schematic flowchart of forming a first sidewall and a second sidewall according to a second embodiment of the present invention;

fig. 4a to 4e are schematic structural diagrams in the process of forming the first side wall and the second side wall according to the second embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.

It will be understood that when an element is referred to as being "on," "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.

As used herein, the term "layer" refers to a portion of material that includes a region having a height. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Further, a layer may be a region of uniform or non-uniform continuous structure having a height less than the height of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers above, and/or below it. The layer may comprise a plurality of layers. For example, the interconnect layers may include one or more conductive layers and contact layers (in which contacts, interconnect lines, and one or more dielectric layers are formed).

As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.

It should be noted that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in the actual implementation, the type, quantity and proportion of the components in the actual implementation can be changed freely, and the layout of the components may be more complicated.

Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Referring to fig. 2a-2i, fig. 2a-2i are schematic structural diagrams of a semiconductor device according to a first embodiment of the present invention during a manufacturing process. The method for manufacturing the semiconductor device includes the following steps S1-S3.

Please refer to step S1 in fig. 1 and fig. 2 a.

Step S1: a substrate 10 is provided, and a high-voltage well region 101 and a low-voltage well region 102 are formed in the substrate 10 at intervals.

The substrate 10 may be a semiconductor substrate, and may be, for example, a Silicon (Si), Germanium (Ge), SiGe substrate, Silicon On Insulator (SOI), Germanium On Insulator (GOI), or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, and may also be a stacked structure, such as Si/SiGe or the like.

In this embodiment, the substrate 10 may be etched to form an isolation trench, the isolation trench is then filled with an insulating material to form an isolation structure 103, an appropriate mask is used to perform ion implantation on the substrate 10 to form the high-voltage well region 101 and the low-voltage well region 102 which are arranged at an interval, and the isolation structure 103 is used to separate the high-voltage well region 101 and the low-voltage well region 102. The device operating voltage corresponding to the high voltage well region 101 is higher, and the device operating voltage corresponding to the low voltage well region 102 is lower. The preparation sequence of the hvw region 101 and the hvw region 102 and the isolation structure 103 is not limited by this embodiment.

Please refer to steps S2-S4 in fig. 1 and fig. 2a-2 e.

Step S2: a gate layer 12 is formed on the substrate 10, and the gate layer 12 is located above the hvw region 101 and the hvw region 102.

In a specific embodiment, as shown in fig. 2a, step S2 may include: firstly, forming a gate insulating layer 11 on a substrate 10 by adopting a proper deposition process; a gate electrode layer 12 is deposited on the gate insulating layer 11, the gate insulating layer 11 may comprise silicon oxide, and the gate electrode layer 12 may comprise polysilicon.

Step S3: removing a portion of the gate layer 12 above the hvw region 102, so that the height of the gate layer 12 above the hvw region 102 is smaller than the height of the gate layer 12 above the hvw region 101.

In one embodiment, as shown in fig. 2b, photoresist is spun on gate layer 12; then, patterning the photoresist by using a mask plate to form a patterned photoresist layer 13 as shown in fig. 2b, wherein the patterned photoresist layer 13 corresponds to the upper part of the high-voltage well region 101; as shown in fig. 2c, the patterned photoresist layer 13 is used to etch the gate layer 12 to remove a portion of the gate layer 12 above the hvw region 102, so that the height of the gate layer 12 above the hvw region 102 is smaller than the height of the gate layer 12 above the hvw region 101, specifically, the etching depth can be controlled by controlling the etching rate and time, thereby precisely controlling the height of the gate layer 12 above the hvw region 102.

When the photoresist is a positive photoresist, the mask plate has openings above the corresponding low-voltage well region 102 and the isolation structure 103, and after exposure and development, the photoresist is removed at the portions above the corresponding low-voltage well region 102 and the isolation structure 103, so that the patterned photoresist layer 13 above the corresponding high-voltage well region 101 is formed.

Step S4: and forming the first gate 121 corresponding to the hvw region 101 and the second gate 122 corresponding to the hvw region 102 by using a photolithography process, wherein the height of the first gate 121 is greater than the height of the second gate 122.

In one embodiment, as shown in fig. 2d, a composite hard mask layer 14 and a photoresist layer 15 are sequentially deposited on the etched gate layer 12, wherein the composite hard mask layer comprises sequentially formed amorphous carbon layers (a-C)141, and a silicon oxynitride (SiON) layer 142 formed on the surface of the amorphous carbon layer 141, the amorphous carbon layer 141 serves as a light absorbing layer, and the silicon oxynitride layer 142 serves as an anti-reflective layer; as shown in fig. 2e, the photoresist layer 15 is exposed and developed by using a mask, a patterned hard mask layer is formed by using the photoresist layer 15, and the gate layer 12 is etched by using the patterned hard mask layer to form the first gate 121 and the second gate 122 as shown in fig. 2 e. Preferably, the width of the first gate 121 formed by changing the pattern of the mask plate is larger than the width of the second gate 122, so that the process for forming the first gate 121 and the second gate 122 with different widths is simple and does not need to add extra process steps.

Please refer to step S5 in fig. 1 and fig. 2f-2 i.

Step S5: forming a first sidewall 1210 on a sidewall of the first gate 121 and a second sidewall 1220 on a sidewall of the second gate 122, wherein a width of the first sidewall 1210 in a direction away from the sidewall of the first gate 121 is greater than a width of the second sidewall 1220 in a direction away from the sidewall of the second gate 122.

In a specific embodiment, step S5 may include:

1) a first oxide layer 1211 and a second oxide layer 1221 covering the first gate 121 and the second gate 122, respectively, may be formed, specifically, an oxide layer may be deposited first, and then the oxide layer on the gate insulating layer 11 may be removed, so as to form the first oxide layer 1211 covering the first gate 121 and the second oxide layer 1221 covering the second gate as shown in fig. 2 f.

2) Specifically, a first nitride layer 1212 on the outer surface of the first oxide layer 1211 is formed on the sidewall of the first gate 121, and a second nitride layer 1222 on the outer surface of the second oxide layer 1221 is formed on the sidewall of the second gate 122, and the nitride layer is deposited first, and then the nitride layer on the horizontal surface is removed by dry etching (isotropic etching) to form the first nitride layer 1212 and the second nitride layer 1222 as shown in fig. 2 f.

3) As shown in fig. 2h, the insulating layer 16 covering the first gate 121, the second gate 122 and the substrate 10 (or the gate insulating layer 11) is formed, and when the insulating layer 16 is deposited, more insulating layers 16 are deposited at the corners of the bottoms of the first gate 121 and the second gate 122, and less insulating layers 16 are deposited in the direction away from the substrate 10. Since the height of the first gate 121 is greater than that of the second gate 122, in order to make the insulating layer 16 cover the first gate 121 higher than the second gate 122, the insulating layer 16 thicker than the second gate 122 is formed on the sidewall of the first gate 121, so that the width of the insulating layer 16 formed is gradually reduced in a direction away from the substrate 10, and the insulating layer 16 on the sidewall of the first gate 121 is wider than the insulating layer 16 on the sidewall of the second gate 122 (comparing the corresponding positions, for example, comparing the bottom of the first gate 121 with the bottom of the second gate 122).

4) As shown in fig. 2i, the insulating layer 16 is etched to form a first insulating layer 161 located on a sidewall of the first gate 121 as the first sidewall 1210, and a second insulating layer 162 located on a sidewall of the second gate 122 as the second sidewall 1220, and widths of the first sidewall 1210 and the second sidewall 1220 are gradually decreased along a direction away from the substrate 10, respectively. Specifically, the insulating layer 16 may be etched by dry etching along a direction perpendicular to the substrate 10, so as to remove the insulating layer 16 on the horizontal surface, and leave the first insulating layer 161 on the sidewall of the first gate 121 and the second insulating layer 162 on the sidewall of the second gate 122, where the first sidewall 1210 includes the first oxide 1211, the first nitride 1212, and the first insulating layer 161 on the sidewall of the first gate 121, and the second sidewall 1220 includes the second oxide 1221, the second nitride 1222, and the second insulating layer 162 on the sidewall of the second gate 122. In the etching process, the width of the first sidewall 1210 formed after etching in the direction away from the sidewall of the first gate 121 is greater than the width of the second sidewall 1220 in the direction away from the sidewall of the second gate 122 due to the thicker insulating layer 16 of the sidewall of the first gate 121, and the widths of the first sidewall 1210 and the second sidewall 1220 formed gradually decrease in the direction away from the substrate 10 due to the gradually decreasing width of the insulating layer 16 from the bottom to the top of the gate.

In a modification, the insulating layer 16 may be directly formed, and then the first insulating layer 161 and the second insulating layer 162 are formed as the first sidewall 1210 and the second sidewall 1220 by etching, i.e., there is no need to form an oxide layer and a nitride layer. In the present embodiment, the first oxide layer 1211 and the first nitride layer 1212 are formed between the first gate 121 and the first sidewall 1210, so as to protect the first gate 121 more effectively; forming the second oxide layer 1221 and the second nitride layer 1222 between the second gate 122 and the second sidewall 1220 can protect the second gate 122 more effectively.

The method for manufacturing the semiconductor device according to this embodiment may further include, after forming the high-voltage well region 101 and the low-voltage well region 102, forming a first source region and a first drain region (not shown in the figure) in the high-voltage well region 101, and forming a second source region and a second drain region (not shown in the figure) in the low-voltage well region 102. Further, after forming the first nitride layer 1212 and the second nitride layer 1222 (fig. 2f), as shown in fig. 2g, a photoresist covering the isolation structure 103 and the hvw region 102 is formed, and a first lightly doped region 1011 and a second lightly doped region 1012 are formed in the hvw region 101 adjacent to the first source region and the first drain region, respectively. Specifically, the first lightly doped region 1011 is formed by performing ion implantation on the high-voltage well region 101 near the first source region, the second lightly doped region 1012 is formed by performing ion implantation on the high-voltage well region 101 near the first drain region, and the first lightly doped region 1011 and the second lightly doped region 1012 are formed in the high-voltage well region 101, so that the first lightly doped region 1011 and the second lightly doped region 1012 also bear partial voltage, and the structure can prevent the HCI effect. Since the energy of the ion implantation is large, the thickness of the first gate 121 corresponding to the high voltage well 101 is set to be thick, so that the first gate 121 can be prevented from being punched through to damage the gate insulating layer 11, thereby ensuring the performance of the device.

The method for manufacturing a semiconductor device according to the first embodiment of the present invention includes forming a substrate 10 having a high-voltage well region 101 and a low-voltage well region 102 disposed at an interval, forming a first gate 121 and a second gate 122 on the substrate, where the first gate 121 and the second gate 122 correspond to the high-voltage well region 101 and the low-voltage well region 102, respectively, and forming a first sidewall 1210 and a second sidewall 1220 on sidewalls of the first gate 121 and the second gate 122, respectively. The height of the first gate 121 is greater than that of the second gate 122, and the width of the first sidewall 1210 is greater than that of the second sidewall 1220. Since the height of the first gate 121 corresponding to the high-voltage well 101 is higher, the first gate 121 can be protected from being penetrated and the gate oxide layer can be protected from being damaged when the first lightly doped region 1011 and the second lightly doped region 1012 are formed, and the hot carrier injection effect can be reduced since the width of the first sidewall 1210 of the sidewall of the first gate 121 is larger. Meanwhile, the height of the second gate 122 and the width of the second sidewall 1220 corresponding to the low-voltage well region 102 are small, which can increase the speed of the device and reduce the area of the device.

Referring to fig. 3, fig. 3 is a schematic flow chart illustrating the formation of the first sidewall spacer and the second sidewall spacer according to the second embodiment of the present invention. Referring to fig. 4a to 4e, fig. 4a to 4e are schematic structural diagrams of a process of forming a first sidewall and a second sidewall according to a second embodiment of the present invention. For ease of understanding, the same structures in the present embodiment as those in the first embodiment are given the same reference numerals. In the present embodiment, the step of forming the first and second sidewalls includes the following steps S51-S56.

Step S51: a first oxide layer 1211 and a second oxide layer 1221 covering the first gate electrode 121 and the second gate electrode 122, respectively, are formed.

Step S52: a first nitride layer 1212 is formed on the sidewall of the first gate 121 and located on the outer surface of the first oxide layer 1211, and a second nitride layer 1222 is formed on the sidewall of the second gate 122 and located on the outer surface of the second oxide layer 1221.

In the present embodiment, step S51 is the same as step S5 in the first embodiment in 1), step S52 is the same as step S5 in the first embodiment in 2), the process of step S51 and step S52 are not described in detail, and the completed structure is as shown in fig. 2f in the first embodiment.

Step S53: a third oxide layer 17, a third nitride layer 18 and a fourth oxide layer 19 are sequentially formed to cover horizontal surfaces and sidewalls of the first gate 121 and the second gate 122.

On the basis of fig. 2f, a third oxide layer 17, a third nitride layer 18 and a fourth oxide layer 19 are sequentially deposited, as shown in fig. 4a, the third oxide layer 17, the third nitride layer 18 and the fourth oxide layer 19 cover the horizontal surfaces and sidewalls of the first gate 121 and the second gate 122 and the gate insulating layer 11.

Step S54: the fourth oxide layer 19 on the horizontal surfaces of the first gate 121 and the second gate 122 is removed.

In this embodiment, a dry etching process may be used to etch the fourth oxide layer 19 along a direction perpendicular to the substrate 10 to form a fourth oxide layer 191 on the sidewall of the first gate 121 and a fourth oxide layer 192 on the sidewall of the second gate 122 (as shown in fig. 4 b).

Step S55: the fourth oxide layer 192 on the sidewall of the second gate 122 is removed (as shown in fig. 4 c).

In this embodiment, the mask used in step S3 in the first embodiment may be adopted, because both step S55 and step S3 are performed to etch the device in the low-voltage well region 102, the number of masks can be reduced by using the same mask as that used in step S3, and the cost can be reduced.

Step S56: the third nitride layer 18 on the horizontal surfaces of the first gate 121 and the second gate 122 is removed.

In this embodiment, dry etching may be used to etch the third nitride layer 18 along a direction perpendicular to the substrate 10 to remove the third nitride layer 18 on the horizontal surfaces of the first gate 121 and the second gate 122, and form a third nitride layer 181 on the sidewall of the first gate 121 and a third nitride layer 182 on the sidewall of the second gate 122 (as shown in fig. 4 d).

In this embodiment, step S56 may be followed by: the oxide layers (including the first oxide layer 1211 and the third oxide layer 17) on the horizontal surfaces of the first gate 121 and the second gate 122 are removed. Specifically, the oxide layer on the top of the first gate 121, the oxide layer on the top of the second gate 122, and the third oxide layer 17 on the surface of the gate insulating layer 11 may be removed by dry etching, so as to leave the third oxide layer 171 on the sidewall of the first gate 121 and the third oxide layer 172 on the sidewall of the second gate 122 (as shown in fig. 4 e).

In this embodiment, the first insulating layer on the sidewall of the first gate 121 and the second insulating layer on the sidewall of the second gate 122 are formed continuously on the basis of fig. 4e (see the first insulating layer 161 and the second insulating layer 162 in fig. 2i in the first embodiment), so that the first sidewall 1210 provided by this embodiment includes the first oxide 1211, the first nitride 1212, the third oxide 171, the third nitride 181, the fourth oxide 191 and the first insulating layer sequentially on the sidewall of the first gate 121, and the second sidewall 1220 includes the second oxide 1221, the second nitride 1222, the third oxide 172, the third nitride 182 and the second insulating layer sequentially on the sidewall of the second gate 122.

Compared with the first embodiment, the method for forming the first sidewall 1210 and the second sidewall 1220 according to the second embodiment of the present invention further forms the third oxide layer 171, the third nitride layer 181, and the fourth oxide layer 191 between the first insulating layer and the first nitride layer 1212, and the third oxide layer 172 and the third nitride layer 182 between the second insulating layer and the second nitride layer 1222, so that not only the first insulating layer and the second insulating layer can increase the width difference between the first sidewall 1210 and the second sidewall 1220, but also the first sidewall 1210 further has a layer of the fourth oxide layer 191 on the first sidewall 1220 than the second sidewall 1220, thereby further increasing the width difference between the first sidewall 1210 and the second sidewall 1220, further satisfying the HCI requirement of the high voltage well 101 device, and reducing the area of the low voltage well 102 device. In addition, since the number of layers formed on the sidewall of the gate is large, the protective effect of the sidewall on the gate can be better, but the process steps of the first embodiment are fewer than those of the second embodiment.

The third embodiment of the present invention also provides a semiconductor device, as shown in fig. 2i, including: the semiconductor device comprises a substrate 10, wherein a high-voltage well region 101 and a low-voltage well region 102 which are arranged at intervals are formed in the substrate 10; a first gate 121 and a second gate 122 on the substrate 10, wherein the first gate 121 corresponds to the hvw region 101, the second gate 122 corresponds to the hvw region 102, and the height of the first gate 121 is greater than the height of the second gate 122; and a first sidewall 1210 located on a sidewall of the first gate 121 and a second sidewall 1220 located on a sidewall of the second gate 122, wherein a width of the first sidewall 1210 in a direction away from the sidewall of the first gate 121 is greater than a width of the second sidewall 1220 in a direction away from the sidewall of the second gate 122. In the present embodiment, the hvw region 101, the first gate 121 and the first sidewall 1210 are devices in HVMOS, and the hvw region 102, the second gate 122 and the second sidewall 1220 are devices in LVMOS.

Preferably, the width of the first gate 121 is greater than the width of the second gate 122.

Optionally, the first sidewall 1210 includes a first insulating layer 161 located on a sidewall of the first gate 121, the second sidewall 1220 includes a second insulating layer 162 located on a sidewall of the second gate 122, and widths of the first sidewall 1210 and the second sidewall 1220 are gradually reduced along a direction away from the substrate 10, respectively.

Further, the first sidewall 1210 includes a first oxide layer 1211 and a first nitride layer 1212, which are sequentially located on sidewalls of the first gate 121, and the first insulating layer 161, and the second sidewall 1220 includes a second oxide layer 1221, a second nitride layer 1222, which are sequentially located on sidewalls of the second gate 122, and the second insulating layer 162.

In a further embodiment, referring to fig. 4e, the first sidewall 1210 includes the first oxide 1211, the first nitride 1212, the third oxide 171, the third nitride 181, the fourth oxide 191 and the first insulating layer sequentially disposed on the sidewall of the first gate 121, and the second sidewall 1220 includes the second oxide 1221, the second nitride 1222, the third oxide 172, the third nitride 182 and the second insulating layer sequentially disposed on the sidewall of the second gate 122.

The semiconductor device may further include: a first source region and a first drain region located in the high voltage well region 101; a second source region and a second drain region located in the low-voltage well region 102; and a first lightly doped region 1011 and a second lightly doped region 1012 located in the hvw region 101 and adjacent to the first source region and the first drain region, respectively. The semiconductor device is formed by the method for manufacturing a semiconductor device provided by the above embodiment, and therefore, the semiconductor device has the same beneficial effects as the above embodiment, and details are not repeated in this embodiment.

The above description of the embodiments is only for helping understanding the technical solution of the present invention and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A method of manufacturing a semiconductor device, comprising:

2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the first gate electrode and the second gate electrode over the substrate includes:

3. The method for manufacturing a semiconductor device according to claim 2, wherein a width of the first gate is larger than a width of the second gate.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the first sidewall spacers on the sidewalls of the first gate and the second sidewall spacers on the sidewalls of the second gate includes:

5. The method for manufacturing a semiconductor device according to claim 4, wherein the widths of the first side wall and the second side wall are gradually reduced along a direction away from the substrate.

6. The method for manufacturing a semiconductor device according to claim 5, wherein the step of forming the first sidewall spacers on the sidewalls of the first gate and the second sidewall spacers on the sidewalls of the second gate further comprises:

7. The method for manufacturing a semiconductor device according to claim 6, wherein the step of forming the first sidewall spacers on the sidewalls of the first gate and the second sidewall spacers on the sidewalls of the second gate further comprises:

removing the fourth oxide layer on the side wall of the second grid electrode;

8. The method for manufacturing a semiconductor device according to claim 1, further comprising:

9. A semiconductor device, comprising:

10. The semiconductor device according to claim 9, wherein a width of the first gate is larger than a width of the second gate.

11. The semiconductor device according to claim 9, wherein the first sidewall comprises a first insulating layer on the first gate sidewall, the second sidewall comprises a second insulating layer on the second gate sidewall, and widths of the first sidewall and the second sidewall are gradually reduced along a direction away from the substrate.

12. The semiconductor device according to claim 11, wherein the first sidewall comprises a first oxide layer and a first nitride layer sequentially on the first gate sidewall, and the first insulating layer, and wherein the second sidewall comprises a second oxide layer, a second nitride layer, and the second insulating layer sequentially on the first gate sidewall.

13. The semiconductor device according to claim 12, wherein the first sidewall comprises the first oxide layer, the first nitride layer, a third oxide layer, a third nitride layer, a fourth oxide layer, and the first insulating layer, which are sequentially located on the first gate sidewall, and wherein the second sidewall comprises the second oxide layer, the second nitride layer, the third oxide layer, the third nitride layer, and the second insulating layer, which are sequentially located on the second gate sidewall.

14. The semiconductor device according to claim 9, further comprising: