CN103618556A - Partially parallel quasi-cyclic low-density parity-check (QC-LDPC) decoding method based on row message passing (RMP) scheduling - Google Patents

Abstract

The invention relates to a partially parallel QC-LDPC decoding method based on Row Message Passing (RMP) scheduling, which belongs to the technical field of communication. The present invention implements a partially parallel decoding structure in the QC-LDPC decoder using the minimum sum decoding algorithm based on RMP scheduling, and in each iterative decoding process, compared with the minimum sum decoding algorithm, it reduces nearly half Iterative delay: In view of the quasi-cyclic characteristics of the QC-LDPC check matrix, a partial parallel processing decoding structure is used to partition the check matrix and perform parallel iterative decoding in the partitions. The decoding delay and each The decoding parallelism in the partition is linear and inversely proportional, which doubles the throughput of the decoder, and ensures that this parallel method has the same performance as the serial RMP method, making the LDPC decoder suitable for high-speed data processing. Require.

Description

Partially Parallel QC-LDPC Decoding Method Based on RMP Scheduling

technical field

The invention relates to a partially parallel QC-LDPC decoding method based on Row Message Passing (RMP) scheduling, which belongs to the technical field of communication.

Background technique

Low-density parity-check code (LDPC) is a code close to the Shannon limit. It has low decoding complexity and flexible structure. It is widely used in modern communication systems and has been adopted by many communication and broadcasting standards. Such as digital satellite TV (DVB-S2), wireless local area network (WLAN) and China's digital TV terrestrial broadcast transmission standard (DTMB) and so on. With the development of wireless communication technology, wireless communication networks need to have higher data service capabilities and comprehensive real-time multimedia services, and fast decoding of channel coding has become an urgent need.

Most LDPC decoders are designed and implemented based on the Min-Sum Algorithm of Standard Message Passing (SMP), which is an approximate simplified algorithm of the Log-Likelihood Ratio (Log-LLR) belief propagation algorithm. There will be a loss in decoding performance, but the complexity of hardware implementation is very low, and there are only numerical comparisons and addition and subtraction operations in the decoding process, which is suitable for engineering implementation.

Its decoder mainly includes the following functional modules: variable node soft information storage unit RAM_Q, corresponding to variable node i; check node soft information storage unit RAM_R, corresponding to check node j; received information storage unit RAM_Y, corresponding to variable node i Node i corresponds to storage; check node update unit CNU, corresponding to check node j, completes the calculation of check node update, and returns the result to the control unit; variable node update unit VNU, corresponding to variable node j, completes the variable node Update the operation, and return the result to the control unit; the control unit is used to generate various control signals to control the read and write addresses of the decoder, and coordinate the work of each unit.

During the decoding process, the soft information received by the decoder is first stored in the received information storage unit RAM_Y, and then the initialization process starts: the variable node soft information storage unit RAM_Q is updated by the soft information in the received information storage unit RAM_Y; Then, update the check node: read the data in the variable node soft information storage unit RAM_Q into the check node update unit CNU according to the read address generated by the control unit, complete the calculation, and store the calculation result according to the storage address provided by the control unit to the check node soft information storage unit RAM_R; then, update the variable node: read the data in the check node soft information storage unit RAM_R into the variable node update unit VNU according to the read address generated by the control unit, complete the operation, and detect Whether the maximum number of iterations is reached, if yes, make a judgment and output the result, otherwise, store the operation result in the variable node soft information storage unit RAM_Q according to the storage address provided by the control unit, and continue to update the check node until the maximum number of iterations is reached .

In 2005, Radosavljevic ("Optimized message passing schedules for LDPC decoding", Signals, Systems and Computers, 2005:591-595) proposed a decoding algorithm based on Row Message Passing (RMP).

The decoder in the above decoding process mainly includes the following functional modules: variable node soft information storage unit RAM_N, which is stored correspondingly to variable node n; check node soft information storage unit RAM_M, which is correspondingly stored to check node m; iterative decoding update The unit ICU completes the operation of iterative decoding and returns the result to the control unit; the control unit is used to generate various control signals to control the read and write addresses of the decoder, and coordinate the work of each unit.

During the decoding process, the soft information received by the decoder starts the initialization process: the received soft information is stored in the variable node soft information storage unit RAM_N, and the check node soft information storage unit RAM_M is initialized to zero; Then, perform iterative update: read the data in the variable node soft information storage unit RAM_N and the check node soft information storage unit RAM_M into the iterative decoding update unit ICU according to the read address generated by the control unit, complete the operation, and follow the control unit to provide Store the operation result in the check node soft information storage unit RAM_N and the check node soft information storage unit RAM_M at the storage address; then, check whether the decoding iteration reaches the maximum number of iterations, if so, make a judgment and output the result, otherwise Continue with checkpoint updates until the maximum number of iterations is reached.

However, there are some problems in the decoders designed by the above two algorithms:

1. Each update of the SMP-based minimum sum algorithm uses the result after the previous iteration. The update result of each node cannot be immediately transmitted to other nodes, and it needs to wait until the next iteration, resulting in slow convergence of the algorithm. Moreover, each iteration needs to update the check node and the variable node respectively, and the decoder needs to perform two read and write operations on the memory for each iteration. These lead to a larger decoding delay for decoding.

2. Although the minimum sum decoding algorithm based on RMP can solve some problems of the minimum sum algorithm based on SMP, it can be seen from the above introduction to the minimum sum decoding algorithm based on RMP that this minimum sum decoding algorithm based on RMP When updating with the decoding algorithm, the row updated later will use the data updated in the row updated earlier, so it can only be updated serially, and parallel decoding cannot be used to increase the decoding delay.

Contents of the invention

The purpose of the present invention is to reduce the decoding delay of the QC-LDPC code decoder and the communication delay of the communication system using the QC-LDPC code as channel coding, and propose a partially parallel LDPC decoding method based on RMP scheduling , for QC-LDPC codes, the decoding processing structure of LDPC decoder based on RMP scheduling is optimized.

The present invention implements a partially parallel decoding structure in a QC-LDPC decoder using a minimum-sum decoding algorithm based on RMP scheduling, specifically through the following technical solutions:

Step 1, the check matrix H(M, N) of the QC-LDPC code whose row weight is a and column weight is b is partitioned, and the specific method is as follows:

(1) find the minimum cyclic submatrix of QC-LDPC code parity check matrix, and obtain its size as I * I, and I is a constant;

(2) Under the premise of ensuring that the column weight of each partition is 1, the check matrix is divided into K partitions with one partition per J row, where I=nJ, M=KJ, n is an integer, and generally n =1, that is, I=J;

(3) Determining the number P of multi-path parallel decoding processes in the partition, Pl=J, where l is the number of lines decoded and processed by each path in each partition.

Step 2, on the basis of partitions, establish a QC-LDPC code decoder based on RMP scheduling, which consists of:

The variable node soft information storage unit RAM_λ is used to store the initialization information and variable node soft information in the iterative decoding process, which includes the P RAM storage block Mλp; the pth RAM storage block Mλp stores the data in each partition The variable node soft information corresponding to the non-zero elements in the row contained in the p-th decoding iteration;

The check node soft information storage unit RAM_Λ is used to store the check node soft information updated in the iterative decoding process, which includes P blocks of RAM storage blocks _MΛp ; wherein the pth RAM storage block _MΛp stores each The check node soft information corresponding to the non-zero elements in the rows included in the p-th decoding iteration in a partition;

The memory address generation module ADU is used to generate the variable node soft information storage unit and the check node soft information storage unit used in the QC-LDPC decoder; it is composed of a RAM_λ memory address generation submodule and a RAM_Λ memory address generation submodule, each A sub-module is composed of P initial address memories and P address offset calculators; each sub-module has P integrated signal output ports, the output of which is from the initial address memory from P initial address memories and counters; ADU has 2P outputs Ports are respectively connected to the read-write address ports of the P read-write ports of the RAM_λ module and the RAM_Λ module.

The iterative decoding module IDU is used to perform parallel update operations on the soft information of the check node and the soft information of the variable node in the iterative process, which includes P CNU calculation modules;

The decoding and judgment module DJU is used to judge and process the information to be output in the variable node soft information storage unit;

The soft information exchange module INU is used to send the data from different RAM storage blocks in the RAM_λ module to the corresponding CNU calculation module during iterative decoding, and return the corresponding updated data to the RAM storage block; the INU has 2P input ports and 2P output ports, where P input ports and output ports are connected to the output ports and input ports of RAM in the RAM_λ module, and P input ports and output ports are connected to output ports and input ports of RAM in P CNU computing modules ; Distribute the P pieces of output soft information in the RAM_λ module to P CNU modules through the integrated signal of the INU module, and store the output soft information of the P CNU modules in the corresponding RAM in the RAM_λ module.

The decoding process control module PCU is used to generate the control signals of the entire decoding process, including the integrated signal of the INU module.

Described each piece of RAM storage block Mλp and _MΛp contain two read-write ports, and its read-write mode is all " read first and then write ", and each read-write port is all connected with the p-th block CNU computing module, and each port is Responsible for reading and writing data all the way;

Step 3, initialize the iterative decoder of the QC-LDPC code decoder based on RMP scheduling established in step 2: the received one frame of channel likelihood ratio soft information, according to the partition in the parity check matrix The channel information is stored in the P-block RAM storage block Mλp of the variable node soft information storage unit RAM_λ, and the data and address of the p-th storage block Mλp correspond to the column where the non-zero element in the row corresponding to the p-th way in the partition is located , the storage address of each storage block ranges from 0 to aJ-1, a is the line weight of the QC-LDPC code, and J is the number of lines corresponding to the p-th road in each partition; at the same time, the check node soft information storage unit RAM_Λ The data stored in is all initialized to 0, and the number of iterations iter_time is initialized to 0;

Step 4, perform iterative decoding operation: the decoding process control module PCU and the memory address generation module ADU jointly control the iterative decoding module IDU and the soft information storage module to update the operation;

Step 4.a) The p-th CNU calculation module in the iterative decoding module IDU performs iterative decoding calculation on the p-th channel parallel information in the k-th partition. The information input by the module comes from the variable node soft information storage unit RAM_λ and calibration Verification node soft information storage unit RAM_Λ, and the result of iterative decoding is stored in the corresponding positions of these two storage units;

Wherein, when updating the information of the i-th row of the road, the RAM storage block of the variable node soft information storage unit RAM_λ corresponding to the p-th CNU calculation module is the information stored in the p-th RAM according to the memory address generation module ADU The given address is read out, and the address obtained by RAM_λ can be calculated as follows: <addr_kp0>+<i-1>;

When updating the information in the i-th row of the road, the RAM storage block of the check node soft information storage unit RAM_Λ corresponding to the p-th CNU calculation module is the information stored in the p-th RAM according to the memory address generation module ADU. The address of RAM_Λ is read out, and the address that RAM_Λ obtains is a consecutive addresses according to the storage block order, and a is the row weight of QC-LDPC code;

Step 4.b) The results calculated by the CNU calculation module are respectively stored in the storage blocks corresponding to the variable node soft information storage unit RAM_λ and the check node soft information storage unit RAM_Λ through the soft information exchange module INU, and the written address is determined by the corresponding Obtained by reading the address with a delay of a clock;

Step 4.c) Repeat Step 4.a) - Step 4.b) until all rows in each partition are updated;

Step 4.d), repeat step 4.a) ~ step 4.c), until the update of all partitions in the entire check matrix is completed;

Step 5: Repeat step 4 until the maximum number of iterations is reached, and read out the data in each storage block in the variable node soft information storage unit RAM_λ according to the stored order to make a decision and obtain a decoding result.

Beneficial effect

Compared with the traditional decoder, the decoder designed by the present invention adopts the decoding algorithm based on RMP, and in the process of each iterative decoding, it reduces the iterative delay by nearly half compared with the minimum sum decoding algorithm; In addition, for the quasi-cyclic characteristics of the QC-LDPC parity check matrix, a partial parallel processing decoding structure is adopted, and the parity check matrix is partitioned, and parallel iterative decoding is performed in the partitions, and the decoding delay and each partition The decoding parallelism is linearly inversely proportional, which doubles the throughput of the decoder, and ensures that this parallel method has the same performance as the serial RMP method, making the LDPC decoder suitable for high-speed data processing. Require. Applying the decoder design of the present invention can make the LDPC decoder adapt to more communication applications with high throughput.

Description of drawings

Fig. 1 is LDP{Calderbank, 1999#38}C decoding method flowchart of the present invention;

Fig. 2 is the structural representation of the LDPC decoder that adopts in the specific embodiment;

Fig. 3 is an explanatory diagram of the memory address control module of the LDPC decoder in the specific embodiment;

FIG. 4 is an explanatory diagram of an address allocation method in a specific embodiment.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

Referring to Fig. 2, the RMP-based partially parallel QC-LDPC decoder provided by the present invention is mainly divided into 6 parts, which are variable node soft information storage unit RAM_λ, check node soft information storage unit RAM_Λ, iterative decoding module IDU, Decoding and judging module DJU, decoding process control module PCU. Among them, the variable node soft information storage unit RAM_λ is used to store the initialization information and variable node soft information in the iterative decoding process, which includes the P block RAM storage block Mλp; the check node soft information storage unit RAM_Λ is used for Store the check node soft information updated in the iterative decoding process, which includes P blocks of RAM storage blocks _MΛp ; the memory address generation module ADU is used to generate the variable node soft information used in the QC-LDPC decoder to store Unit and check node soft information storage unit; iterative decoding module IDU, used to perform parallel update operation on check node soft information and variable node soft information in the iterative process, including P CNU calculation modules; decoding judgment module The DJU is used to judge and process the information to be output in the variable node soft information storage unit; the decoding process control module PCU is used to generate control signals for the entire decoding process. Among them, the pth RAM storage block in the RAM_λ and RAM_Λ modules stores the variable section and check node soft information corresponding to the non-zero elements in the row included in the pth decoding iteration in each partition; each block of RAM The storage block contains two read-write ports, and the read-write mode is "read first, then write". Each read-write port is connected to the p-th CNU computing module, and each port is responsible for reading and writing one channel of data; the memory address The generation module ADU is composed of the RAM_λ memory address generation sub-module and the RAM_Λ memory address generation sub-module, each sub-module is composed of P initial address memories and P address offset calculators; the memory address generation module ADU has 2P output ports , respectively connected to the read-write address ports of the P read-write ports of the RAM_λ module and the RAM_Λ module.

The connection relationship between the various modules of the decoder is as follows:

Each piece of RAM in the RAM_λ module has two read-write ports, which are respectively responsible for reading and writing iteratively decoded soft information. The mode is "read first and then write". The "port is connected with the pth input port of the INU module and the DJU input port of the decoding judgment module, and the "write" port of the pth block RAM is connected with the pth input port of the INU module and the input port of the decoder at the same time; Each piece of RAM in the RAM_Λ module has two read-write ports, which are respectively responsible for reading and writing iteratively decoded soft information. The mode is "read first and then write". The two ports of the p-th RAM The ports are connected to the input and output ports of the pth iterative decoding calculation unit CNU_p at the same time; the P output ports and input ports of the INU module are respectively connected to the input ports and output ports of the P iterative decoding calculation unit CNU, and the other P The output port and input port are respectively connected to the input port and output port of the P block RAM in the RAM_λ module; the 2p output ports of the ADU module are respectively connected to the RAM_λ module and the p RAM read and write address ports in the RAM_Λ module, responsible for reading and writing Address control.

With reference to Fig. 1, the method for iterative decoding provided by the present invention, its steps are as follows:

Step 1, initialization: store the received channel likelihood ratio soft information of one frame into the P block RAM storage block Mλp of the variable node soft information storage unit RAM_λ according to the partition in the parity check matrix, the pth block The data and address of the storage block Mλp correspond to the column of the non-zero element in the row corresponding to the pth road in the partition. The storage address range of each storage block is 0~aJ-1, and a is the QC-LDPC code Line weight, J is the number of lines corresponding to the p-th road of each partition; at the same time, all the data stored in the check node soft information storage unit RAM_Λ is initialized to 0, and the number of iterations iter_time is initialized to 0 times;

Step 2, iterative decoding operation, the iterative decoding module IDU performs calculation update on the soft information storage module:

Each calculation unit CNU_p in the iterative decoding module IDU updates the information in the p-th block RAM of the RAM_λ and RAM_Λ modules connected to it one by one in the order of rows, and the P calculation units simultaneously update the P channels in a partition of the check matrix Perform parallel decoding;

Each calculation module CNU_p in the described iterative decoding module IDU is divided into three steps to the update of the information in each RAM: CNU_p first reads the software required for updating from the pth block RAM of the RAM_λ and RAM_Λ modules respectively. information; CNU_p performs iterative decoding update calculation according to the read soft information; finally writes the external information obtained by the update calculation back into the p-block RAM of the RAM_λ and RAM_Λ modules;

The iterative decoding module IDU updates the information of each block of RAM of the RAM_λ and RAM_Λ modules, and needs to read and write the soft information in each block of RAM, wherein the data reading and writing of each block of RAM adopts a cyclic Address reading and writing management method, with reference to Figure 4, its address allocation method is as follows:

a) The check node soft information storage module RAM_Λ saves the check soft information of the p-th parallel processing in the p-th block RAM_p according to the row order of each partition, 1≤p≤P (P is the number of parallel processing channels, Fig. In P=4), the address bits of each RAM are 0~(aJ-1);

b) Each sub-unit matrix is divided into P parts according to the column order, and the variable node soft information corresponding to the p-th part of each sub-matrix is stored in the p-th block RAM_p of the RAM_λ module, 1≤p≤P (P is parallel processing The number of channels, P=4 in the figure), the address bits of each block of RAM are 0~J-1;

c) Under the above-mentioned premise, the ADU module performs offset calculation through the initial address of each sub-matrix, and obtains the check node soft information corresponding to the variable node soft information stored in each block of RAM in the variable node soft information storage module, and The result is sent to the INU module, and the variable node soft information obtained from the P block RAM is sent to the corresponding calculation module CNU for iterative decoding update.

For example, if a circulant matrix obtained by circling a 64×64 unit matrix has a head address of 23 and performs 4-way parallel decoding, each RAM in the RAM_Λ module stores 8 check node soft information, and the address is 0～ 15. Similarly, each RAM in the RAM_λ module stores 8 check node soft information, with addresses ranging from 0 to 15; the relationship between the soft information addresses stored in each RAM and the calculation module is shown in the following table:

Step 3, repeat step 2 until the update of each path in this partition is completed;

Step 4, repeat step 2 and step 3 until the update of all partitions in the entire check matrix is completed, and the number of iterations iter_time is increased by 1;

Step 5: Repeat steps 2 to 4 until the number of iterations iter_time reaches the maximum value iter_MAX, read out the data in each storage block in the variable node soft information storage unit RAM_λ according to the order of storage, and make a decision to obtain the decoding result.

Compared with the LDPC decoder that adopts the SMP minimum sum decoding algorithm, under the same situation of the number of iterations and the parallel number, the decoder of the present invention can reduce nearly half of the decoding delay; compared with the LDPC decoder that adopts RMP In comparison, under the condition of the same number of iterations, the decoder of the present invention can reduce the decoding delay by half without affecting the decoding performance.

The above description is only a preferred embodiment of the present invention, and the present invention should not be limited to the content disclosed in this embodiment and the accompanying drawings. All equivalents or modifications accomplished without departing from the disclosed spirit of the present invention fall within the protection scope of the present invention.

Claims (1)

1. the part parallel QC-LDPC interpretation method of dispatching based on RMP, is characterized in that: specifically comprise the following steps:

Step 1, is heavily a to row, and the check matrix H (M, N) of the QC-LDPC code that column weight is b is carried out subregion, and concrete grammar is:

(1) find the minimal circulation submatrix of QC-LDPC code check matrix, and obtain its size for I * I, I is constant;

(2), under the prerequisite that is 1 at the column weight that guarantees each subregion, with subregion of every J behavior, check matrix is divided into K subregion, I=nJ wherein, M=KJ, n is integer, generally n=1, i.e. I=J;

(3) determine that in subregion, number P is processed in multidiameter delay decoding, have Pl=J, l is the line number that in each subregion, each road decoding is processed;

Step 2, on the basis of subregion, sets up the QC-LDPC code decoder based on RMP scheduling, and its composition comprises:

The soft information memory cell RAM_ of variable node λ, for the initialization information of iterative decoding process and the soft information of variable node are stored, wherein comprises P block RAM memory block M λ p; P block RAM memory block M λ p, has stored the soft information of the corresponding variable node of nonzero element in the row that the p road decoding iteration in each subregion comprises;

The soft information memory cell RAM_ of check-node Λ, stores for the soft information of check-node that iterative decoding process is upgraded, and wherein comprises P block RAM memory block M Λ _p; P block RAM memory block M Λ wherein _p, stored the soft information of the corresponding check-node of nonzero element in the row that the p road decoding iteration in each subregion comprises;

Storage address generation module ADU, for generation of the soft information memory cell of variable node used in QC-LDPC decoder and the soft information memory cell of check-node; By RAM_ λ storage address generation submodule and RAM_ Λ storage address, produce submodule and form, each submodule is comprised of P initial address memory and P address offset calculator; Each submodule has P integrated signal output port, its output by initial address memory from P initial address memory sum counter; ADU has 2P output port, is connected respectively with RAM_ λ module with the read/write address port of P reading-writing port of RAM_ Λ module;

Iteration decoding module IDU, for the soft information of the check-node of iterative process and the soft information of variable node are walked abreast and upgrades computing, wherein comprises P CNU computing module;

Decoding judging module DJU, carries out decision process for the soft information memory cell of variable node being about to the information of output;

Soft information exchange module INU, for will delivering to corresponding CNU computing module from the data of the different RAM memory blocks of RAM_ λ module when the iterative decoding, and will be accordingly more new data return to RAM memory block; INU has 2P input port and 2P output port, wherein P input port and output port are connected with output port and the input port of RAM in RAM_ λ module, and P input port and output port are connected with output port and the input port of RAM in P CNU computing module; By INU module synthesis signal, P the soft information distribution of output in RAM_ λ module, in P CNU module, and stored into the soft information of the output of P CNU module in RAM_ λ module in the RAM of correspondence;

Decoding process control module PCU, for generation of the control signal of whole decoding flow process, comprising INU module synthesis signal;

Described every block RAM memory block M λ p and M Λ _pcontain two reading-writing port, its read-write mode is all " write-after-reads ", and each reading-writing port is all connected with p piece CNU computing module, and each is responsible for the read-write of a circuit-switched data each port;

Step 3, the iterative decoder of the QC-LDPC code decoder based on RMP scheduling that step 2 is set up carries out initialization: by the soft information of a frame channel likelihood ratio receiving, according to the subregion in check matrix, channel information is stored in the P block RAM memory block M λ p of the soft information memory cell RAM_ of variable node λ, the data of p piece memory block M λ p are carried out corresponding with address according to the row at the nonzero element place in row corresponding to the p road in subregion, the memory address scope of each memory block is 0～aJ-1, a is that the row of QC-LDPC code is heavy, J is each line number corresponding to subregion p road, meanwhile, the data of storing in the soft information memory cell RAM_ of check-node Λ are all initialized as to 0, and iterations iter_time is initialized as 0 time,

Step 4, carries out iterative decoding computing: iteration decoding module IDU and soft information storage module described in decoding process control module PCU and storage address generation module ADU co-controlling carry out computing renewal;

Step 4.a) p CNU computing module in iteration decoding module IDU carries out iterative decoding calculating to the p road parallel information in k subregion, the information of module input is from variable node soft information memory cell RAM_ λ and the soft information memory cell RAM_ of check-node Λ, and the result of iterative decoding is saved on these two corresponding positions of memory cell;

Wherein, when upgrading the capable information of this road i, the RAM memory block of the variable node soft information memory cell RAM_ λ corresponding with p CNU computing module, be that read the address that p RAM canned data wherein provides according to storage address generation module ADU, the address that RAM_ λ obtains can be according to calculating as follows: k subregion p road decoding initialization address addr_kp0>+<i-1> of <;

When upgrading the capable information of this road i, the RAM memory block of the check-node soft information memory cell RAM_ Λ corresponding with p CNU computing module is that read the address that p RAM canned data wherein provides according to storage address generation module ADU, the address that RAM_ Λ obtains is according to a of memory block order continuous address, and a is that the row of QC-LDPC code is heavy;

Step 4.b) result that CNU computing module calculates is saved in respectively in variable node soft information memory cell RAM_ λ and memory block corresponding to the soft information memory cell RAM_ of check-node Λ by soft information exchange module INU, and the address writing is that the delay of carrying out a clock by corresponding reading address obtains;

Step 4.c) repeating step 4.a)-step 4.b), until complete the renewal of all row in each subregion;

Step 4.d), repeating step 4.a)～step 4.c), until complete the renewal of all subregions in whole check matrix;

Step 5, repeating step four, until reach maximum iteration time, and the data in each memory block in the soft information memory cell RAM_ of variable node λ are adjudicated according to calling over of storage, obtain decode results.

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