CN106911336A - The high-speed parallel low density parity check coding device and its interpretation method of multi-core dispatching - Google Patents

Abstract

The invention relates to a multi-core scheduling high-speed parallel low-density parity-check decoder and a decoding method thereof, belonging to the technical field of wireless communication. The decoder includes a sequentially connected data cache module, a multi-core scheduling module, and an LDPC parallel decoding core composed of multiple decoding cores; According to the working status of a single codeword, the word to be decoded with a single codeword length is assigned to the decoding core in the idle state that has completed the decoding. The multi-core scheduling module checks whether the decoding core has been decoded. If it meets the decoding result verification , then output the decoding result to the multi-core scheduling module. After the decoding is completed, the multi-core scheduling module will output the decoding results of each decoding core to the data buffer module in the same order according to the codeword allocation order, and the data buffer module will decode data output. The invention effectively improves the computing efficiency and decoding rate of the decoder by adding a novel multi-core scheduling module.

Description

High-speed parallel low-density parity-check decoder with multi-core scheduling and its decoding method

technical field

The invention belongs to the technical field of wireless communication, and relates to a multi-core scheduling high-speed parallel low-density parity-check decoder and a decoding method thereof.

Background technique

With the rapid development of the economy, both civilian and military fields have put forward higher requirements for high resolution and high precision, and a mature and stable high resolution (high resolution) system is very important for national military security and many civilian applications. Fields are important supports. In the high-resolution field, the United States first developed a high-resolution observation satellite, making this technology a world leader, and due to limited space resources and the extraordinary importance of data in the era of big data, the leading high-resolution technology The country is unwilling to share resources, so it is urgent to carry out high-scoring research and development independently.

With the gradual advancement of the high-resolution project (that is, the major project of the high-resolution Earth observation system), the number of various spacecraft and detectors has increased rapidly, the data rate of detection information has become higher and higher, and the amount of data generated is unprecedentedly large. In recent years, data acquisition technology has developed rapidly, and digital image processing technology has become increasingly mature. In order to obtain more comprehensive data analysis, it is required that the receiver can receive and process a larger amount of data. At present, the 300Mbps satellite high-speed data transmission system has been widely used, and the transmission rate has been required to reach more than 3Gbps, and will continue to increase to 10Gbps or even 30Gbps in the future. Therefore, a transmission system that can adapt to the requirements of high-speed data transmission is an important support for the development of high-resolution projects. However, there is a direct proportional relationship between the data transmission rate and the system power. An increase in the rate will inevitably lead to an increase in the system power, and the system resources themselves are strictly limited. Therefore, how to process higher-rate data under limited resources has become an important issue for high-speed data transmission systems. .

Low Density Parity Check (LDPC) codes have attracted more and more attention due to their code word construction method which is very close to the theoretical limit coding gain. Its decoding complexity is low, it can be decoded in parallel, and it is easy to detect whether there is an error in decoding. It can meet the requirements of high-speed data transmission and high coding gain. It is currently more and more widely used in high-speed satellite data transmission systems. . In general, the decoding capability of a single decoding core is limited. If it is necessary to achieve high-speed decoding that can match high-speed data transmission, multiple decoding cores usually need to work in parallel. As shown in Figure 1, it is a traditional high-speed LDPC decoder, including sequentially connected data cache modules, multi-core scheduling modules, and LDPC parallel decoding cores composed of multiple decoding cores; The connected input data cache module, soft information storage module, variable node array module, control module, and the check node array module, variable node storage module, check node storage module respectively connected to the control module, and the variable node array module in sequence A connected decoding result storage module and an output buffer module. Each module is realized by an FPGA chip.

The decoding method of this traditional high-speed LDPC decoder is as follows: the data to be decoded first enters the data buffer module (constituted by the FIFO in the FPGA chip), and sends the data to each LDPC in parallel for decoding according to the instructions issued by the multi-core scheduling module decoded in the core. The dotted line box is a parallel decoding core, and each decoding core works in the same way, that is, a single code word first enters the input data buffer module for buffering, and its function is to provide a single code word with the same frequency as the decoding core working clock for the subsequent module. Word information, and then the information to be translated enters the soft information storage module, according to the fixed number of iterations (denoted as N times) and decoding cycle set by the control module, the soft information is read from the storage module, and circulates through the variable node array module The sum check node array module is output to the decoding result storage module and the output buffer module after reaching the number of iterations. The function of the output buffer module is to output the decoding result to the subsequent module at a certain clock duty ratio according to requirements. The multi-core scheduling module concatenates the data according to the number of each decoding core and then directly outputs it through the data cache module. It can be seen that the traditional high-speed LDPC decoder is usually implemented in a multi-core parallel method, which simply replicates the single-core decoder, and the front end is connected to the traditional multi-core scheduling module and data cache module to control the entire system.

However, the correct decoding of the traditional high-speed LDPC decoder is not only related to the normal operation of each parallel decoder, but also the scheduling function of the multi-core scheduling module is more critical. The traditional multi-core scheduling module is mainly responsible for the order allocation of codewords, that is, after the information to be decoded is cached in the data cache module and reaches the storage depth of a codeword length, the multi-core scheduling module will allocate the codewords to be decoded according to the specified single codeword length Read out from the data cache module sequentially, and assign it to each decoding core in sequence according to the numbering order of the decoding cores. Since the number of decoding iterations N set by the control module in the parallel decoding core is fixed, the multi-core scheduling module only needs to wait for a fixed time to obtain the decoded data of each decoding core, and then transfer the data according to the number of the decoding core The data can be spliced and output. Then the multi-core scheduling module continues to assign the words to be decoded to each decoding core in sequence according to the steps of reading, assigning, and splicing, and outputs the decoding data after waiting, and repeats this process until all the words to be decoded are decoded or received stop signal. Since the function of the multi-core scheduling module in the traditional high-speed LDPC decoder is simple and the timing is fixed, the multi-core scheduling module can be directly implemented using a counter.

The workflow of the traditional multi-core scheduling module is shown in Figure 2, taking a quad-core parallel decoder as an example. After setting a fixed maximum number of iterations, the multi-core scheduling module waits for the data input to the data buffer module to reach a codeword before starting to work. It reads the data of the input data buffer module in units of one codeword length, and sends them to decoding core 1, decoding core 2, decoding core 3 and decoding core 4 in sequence, and each decoding core is always Work, the multi-core scheduling module waits during the decoding period until all the decoding cores reach the maximum number of iterations, and re-decodes the decoded data in the order of decoding core 1, decoding core 2, decoding core 3, and decoding core 4 Combine and output. The multi-core scheduling module continues to perform the above assignment work until the system stops. Since the four decoding cores stop decoding after reaching the maximum number of iterations, the work progress of the four decoding cores remains consistent, and only four codewords can be decoded in each decoding cycle. .

This method is difficult to implement, but in the process, the traditional parallel decoding only simply copies a single decoding core, and sends the word to be decoded to each decoding core in turn for decoding. According to the simulation situation, each decoding core has a fixed number of iterations set in advance to ensure the bit error rate under the specified requirements. Therefore, each decoding core also maintains a synchronous working state, and the code word allocation is easy to realize. However, in the actual decoding process, each decoding core needs to perform a fixed number of iterations when decoding, and not every codeword needs the maximum number of iterations to decode successfully. After the decoding is completed, for the codewords that have been successfully decoded, continuing to iterate will not bring performance improvement, but will reduce the decoding efficiency and cause a waste of resources.

These are very critical issues for high-speed decoders.

It can be seen that the overall decoding efficiency of the traditional parallel decoder is not high enough due to its fixed number of iterations, and hardware resources are wasted in the case of limited resources. At present, there is an urgent need for a new multi-core scheduling module that can control the number of iterations according to the actual decoding completion, and can schedule the entire decoder as a whole, so as to make full use of limited resources and improve the overall decoding efficiency.

Contents of the invention

The purpose of the present invention is to solve the problem of insufficient utilization of hardware resources in traditional high-speed LDPC decoders with limited resources, and propose a new type of multi-core scheduling high-speed parallel low-density parity check (LDPC) decoder and its decoder. The decoding method can control the decoding core to perform a non-fixed number of iterations through a new multi-core scheduling module, thereby effectively improving the decoding efficiency and making full use of hardware resources.

The present invention proposes a multi-core scheduling high-speed parallel low-density parity-check decoder. The decoder is implemented by an FPGA chip, including sequentially connected data cache modules, multi-core scheduling modules, and multiple decoding cores. The LDPC parallel decoding core; it is characterized in that: the data cache module is formed by the FIFO inside the FPGA, and this FIFO has a deeper storage depth to ensure that when the next codeword arrives, there is enough buffer space; the multi-core scheduling The module is used to control the scheduling of the entire high-speed LDPC decoder. When the upper-level data cache module stores more than one codeword of data, it sends a decoding start signal to the subsequent parallel decoding core to allocate the cached data to each The decoding core decodes, and at the same time receives the decoding end signal fed back by the parallel decoding core of the subsequent stage, checks whether each decoding core is in an idle state, and sends the next word to be decoded in the previous stage data buffer module to the decoding in the idle state The code core performs decoding; after the decoding is completed, according to the codeword distribution order, and in the same order, the decoding results of each decoding core are uniformly output to the data buffer module; each decoding in the LDPC parallel decoding core The core consists of a soft information storage module, a variable node array module, and a control module connected in sequence, and a check node array module, a variable node storage module, and a check node storage module connected to the control module, and a translator connected to the variable node array module. A code result storage module; the variable node array module is also connected with the check node storage module and the variable node storage module.

The present invention proposes a decoding method of a high-speed parallel low-density parity-check decoder as described above, characterized in that:

The word stream to be decoded first enters the data cache module, and the multi-core scheduling module assigns the word to be decoded with a single codeword length to the decoding core in the idle state that has completed decoding according to the working status of the back-end parallel decoding core. After each decoding core receives the word to be decoded, it first puts it into the soft information storage module, circulates through the variable node array module and the check node array module for decoding, and each decoding result is stored in the In the decoding result storage module, the multi-core scheduling module checks whether the decoding core has been decoded. If it meets the decoding result verification, the decoding result is output to the multi-core scheduling module, and the decoding core is turned into an idle state; otherwise The decoding core continues to perform iterative decoding until it reaches the set maximum number of iterations. If it has not been correctly decoded at this time, it will forcibly stop the decoding to check the decoding of the current codeword, output the decoding result and feedback the decoding Failure information; the multi-core scheduling module sends the next word to be decoded to the idle decoding core for decoding; after decoding, the multi-core scheduling module sends the decoding results of each decoding core in the same order according to the code word allocation order Unified output to the data cache module, and the data cache module outputs the decoded data.

Technical characteristics and beneficial effects of the present invention:

1) The data cache module of the present invention increases the storage depth to ensure that when the next codeword arrives, there is enough buffer space until a certain decoding core completes the decoding of the previous codeword and assigns the new codeword to the the decoding core;

2) The multi-core scheduling module controls the scheduling of the entire high-speed LDPC decoder. The multi-core scheduling module controls the decoding core to perform a non-fixed number of iterations, thereby effectively improving the decoding efficiency.

3) Since there is a data cache module at the front end of the multi-core scheduling module, which is used to cache data to be decoded, and there is code word scheduling and control of the multi-core scheduling module, so the input and output FIFOs are omitted in a single decoding core to save hardware resources.

The present invention greatly reduces the calculation amount of the traditional method through very small hardware overhead, significantly improves the overall efficiency of the system and saves the overall hardware resources.

Description of drawings

Figure 1 is a structural block diagram of a traditional multi-core parallel LDPC decoder.

Fig. 2 is a working diagram of a traditional multi-core scheduling module.

Fig. 3 is a structural block diagram of the multi-core scheduling high-speed LDPC decoder of the present invention.

Fig. 4 is the distribution of the maximum number of iterations in the embodiment of the present invention.

Fig. 5 shows the relationship between the number of iterations and the decoding performance of the embodiment of the present invention.

FIG. 6 shows the relationship between the number of iterations and the amount of computation saved in the embodiment of the present invention.

Fig. 7 shows the increase of input FIFO depth according to the embodiment of the present invention.

detailed description

The present invention will be described in further detail below in conjunction with the accompanying drawings.

A high-speed LDPC decoder with multi-core scheduling proposed by the present invention, as shown in Figure 2, includes a data buffer module, a multi-core scheduling module connected in sequence, and an LDPC parallel decoding core composed of multiple decoding cores, which can be combined with The traditional LDPC decoder is also realized by an FPGA chip; the difference between this multi-core scheduling high-speed LDPC decoder and the traditional decoder is:

1) The data buffer module is composed of FIFO inside the FPGA. This FIFO has a deeper storage depth than the FIFO in the traditional LDPC decoder data buffer module, so that more codeword sequence information can be cached to ensure that the next codeword arrives. , can have enough buffer space, after a decoding core completes the decoding of the previous code word, assign the new code word to the decoding core;

2) The multi-core scheduling module is used to control the scheduling of the entire high-speed LDPC decoder. When the upper-level data cache module stores more than one codeword of data, it sends a decoding start signal to the subsequent parallel decoding core, and the buffer The data is allocated to each decoding core for decoding, and at the same time, it receives the decoding end signal fed back by the subsequent parallel decoding core, checks whether each decoding core is in an idle state, and sends the next word to be decoded in the previous data buffer module to the The decoding core in the idle state performs decoding; after the decoding is completed, the decoding results of each decoding core are uniformly output to the data buffer module in the same order according to the codeword allocation sequence;

3) Each decoding core in the LDPC parallel decoding core is composed of a soft information storage module, a variable node array module, and a control module connected in sequence, and a check node array module, a variable node storage module, and a calibration node respectively connected to the control module. A verification node storage module, a decoding result storage module connected to the variable node array module; the variable node array module is also connected to the verification node storage module and the variable node storage module. Wherein the control module no longer sets a fixed number of iterations for all parallel decoding cores, but only sets the maximum number of iterations (the maximum number of iterations is set slightly larger than the fixed number of iterations N set by the traditional control module). And control the decoding cycle of each iteration, that is, sequentially substitute the soft information into the variable node array module and the check node array module for calculation. Since the data cache module is used to cache the data to be decoded, and the storage depth is increased, and there is codeword scheduling and control of the multi-core scheduling module, the LDPC parallel decoding core of the present invention omits each decoding core of the traditional LDPC decoder The internal input data buffer module is used to provide the subsequent module with a single code word information with the same frequency as the decoding core working clock, and the output for outputting the decoding result to the subsequent module at a certain clock duty cycle as required Data caching module to save hardware resources.

The present invention sets the depth increment of FIFO (deeper than FIFO in the traditional LDPC decoder data cache module) and is specifically described as follows: if M codewords need to be decoded altogether, wherein a codeword is correctly decoded after iteration N times , b codewords are correctly decoded after iteration N+1 times, and c codewords are correctly decoded after iteration N+2 times, then the required average number of iterations N′ of the M codewords can be calculated according to b and The probability of c is calculated, and according to the average number of iterations, the required bit depth storage capacity of the FIFO can be calculated. By analogy, different numbers of iterations greater than N are required according to different numbers of codewords. Using this method, the increase in FIFO depth in the data cache module of the multi-core scheduled high-speed LDPC decoder can be obtained.

The decoding method of the high-speed LDPC decoder of multi-core scheduling proposed by the present invention is as follows: the word stream to be decoded first enters the data buffer module, and the multi-core scheduling module converts the single code word length according to the working status of the back-end parallel decoding core. The words to be decoded are assigned to the decoding cores in the idle state that have completed the decoding, and each decoding core puts them into the soft information storage module after receiving the words to be decoded, and when the maximum number of iterations is not reached Before, loop through the variable node array module and the check node array module to decode, each decoding result is stored in the decoding result storage module, and the multi-core scheduling module checks whether the decoding core has been decoded. If the decoding result is verified, the decoding result is output to the multi-core scheduling module, and the decoding core turns into an idle state; otherwise, the decoding core continues to perform iterative decoding until the set maximum number of iterations is reached. If the decoding is correct, the decoding is forced to stop and the decoding of the current codeword is checked, the decoding result is output and the decoding failure information is fed back; the multi-core scheduling module sends the next word to be decoded to the idle decoding core for decoding; After the decoding is completed, the multi-core scheduling module outputs the decoding results of each decoding core to the data cache module according to the order of the codeword allocation and in the same order, and the data cache module outputs the decoded data.

The core of the present invention is the comprehensive control and scheduling of the whole system by the multi-core scheduling module, and the working signal of the multi-core scheduling module depends on whether each parallel decoding core completes decoding, that is, a non-fixed iteration number decoding mechanism. This mechanism is manifested in the fact that if the multi-core scheduling module detects that the codeword decoded by a certain decoding core conforms to the verification relationship, the decoding core immediately stops iterating and becomes an idle decoding core, waiting for the scheduling module to allocate new codewords. The verification of the decoding result is to perform an XOR operation on the positive and negative values of the output information of each variable node i that has a link relationship with the check node j, and take the result of the XOR operation as the verification result, as shown in the following formula :

Where i is the variable node connected to check node j, the number of which is q _ij represents the output external information of the variable node i that has a connection relationship with the check node j, check is the output result of the check, sgn() is a sign function that returns the positive and negative values of the output external information, 0 is positive and 1 is negative , It is an XOR operation; check=0 means that the verification relationship is satisfied; if all the check nodes satisfy the verification relationship of check=0, it means that the codeword has been decoded correctly, or the codeword has been decoded into a codeword Another codeword in the space; both of the above two cases indicate that the decoding has been completed, and continued iteration will not have an effect on the decoding result, so the iteration of the current codeword should be stopped at this time, and the decoding core is in an idle state And the decoding of a new codeword can be started.

The present invention aims at the problem that the traditional multi-core scheduling cannot make full use of the decoding cycle, and improves the traditional scheduling method. The multi-core scheduling module of the present invention allocates the codewords to be allocated. The specific method is as follows: Let the LDPC parallel decoding core be m When the storage capacity in the input FIFO reaches one codeword, the multi-core scheduling module starts to work. The multi-core scheduling module first allocates the codewords in the order of each decoding core number from small to large, and sends the first m codewords to m respectively. After the initial allocation, the multi-core scheduling module has been in the standby detection state. When the multi-core scheduling module is to allocate each subsequent codeword, it will judge which decoding core according to the result returned by the decoding core. When the core is in the idle state, record the number of the decoding core and temporarily store the code word that has been decoded, and at the same time read a word to be decoded from the front-end data buffer module and assign it to the decoding core that is currently in the idle state. The core performs decoding, and then continues to enter the standby detection state, waiting for the next decoding core to complete the decoding; then sequentially schedule the subsequent codewords to the decoding cores in the idle state for decoding (without waiting for m decoding cores After all the decoding is completed, a new round of code word allocation is carried out, which fully utilizes the decoding time of each decoding core). If multiple decoding cores complete the decoding at the same time, the words to be decoded are allocated in ascending order of the numbers of the decoding cores.

Provide the application effect of the embodiment of the present invention below:

Taking the LDPC code with a code length of 12288 bits and an information bit length of 10240 bits as an example, there is no maximum number of iterations in the decoding process, and the condition for stopping decoding is that the decoding is correct.

As shown in Fig. 4, the number of iterations executed for correct decoding of each codeword is shown, the abscissa is the sequence number of each codeword, and the ordinate is the number of iterations executed when the codeword is correctly decoded. In the figure, the maximum number of iterations is 29, the minimum number of iterations is 12, and the number of iterations to complete decoding is very dense at 16, and only 0.2% of the codewords need the maximum number of iterations. In traditional parallel decoders, in order to meet the decoding requirements and control the process simply, it is usually necessary to set the maximum number of iterations, and each decoding cycle is set according to the maximum number of iterations. For this embodiment, the maximum number of iterations is set to 29 times, so in fact only 0.2% of the codewords need to iterate 29 times, and 99.8% of the codewords do not need to reach the maximum number of iterations, thus causing an increase in the number of iterations Waste, which in turn causes a waste of hardware resources.

Fig. 5 is a graph showing the relationship between the number of iterations and decoding performance, the abscissa is the maximum number of iterations, and the ordinate is the bit error rate of the decoding result under the maximum number of iterations. When the signal-to-noise ratio is appropriate, the increase of the number of iterations has a significant effect on the reduction of BER, and every two iterations, the BER is reduced by an order of magnitude. Therefore, a new multi-core scheduling parallel decoding method with a non-fixed number of iterations is used to allocate the time saved for codewords that require fewer iterations to decode codewords that require more iterations to be decoded correctly, which is equivalent to increasing The overall effective number of iterations is increased, and the average number of iterations is reduced. From the perspective of decoding calculation, the average number of iterations is positively correlated with the working clock of the decoder, that is, the average number of iterations is small, the working clock of the decoder is low, and the low clock rate helps to improve the stability of the hardware circuit, and at the same The lower the decoding processing rate, the lower the amount of computation. Figure 6 shows the relationship between the maximum number of iterations and the amount of computation saved, the abscissa is the maximum number of iterations, and the ordinate is the percentage of the amount of computation saved. In this case, the average number of iterations is reduced from 29 to 16, and the amount of computation is reduced by 46.7%. On the one hand, hardware resources are more fully utilized than traditional methods, and on the other hand, the amount of computation is greatly reduced. Under the premise, the present invention significantly improves the overall efficiency of the system and saves hardware resources.

The new multi-core scheduling greatly improves the utilization rate of the decoding core, but also introduces two additional overheads, one is the verification relationship verification module added by the check node, and the other is the increase in the depth of the input FIFO. The essence of the verification module is the XOR operation of all the sign bits of the input external information, which is represented as a few LUT resources on the hardware.

In the traditional mode, the setting of the maximum number of iterations N is often set according to the actual data rate, decoding performance index, and decoding rate supported by the hardware, while the increased FIFO depth required by the new multi-core scheduling method is calculated on the basis of N. Suppose a total of 10 codewords need to be decoded, of which 9 codewords are correctly decoded after N iterations, and 1 codeword is correctly decoded after N+1 iterations, then the probability that the FIFO needs to deepen the bit depth is this Probability of occurrence of 1 codeword; if 8 codewords are correctly decoded after N iterations, 1 codeword is correctly decoded after N+1 iterations, and 1 codeword is correctly decoded after N+2 iterations code, the probability that the FIFO needs to deepen the bit depth is the probability that iterations N+1 and N+2 occur each time. Since codewords that require more than N iterations occur at different times, they have different impacts on the FIFO depth, so the calculation of the probability also needs to take into account the order in which the codewords appear. Figure 7 shows the increased bit amount of FIFO depth calculated after each codeword is decoded, the abscissa is the sequence number of the word to be decoded, and the ordinate is the number of bits to be decoded in the current FIFO buffer. It can be seen that when the maximum number of iterations is reduced from 29 to 16, the input FIFO depth only needs to increase the length of two codewords, but the decoding performance has been greatly improved, and the maximum number of buffered bits in Figure 7 does not exceed two codewords words, so when the FIFO depth is increased by two codeword lengths, the FIFO will not be full during the entire decoding process. In Figure 6, if the number of iterations increases from 16 to 29, the input FIFO only increases the depth of two codewords, and the bit error rate decreases from 10 ^-4 to 10 ^-9 , so the increase in FIFO depth Compared with the improvement of decoding performance, the small amount of LUT usage brought by the volume and verification relationship verification module is completely acceptable. Therefore, the present invention greatly reduces the calculation amount of the traditional method through very small hardware overhead, and remarkably improves the efficiency of the whole system and saves the whole hardware resources.

Claims (4)

1. A multi-core scheduling high-speed parallel low-density parity-check decoder, the decoder is implemented using an FPGA chip, including sequentially connected data buffer modules, multi-core scheduling modules, and LDPC composed of multiple decoding cores Parallel decoding core; it is characterized in that: described data cache module is made of FIFO inside FPGA, and this FIFO has deeper memory depth, when guaranteeing that next code word arrives, can have enough buffer space; Described multi-core scheduling module uses To control the scheduling of the entire high-speed LDPC decoder, when the upper-level data cache module stores more than one codeword of data, it sends a decoding start signal to the subsequent parallel decoding core to allocate the buffered data to each decoding Core decoding, while receiving the decoding end signal fed back by the parallel decoding core of the subsequent stage, checking whether each decoding core is in the idle state, and sending the next word to be decoded in the previous stage data buffer module to the decoding core in the idle state Decoding; each decoding core in the described LDPC parallel decoding core consists of a soft information storage module, a variable node array module, a control module connected in sequence, and a check node array module, a variable node array module and a variable node respectively connected to the control module A node storage module, a check node storage module, and a decoding result storage module connected to the variable node array module; the variable node array module is also connected to the check node storage module and the variable node storage module. 2. a kind of decoding method of decoder as claimed in claim 1, it is characterized in that, word stream to be decoded at first enters data cache module, by multi-core dispatching module according to the operating condition of back-end parallel decoding core, will The word to be decoded with a single codeword length is assigned to the decoding core in the idle state that has completed the decoding, and after each decoding core receives the word to be decoded, it first puts it into the soft information storage module, and loops Decoding is performed through the variable node array module and the check node array module, and each decoding result is stored in the decoding result storage module, and the multi-core scheduling module checks whether the decoding core has been decoded, and if it meets the decoding result check, then output the decoding result to the multi-core scheduling module, and the decoding core will turn into an idle state; otherwise, the decoding core will continue to perform iterative decoding until the set maximum number of iterations is reached. If the decoding has not been completed at this time , the decoding is forced to stop and check the decoding of the current codeword, output the decoding result and feedback the decoding failure information; the multi-core scheduling module sends the next word to be decoded to the idle decoding core for decoding; the decoding ends The post-multi-core scheduling module outputs the decoding results of each decoding core to the data cache module in the same order according to the codeword allocation order, and the data cache module outputs the decoded data. 3. The decoding method according to claim 2, wherein the decoding result is verified as performing exclusive OR on the positive and negative values of the output external information of each variable node i that has a link relationship with the check node j operation, and use the result of the XOR operation as the verification result, as shown in the following formula: $\mathrm{<span\; class="notranslate">\; c</span>}\mathrm{<span\; class="notranslate">\; h</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; c</span>}\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; sgn</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CirclePlus;</span>\mathrm{<span\; class="notranslate">\; sgn</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; q</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CirclePlus;</span>\mathrm{<span\; class="notranslate">\; ...</span>}<span\; class="notranslate">\; \&CirclePlus;</span>\mathrm{<span\; class="notranslate">\; sgn</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; q</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CirclePlus;</span>\mathrm{<span\; class="notranslate">\; ...</span>}<span\; class="notranslate">\; \&CirclePlus;</span>\mathrm{<span\; class="notranslate">\; sgn</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; q</span>}}_{{\mathrm{<span\; class="notranslate">\; d</span>}}_{{\mathrm{<span\; class="notranslate">\; c</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}}\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \&le;</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; \&le;</span>{\mathrm{<span\; class="notranslate">\; d</span>}}_{{\mathrm{<span\; class="notranslate">\; c</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}}$ Where i is the variable node connected to check node j, the number of which is q _ij represents the output external information of the variable node i that has a connection relationship with the check node j, check is the output result of the check, sgn() is a sign function that returns the positive and negative values of the output external information, 0 is positive and 1 is negative , It is an XOR operation; check=0 means that the verification relationship is satisfied; if all check nodes satisfy the verification relationship of check=0, the codeword has been decoded correctly, or the codeword has been decoded into a codeword space The other codeword in the above two cases all means that the decoding has been completed, and the decoding core is in an idle state. 4. decoding method as claimed in claim 2, it is characterized in that, multi-core dispatching module is as follows with the concrete method of code word distribution to be distributed: Let LDPC parallel decoding core be m, when input FIFO internal storage capacity reaches a code word The multi-core scheduling module starts to work. The multi-core scheduling module first allocates codewords in the order of each decoding core number from small to large, and sends the first m codewords to m decoding cores for decoding; after the initial allocation, The multi-core scheduling module has been in the standby detection state. When the multi-core scheduling module is to allocate each subsequent codeword, it can judge which decoding core is in the idle state according to the result fed back by the decoding core, and record the decoding core. Number and temporarily store the code word that has been decoded, and at the same time read a word to be decoded from the data cache module, assign it to the decoding core that is currently in the idle state for decoding, and then continue to enter the standby detection state, waiting The next decoding core completes the decoding; then the subsequent codewords are scheduled to the decoding cores in the idle state for decoding in turn; if multiple decoding cores complete the decoding at the same time, the decoding cores are numbered from small to large The order of the words to be decoded is allocated.