CN103560916B - High-speed data packet filtering circuit and method - Google Patents

Abstract

The present invention proposes a high-speed data packet filtering circuit, including: a first buffer, a second buffer, a preset dual-port RAM, a delayer and a comparator, and the input data includes: a packet header, a packet tail, data enable and 8-bit wide data; the input data is divided into two paths, one path is sent to the first buffer cache, and the other path is delayed by the delay device and filtered with the preset dual-port RAM in the The comparator performs a comparison, and the result signal generated by the comparison is sent to the second buffer cache under the control of the combination of the end of the packet and the synchronous clock, and is controlled by the combination of the packet header signal and the synchronous clock in the output data of the first buffer. The result signal is read out, and the data output by the first buffer is controlled by the read out signal. The high-speed data packet filtering circuit of the present invention only uses a one-bit wide FIFO, which simplifies circuit design and reduces design cost.

Description

A high-speed data packet filtering circuit and method

technical field

The invention relates to the field of network technology, in particular to a high-speed data packet filtering circuit, and also to a high-speed data packet filtering method.

Background technique

Data packet filtering is a key technology to realize network content analysis, monitor and maintain network information security. For data filtering in the current high-speed environment, the processing speed of software filtering algorithms is difficult to keep up with the pace of network development, and using hardware to filter high-speed network data has become an inevitable choice. Usually, the hardware filtering method is to buffer the currently filtered data packet first, and perform data comparison processing, and then determine the selection of the data packet according to the comparison result after the comparison is completed or the data packet is completed.

Due to the limitations of current hardware resources, in order to meet higher filtering efficiency, it is often necessary to discard or partially discard the content of the first compared data packet, which is not conducive to the analysis of the content of IP data. To realize the complete preservation of the current data packet, it is necessary to increase the buffer space and the corresponding processing circuit, which will increase the delay of the data packet, reduce the filtering efficiency, and increase the design cost.

Contents of the invention

The invention proposes a high-speed data packet filtering circuit and method, which solves the problem that the current data packet cannot be fully preserved in the prior art.

Technical scheme of the present invention is realized like this:

A high-speed data packet filtering circuit, comprising: a first buffer, a second buffer, a preset dual-port RAM, a delayer and a comparator;

The input data is divided into two paths, one path is sent to the first buffer cache, and the other path is delayed by the delayer and compared with the filtered data in the preset dual-port RAM in the comparator, The result signal generated by the comparison is sent to the second buffer buffer under the control of the combination of the end of packet and the synchronous clock, and the readout of the result signal is controlled by the combination of the packet header signal and the synchronous clock in the output data of the first buffer , and then the data output by the first buffer is controlled by the readout signal.

The present invention also provides a high-speed data packet filtering method, comprising the following steps:

In step (a), the input data is divided into two paths, one path is sent into the first buffer cache, and the other path is compared with the filter data in the preset dual-port RAM after being delayed by the delay device;

Step (b), the result signal generated by the comparison is sent to the second buffer buffer under the control of the combination of the end of the packet and the synchronous clock, and the reading of the result signal is controlled by the combination of the packet header signal and the synchronous clock in the output data of the first buffer output, and then the data output by the first buffer is controlled by the read signal.

The beneficial effects of the present invention are:

(1) Utilize FIFO to cache the compared one-bit information, and form a feedback control circuit with signals such as the header and tail of the current data packet, so as to realize the complete enabling of the current data packet;

(2) The present invention only uses a one-bit wide FIFO, which simplifies circuit design and reduces design cost.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is the control block diagram of a kind of high-speed packet filtering circuit of the present invention;

FIG. 2 is a composition diagram of the input signal of the high-speed data packet filtering circuit of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The interpretation of the English letters in Figure 1 is specifically: clock: data clock; frm-st: data packet start pulse; frm-end: data packet end pulse; frm-en: data packet valid signal; data-in: to be filtered data; cpu-en: the filter enable signal sent by the controller; cpu-addr, cpu-data, cpu-clk: the control address written in the memory, the filtered data, and the written clock; data-out: the filtered data; filt-data: current filter data.

As shown in Figure 1, a kind of high-speed data packet filtering circuit of the present invention comprises: the first register (FIFO11), the second register (FIFO1), preset dual-port RAM (DPRAM), delayer and comparator, The input data (data-in) includes: packet header (frm-st), packet tail (frm-end), data enable (frm-en) and 8-bit wide data.

The data packet filtering process is controlled by the corresponding combination of the packet header (frm-st), packet tail (frm-end), data enable (frm-en) and other signals under the synchronization of the data clock (clock) , the specific process is as follows: the input data (data-in) is divided into two paths, one path is sent to the first buffer (FIFO11) cache, and the other path is delayed by the delayer and filtered with the preset dual-port RAM (DPRAM). The comparator is compared, and the result signal generated by the comparison is sent to the second buffer (FIFO1) buffer under the control of the combination of the end of the packet and the synchronous clock, and the packet header signal in the output data of the first buffer (FIFO11) is combined with the synchronous clock The readout of the result signal is controlled, and the readout signal is used to control the output data of the first buffer (FIFO11) to complete the selection of the filtered data packet. The aforementioned synchronous clock is a synchronous signal of a data clock (clock).

As shown in FIG. 2, the input data (data-in) includes: packet header (frm-st), packet tail (frm-end), data enable (frm-en) and 8-bit wide data.

The present invention also provides a high-speed data packet filtering method, comprising the following steps:

In step (a), the input data is divided into two paths, one path is sent into the first buffer cache, and the other path is compared with the filter data in the preset dual-port RAM after being delayed by the delay device;

Step (b), the result signal generated by the comparison is sent to the second buffer buffer under the control of the combination of the end of the packet and the synchronous clock, and the reading of the result signal is controlled by the combination of the packet header signal and the synchronous clock in the output data of the first buffer output, and the output data of the first buffer is controlled by the read signal.

The high-speed data packet filtering circuit and method of the present invention use FIFO to cache the compared one-bit information, and form a feedback control circuit with signals such as the header and tail of the current data packet, so as to realize the complete enabling of the current data packet; The comparison result information needs to be buffered, which greatly reduces the requirement for FIFO capacity, and only uses a FIFO with a width of one bit, which simplifies the circuit design and reduces the design cost.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims (2)

1. A high-speed data packet filtering circuit is characterized in that, comprising: a first buffer, a second buffer, a preset dual-port RAM, a delayer and a comparator; The input data is divided into two paths, one path is sent to the first buffer buffer, and the other path is compared with the filtering data in the preset dual-port RAM after being delayed by the delayer, and the comparison generates The resulting signal is sent to the second buffer cache under the control of the combination of the end of the packet and the synchronous clock, and the combination of the packet header signal and the synchronous clock in the output data of the first buffer controls the reading of the resulting signal, and then The data output by the first buffer is controlled by a clock signal. 2. A high-speed data packet filtering method is characterized in that, comprising the following steps: In step (a), the input data is divided into two paths, one path is sent into the first buffer cache, and the other path is compared with the filter data in the preset dual-port RAM after being delayed by the delay device; Step (b), the result signal generated by the comparison is sent to the second buffer buffer under the control of the combination of the end of the packet and the synchronous clock, and the reading of the result signal is controlled by the combination of the packet header signal and the synchronous clock in the output data of the first buffer output, and the clock signal controls the output data of the first buffer.