CN103208300B - A kind of reading sense amplifier comparison circuit - Google Patents
A kind of reading sense amplifier comparison circuit Download PDFInfo
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- CN103208300B CN103208300B CN201210007613.9A CN201210007613A CN103208300B CN 103208300 B CN103208300 B CN 103208300B CN 201210007613 A CN201210007613 A CN 201210007613A CN 103208300 B CN103208300 B CN 103208300B
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Abstract
The invention discloses a kind of reading sense amplifier comparison circuit, including: memory cell circuits, clamp circuit, first, second clamp circuit, first, second electric current conversion potential circuit; First electric current source generating circuit, outfan connects described first clamp circuit and memory cell circuits; Second electric current source generating circuit, outfan connects described second clamp circuit and reference cell scheme; Described first electric current conversion potential circuit be connected to and the first clamp circuit between, described second electric current conversion potential circuit be connected to and the second clamp circuit between; One input of described comparator connects the junction point between described first electric current conversion potential circuit and described first clamp circuit, and another input connects the junction point of described second electric current conversion potential circuit and described second clamp circuit. The present invention can be applied in low supply voltage situation.
Description
Technical field
The present invention relates to circuit field, particularly relate to a kind of reading sense amplifier comparison circuit.
Background technology
In memorizer memory, data with 1 and the storage of 0 two kind of form, correspondence erasing unit Erasecell and the basic memory cell of programming unit Programcell both respectively. When reading memory data, in order to judge that certain memory cell is Erasecell or Programcell, it is necessary to memory cell and a reference unit are compared, this is accomplished by using sense amplifier senseamplifier comparison circuit.
Traditional senseamplifier structure is as it is shown in figure 1, include: left and right two parts circuit and a comparator; This comparator includes two inputs, an outfan.
In left-half circuit, floating gate type metal-oxide-semiconductor memory part Mcell represents a memory cell chosen by row decoding circuit and array decoding circuit, its source ground, control gate connects row decoding circuit, read voltage WL is added in the control gate of this memory cell Mcell by row decoding circuit, produces electric current Icell; The drain electrode of this memory cell Mcell is connected to the source electrode of N-type metal-oxide-semiconductor MN1 and the grid of N-type metal-oxide-semiconductor MN3 by array decoding circuit; The drain voltage of this memory cell Mcell is BL.
The voltage of the junction point of described array decoding circuit and N-type metal-oxide-semiconductor MN1, MN3 is sensebl; This junction point is additionally attached to one end of the drain terminal electric capacity CBL of described memory cell, the other end ground connection of this drain terminal electric capacity CBL.
Described N-type metal-oxide-semiconductor MN1 is a clamper tube, its objective is by voltage sensebl clamper between 0.8V��1.2V, to avoid drainstress (drain stress) effect of memory cell. The drain electrode of clamper tube MN1 is connected with the drain and gate of the P type metal-oxide-semiconductor MP1 as load pipe, and grid is connected with the drain electrode of described N-type metal-oxide-semiconductor MN3.
Described N-type metal-oxide-semiconductor MN3 is a feedback pipe, its source ground, and drain electrode is also connected with the drain electrode of P type metal-oxide-semiconductor MP3, for producing the bias voltage Vfb needed for described clamper tube MN1.
The grid of described P type metal-oxide-semiconductor MP3 connects bias voltage Vbias, and source electrode connects voltage source VDD, for providing bias voltage for described feedback pipe MN3.
The source electrode of described load pipe MP1 connects voltage source VDD; Described electric current Icell passes through described array decoding circuit and clamper tube MN1, is finally applied on the load pipe MP1 of a diode type of attachment, thus producing voltage sain on the grid and drain electrode of this load pipe MP1, as an input of described comparator; Significantly different memory cell produces different electric current Icell, thus producing different comparison voltage sain.
In right half part circuit, floating gate type metal-oxide-semiconductor memory part Mref represents reference unit, and for providing a benchmark being available for comparing, row reference voltage Rowref is applied in the control gate of this reference unit Mref, produces a reference current Iref. The source ground of this reference unit Mref, drain electrode is connected to the source electrode of N-type metal-oxide-semiconductor Mcol, and drain voltage is RBL.
Described N-type metal-oxide-semiconductor Mcol is column decoding pipe, and row reference voltage Colref is applied on the grid of this column decoding pipe Mcol; The drain electrode of this column decoding pipe Mcol is connected to the source electrode of N-type metal-oxide-semiconductor MN2 and the grid of N-type metal-oxide-semiconductor MN4, and the voltage of this junction point is rsensebl.
Described N-type metal-oxide-semiconductor MN2 is a clamper tube, its objective is by voltage rsensebl clamper between 0.8V��1.2V, to avoid drainstress (drain stress) effect. The drain electrode of clamper tube MN2 is connected with the drain and gate of the P type metal-oxide-semiconductor MP2 as load pipe, and grid is connected with the drain electrode of described N-type metal-oxide-semiconductor MN4.
Described N-type metal-oxide-semiconductor MN4 is a feedback pipe, its source ground, and drain electrode is also connected with the drain electrode of P type metal-oxide-semiconductor MP4, for producing the bias voltage Vrfb needed for described clamper tube MN2.
The grid of described P type metal-oxide-semiconductor MP4 connects bias voltage Vrefbias, and source electrode connects voltage source VDD, for providing bias voltage for described feedback pipe MN4.
The source electrode of described load pipe MP2 connects voltage source VDD; Described electric current Iref passes through described column decoding pipe Mcol, and clamper tube MN2, finally it is applied on the load pipe MP2 of a diode type of attachment, thus producing voltage sainref on the grid and drain electrode of this load pipe MP1, as another input of described comparator.
Finally, described comparator compares voltage sain and voltage sainref, produce or 0 or 1 output signal SAout, thus completing the digital independent to memory cell.
In traditional structure above, load pipe MP1 and MP2 is used for producing voltage as load, and its source and drain can consume bigger voltage margin, to ensure that comparison circuit possesses enough accuracy and speeds, which limits its application in low supply voltage situation. Along with the progress of technology, the supply voltage used gradually reduces, and is reduced to 1.8V or even below 1.5V at present, and in this case, the senseamplifier comparison circuit of above-mentioned traditional structure is just no longer applicable.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of reading sense amplifier comparison circuit can being applied in low supply voltage situation.
In order to solve the problems referred to above, the invention provides a kind of reading sense amplifier comparison circuit, including: comparator; Memory cell circuits, clamp circuit, first, second clamp circuit, first, second electric current conversion potential circuit;
First electric current source generating circuit, outfan connects described first clamp circuit and memory cell circuits;
Second electric current source generating circuit, outfan connects described second clamp circuit and reference cell scheme;
Described first electric current conversion potential circuit be connected to and the first clamp circuit between, described second electric current conversion potential circuit be connected to and the second clamp circuit between;
One input of described comparator connects the junction point between described first electric current conversion potential circuit and described first clamp circuit, and another input connects the junction point of described second electric current conversion potential circuit and described second clamp circuit.
Further, described first clamp circuit includes:
First clamper tube, for for described first clamper tube provide bias voltage the first biasing circuit;
Described first clamper tube is a P type metal-oxide-semiconductor, and the grid of this P type metal-oxide-semiconductor connects described first biasing circuit, and source electrode connects the outfan of described first electric current source generating circuit, and drain electrode connects described first electric current conversion potential circuit.
Further, described first biasing circuit includes:
One P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, the common leak source of this P type metal-oxide-semiconductor and N-type metal-oxide-semiconductor connects the grid of described first clamper tube;
The source electrode of described P type metal-oxide-semiconductor connects high level, and grid connects the first bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connects the source electrode of described first clamper tube.
Further, described first electric current conversion potential circuit is the first load being connected between described first clamper tube drain electrode and ground.
Further, described first load includes the N-type metal-oxide-semiconductor of a diode type of attachment; The source ground of the N-type metal-oxide-semiconductor in this first load, drain and gate is connected with the drain electrode of described first clamper tube.
Further, described second clamp circuit includes:
Second clamper tube, for for described second clamper tube provide bias voltage the second biasing circuit;
Described second clamper tube is a P type metal-oxide-semiconductor, and the grid of this P type metal-oxide-semiconductor connects described second biasing circuit, and source electrode connects the outfan of described second electric current source generating circuit, and drain electrode connects described second electric current conversion potential circuit.
Further, described second biasing circuit includes:
One P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, the common leak source of this P type metal-oxide-semiconductor and N-type metal-oxide-semiconductor connects the grid of described second clamper tube;
The source electrode of described P type metal-oxide-semiconductor connects high level, and grid connects the second bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connects the source electrode of described second clamper tube.
Further, described second electric current conversion potential circuit is the second load being connected between described second clamper tube drain electrode and ground.
Further, described second load includes the N-type metal-oxide-semiconductor of a diode type of attachment; The source ground of the N-type metal-oxide-semiconductor in this second load, drain and gate is connected with the drain electrode of described second clamper tube.
Further, described first clamp circuit is used for the voltage clamp of the outfan of described first electric current source generating circuit between 0.8V��1.2V; Described second clamp circuit is used for the voltage clamp of the outfan of described second electric current source generating circuit between 0.8V��1.2V.
Further, described memory cell circuits includes:
Row decoding circuit, array decoding circuit, the electric capacity that is connected between array decoding circuit and ground;
Memory cell, is a floating gate type metal-oxide-semiconductor memory part, and control gate connects described row decoding circuit, source ground, drains and connects described first clamp circuit, the first electric current source generating circuit and described electric capacity by described array decoding circuit;
Described reference cell scheme includes:
Reference unit, is a floating gate type metal-oxide-semiconductor memory part, source ground, and control gate connects row reference voltage;
Column decoding pipe, is a N-type metal-oxide-semiconductor, and source electrode is connected with the drain electrode of described reference unit, and grid connects row reference voltage, and drain electrode connects described second clamp circuit and the second electric current source generating circuit.
Further, described first, second electric current source generating circuit respectively includes:
One P type metal-oxide-semiconductor, grid connects the 3rd bias voltage, and source electrode connects voltage source, and drain electrode is as outfan.
Script is stacked on the present invention load pipe above memory element and clamper tube is folded, thus eliminating load pipe two ends attrition voltage nargin adverse effect in traditional structure, it is achieved that application at low supply voltages.
Accompanying drawing explanation
Fig. 1 is traditional structural representation reading sense amplifier comparison circuit;
Fig. 2 is the structural representation reading sense amplifier comparison circuit of embodiment one;
Fig. 3 be embodiment one example in read sense amplifier comparison circuit structural representation.
Detailed description of the invention
Below in conjunction with drawings and Examples, technical scheme is described in detail.
If it should be noted that do not conflict, the embodiment of the present invention and each feature in embodiment can be combined with each other, all within protection scope of the present invention.
Embodiment one, a kind of reading sense amplifier comparison circuit, as in figure 2 it is shown, include: comparator, memory cell circuits, reference cell scheme, first, second clamp circuit;
First electric current source generating circuit, outfan connects described first clamp circuit and memory cell circuits;
Second electric current source generating circuit, outfan connects described second clamp circuit and reference cell scheme;
First electric current conversion potential circuit, be connected to and the first clamp circuit between;
Second electric current conversion potential circuit, be connected to and the second clamp circuit between;
One input of described comparator connects the junction point between described first electric current conversion potential circuit and described first clamp circuit, and another input connects the junction point of described second electric current conversion potential circuit and described second clamp circuit.
In the present embodiment, described first clamp circuit can be, but not limited to for described first current source is produced the voltage clamp of circuit output end between 0.8V��1.2V; Described second clamp circuit can be, but not limited to for described second current source is produced the voltage clamp of circuit output end between 0.8V��1.2V.
In the present embodiment, described memory cell circuits can be, but not limited to include:
Row decoding circuit, array decoding circuit, the electric capacity that is connected between array decoding circuit and ground;
Memory cell, is a floating gate type metal-oxide-semiconductor memory part, and control gate connects described row decoding circuit, source ground, drains and connects described first clamp circuit, the first electric current source generating circuit and described electric capacity by described array decoding circuit.
In the present embodiment, described memory cell, row decoding circuit, array decoding circuit and electric capacity choose and annexation is referred to existing reading sense amplifier comparison circuit; If the memory cell circuits read in sense amplifier comparison circuit has other form, it is applied equally to the present embodiment.
In the present embodiment, described reference cell scheme can be, but not limited to include:
Reference unit, is a floating gate type metal-oxide-semiconductor memory part, source ground, and control gate connects row reference voltage;
Column decoding pipe, is a N-type metal-oxide-semiconductor, and source electrode is connected with the drain electrode of described reference unit, and grid connects row reference voltage, and drain electrode connects described second clamp circuit and the second electric current source generating circuit.
In the present embodiment, the choosing of described reference unit, reference voltage value be referred to existing reading sense amplifier comparison circuit; If the reference cell scheme read in sense amplifier comparison circuit has other form, it is applied equally to the present embodiment.
In the present embodiment, described first clamp circuit can be, but not limited to include:
First clamper tube, for for described first clamper tube provide bias voltage the first biasing circuit.
In the present embodiment, described first clamper tube can be, but not limited to be a P type metal-oxide-semiconductor, the grid of this P type metal-oxide-semiconductor connects described first biasing circuit, and source electrode connects the outfan of described first electric current source generating circuit, and drain electrode connects described first electric current conversion potential circuit.
In the present embodiment, described second clamp circuit can be, but not limited to include:
Second clamper tube, for for described second clamper tube provide bias voltage the second biasing circuit.
In the present embodiment, described second clamper tube can be, but not limited to be a P type metal-oxide-semiconductor, the grid of this P type metal-oxide-semiconductor connects described second biasing circuit, and source electrode connects the outfan of described second electric current source generating circuit, and drain electrode connects described second electric current conversion potential circuit.
In the present embodiment, described first/second clamp circuit can also adopt other clamp members to realize, such as clamp diode etc., or adopts other to have the circuit realiration of clamper function.
In the present embodiment, described first electric current conversion potential circuit can be, but not limited to as being connected to the first load between described first clamper tube drain electrode and ground; Described second electric current conversion potential circuit can be, but not limited to as being connected to the second load between described second clamper tube drain electrode and ground.
During practical application, it is also possible to be other element that can convert electrical current into voltage or circuit.
In the present embodiment, described first load can be, but not limited to include the N-type metal-oxide-semiconductor of a diode type of attachment, the source ground of the N-type metal-oxide-semiconductor in this first load, and drain and gate is connected with the drain electrode of described first clamper tube.
In the present embodiment, described second load can be, but not limited to include the N-type metal-oxide-semiconductor of a diode type of attachment, the source ground of the N-type metal-oxide-semiconductor in this second load, and drain and gate is connected with the drain electrode of described second clamper tube.
During practical application, described first, second load can also be other element that can use as load or the circuit such as resistance.
In the present embodiment, described first biasing circuit specifically may include that
One P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, the common leak source of this P type metal-oxide-semiconductor and N-type metal-oxide-semiconductor connects the grid of described first clamper tube;
The source electrode of described P type metal-oxide-semiconductor connects high level, and grid connects the first bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connects the source electrode of described first clamper tube.
In the present embodiment, described second biasing circuit specifically may include that
One P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, the common leak source of this P type metal-oxide-semiconductor and N-type metal-oxide-semiconductor connects the grid of described second clamper tube;
The source electrode of described P type metal-oxide-semiconductor connects high level, and grid connects the second bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connects the source electrode of described second clamper tube.
Wherein, first, second bias voltage in first, second biasing circuit can be identical or different.
During practical application, first, second biasing circuit can also adopt other embodiment, such as adopts the load being connected between voltage source and ground to provide described bias voltage for described first, second clamper tube.
In the present embodiment, the realization of described clamp circuit, electric current conversion potential circuit is referred to existing reading sense amplifier comparison circuit; If reading sense amplifier comparison circuit have other way of realization, it is applied equally to the present embodiment.
In the present embodiment, described first, second electric current source generating circuit respectively may include that
One P type metal-oxide-semiconductor, grid connects the 3rd bias voltage, and source electrode connects high level, and drain electrode is as outfan.
Wherein, the 3rd bias voltage in first, second electric current source generating circuit can be identical or different.
Other embodiment can also be adopted during practical application, such as directly adopt a current source etc., it is also possible on the basis of P type metal-oxide-semiconductor, increase load or other element.
In the present embodiment, described current comparison circuit can also include one for providing the voltage source of described high level; Described high level is not limited to be produced by voltage source, it is also possible to be other external high level.
One object lesson of the present embodiment is as it is shown on figure 3, include: left and right two parts circuit and a comparator C; This comparator C includes two inputs, an outfan.
In left-half circuit, memory cell circuits includes memory cell Mcell2, the drain terminal electric capacity CBL2 of described memory cell, row decoding circuit and array decoding circuit.
Floating gate type metal-oxide-semiconductor memory part Mcell2 represents a memory cell chosen by row decoding circuit and array decoding circuit, its source ground, control gate connects row decoding circuit, and read voltage WL is added in the control gate of this memory cell Mcell2 by row decoding circuit, produces electric current Icell; The drain electrode of this memory cell Mcell2 is connected to the grid of the drain electrode of P type metal-oxide-semiconductor MP9, the source electrode of P type metal-oxide-semiconductor MP5 and N-type metal-oxide-semiconductor MN7 by array decoding circuit; The drain voltage of this memory cell Mcell is BL.
Described P type metal-oxide-semiconductor MP9 source electrode connects voltage source VDD, bias voltage Vpbias inputs the grid of this P type metal-oxide-semiconductor MP9; This P type metal-oxide-semiconductor MP9, as the first electric current source generating circuit, provides current source for left-half circuit.
Described array decoding circuit and P type metal-oxide-semiconductor MP9, MP5, N-type metal-oxide-semiconductor MN7 the voltage of junction point be sensebl; This junction point is additionally attached to one end of the drain terminal electric capacity CBL2 of described memory cell, the other end ground connection of this drain terminal electric capacity CBL2.
Described P type metal-oxide-semiconductor MP5 is the first clamper tube, its objective is by voltage sensebl clamper between 0.8V��1.2V, to avoid drainstress (drain stress) effect of memory cell. The drain electrode of clamper tube MP5 is connected with the drain and gate of the N-type metal-oxide-semiconductor MN5 as load pipe, and grid is connected with the drain electrode of described N-type metal-oxide-semiconductor MN7.
In first biasing circuit, described N-type metal-oxide-semiconductor MN7 is a feedback pipe, and as the first load, its source ground, drain electrode is also connected with the drain electrode of P type metal-oxide-semiconductor MP7, for producing the bias voltage Vfb needed for described clamper tube MP5, and provides feedback control loop for it. The grid of described P type metal-oxide-semiconductor MP7 connects bias voltage Vbias, and source electrode connects voltage source VDD, for providing bias voltage for described feedback pipe MN7.
The source ground of described load pipe MN5, described electric current Icell passes through described array decoding circuit, and clamper tube MP5, finally it is applied to and connects on load pipe MN5 in circuit with diode, thus producing voltage sain on the grid and drain electrode of this load pipe MN5, as an input of described comparator; Significantly different memory cell produces different electric current Icell, thus producing different comparison voltage sain.
In right half part circuit, floating gate type metal-oxide-semiconductor memory part Mref2 represents reference unit, for providing a benchmark being available for comparing, row reference voltage Rowref to be applied in the control gate of this N-type metal-oxide-semiconductor Mref, produces a reference current Iref. The source ground of this reference unit Mref2, drain electrode is connected to the source electrode of N-type metal-oxide-semiconductor Mcol2, and drain voltage is RBL.
Described N-type metal-oxide-semiconductor Mcol2 is column decoding pipe, and voltage Colref is applied on the grid of this column decoding pipe Mcol2; The drain electrode of this column decoding pipe Mcol2 is connected to the grid of the drain electrode of P type metal-oxide-semiconductor MPl0, the source electrode of P type metal-oxide-semiconductor MP6 and N-type metal-oxide-semiconductor MN8; The voltage of this junction point is rsensebl.
The source electrode of described P type metal-oxide-semiconductor MP10 connects voltage source VDD, reference bias voltage Vrefpbias inputs the grid of this P type metal-oxide-semiconductor MP10, and this P type metal-oxide-semiconductor MP10, as the second electric current source generating circuit, provides current source for right half part circuit.
Described P type metal-oxide-semiconductor MP6 is the second clamper tube, its objective is by voltage rsensebl clamper between 0.8V��1.2V, to avoid drainstress effect. The drain electrode of clamper tube MP6 is connected with the drain and gate of the N-type metal-oxide-semiconductor MN6 as load pipe, and grid is connected with the drain electrode of described N-type metal-oxide-semiconductor MN8.
In second biasing circuit, described N-type metal-oxide-semiconductor MN8 is a feedback pipe, and as the second load, its source ground, drain electrode is also connected with the drain electrode of P type metal-oxide-semiconductor MP8, for producing the bias voltage Vrfb needed for described clamper tube MN5. The grid of described P type metal-oxide-semiconductor MP8 connects bias voltage Vrefbias, and source electrode connects voltage source VDD, for providing bias voltage for described feedback pipe MN8.
The source ground of described load pipe MN6, described electric current Iref passes through described column decoding pipe Mcol2, and clamper tube MP6, finally it is applied to and connects on load pipe MN6 in circuit with diode, thus producing voltage sainref on the grid and drain electrode of this load pipe MN6, as another input of described comparator.
Finally, described comparator compares voltage sain and voltage sainref, produce or 0 or 1 output signal SAout, thus completing the digital independent to memory cell.
It is not limited to during practical application adopt the physical circuit in above-mentioned example.
Certainly; the present invention also can have other various embodiments; when without departing substantially from present invention spirit and essence thereof; those of ordinary skill in the art are when can make various corresponding change and deformation according to the present invention, but these change accordingly and deform the scope of the claims that all should belong to the present invention.
Claims (11)
1. read a sense amplifier comparison circuit, including: comparator; Memory cell circuits, reference cell scheme, first, second clamp circuit, first, second electric current conversion potential circuit;
It is characterized in that, also include:
First electric current source generating circuit, outfan connects described first clamp circuit and memory cell circuits;
Second electric current source generating circuit, outfan connects described second clamp circuit and reference cell scheme;
Described first electric current conversion potential circuit be connected to and the first clamp circuit between, described second electric current conversion potential circuit be connected to and the second clamp circuit between;
One input of described comparator connects the junction point between described first electric current conversion potential circuit and described first clamp circuit, and another input connects the junction point between described second electric current conversion potential circuit and described second clamp circuit;
Wherein, described first clamp circuit is used for the voltage clamp of the outfan of described first electric current source generating circuit between 0.8V��1.2V; Described second clamp circuit is used for the voltage clamp of the outfan of described second electric current source generating circuit between 0.8V��1.2V.
2. reading sense amplifier comparison circuit as claimed in claim 1, it is characterised in that described first clamp circuit includes:
First clamper tube, for for described first clamper tube provide bias voltage the first biasing circuit;
Described first clamper tube is a P type metal-oxide-semiconductor, and the grid of this P type metal-oxide-semiconductor connects described first biasing circuit, and source electrode connects the outfan of described first electric current source generating circuit, and drain electrode connects described first electric current conversion potential circuit.
3. reading sense amplifier comparison circuit as claimed in claim 2, it is characterised in that described first biasing circuit includes:
The common leak source of one P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, described P type metal-oxide-semiconductor in described first biasing circuit and N-type metal-oxide-semiconductor connects the grid of described first clamper tube;
The source electrode of the described P type metal-oxide-semiconductor in described first biasing circuit connects high level, and grid connects the first bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connects the source electrode of described first clamper tube.
4. reading sense amplifier comparison circuit as claimed in claim 2, it is characterised in that:
Described first electric current conversion potential circuit is the first load being connected between described first clamper tube drain electrode and ground.
5. reading sense amplifier comparison circuit as claimed in claim 4, it is characterised in that:
Described first load includes the N-type metal-oxide-semiconductor of a diode type of attachment; The source ground of the N-type metal-oxide-semiconductor in this first load, drain and gate is connected with the drain electrode of described first clamper tube.
6. reading sense amplifier comparison circuit as claimed in claim 1, it is characterised in that described second clamp circuit includes:
Second clamper tube, for for described second clamper tube provide bias voltage the second biasing circuit;
Described second clamper tube is a P type metal-oxide-semiconductor, and the grid of this P type metal-oxide-semiconductor connects described second biasing circuit, and source electrode connects the outfan of described second electric current source generating circuit, and drain electrode connects described second electric current conversion potential circuit.
7. reading sense amplifier comparison circuit as claimed in claim 6, it is characterised in that described second biasing circuit includes:
The common leak source of one P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, described P type metal-oxide-semiconductor in described second biasing circuit and N-type metal-oxide-semiconductor connects the grid of described second clamper tube;
The source electrode of the described P type metal-oxide-semiconductor in described second biasing circuit connects high level, and grid connects the second bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connects the source electrode of described second clamper tube.
8. reading sense amplifier comparison circuit as claimed in claim 6, it is characterised in that:
Described second electric current conversion potential circuit is the second load being connected between described second clamper tube drain electrode and ground.
9. reading sense amplifier comparison circuit as claimed in claim 8, it is characterised in that:
Described second load includes the N-type metal-oxide-semiconductor of a diode type of attachment; The source ground of the N-type metal-oxide-semiconductor in this second load, drain and gate is connected with the drain electrode of described second clamper tube.
10. the reading sense amplifier comparison circuit as according to any one of claim 1 to 9, it is characterised in that described memory cell circuits includes:
Row decoding circuit, array decoding circuit, the electric capacity that is connected between array decoding circuit and ground;
Memory cell, is a floating gate type metal-oxide-semiconductor memory part, and control gate connects described row decoding circuit, source ground, drains and connects described first clamp circuit, the first electric current source generating circuit and described electric capacity by described array decoding circuit;
Described reference cell scheme includes:
Reference unit, is a floating gate type metal-oxide-semiconductor memory part, source ground, and control gate connects row reference voltage;
Column decoding pipe, is a N-type metal-oxide-semiconductor, and source electrode is connected with the drain electrode of described reference unit, and grid connects row reference voltage, and drain electrode connects described second clamp circuit and the second electric current source generating circuit.
11. the reading sense amplifier comparison circuit as according to any one of claim 1 to 9, it is characterised in that described first, second electric current source generating circuit respectively includes:
One P type metal-oxide-semiconductor, grid connects the 3rd bias voltage, and source electrode connects voltage source, and drain electrode is as outfan.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210007613.9A CN103208300B (en) | 2012-01-11 | 2012-01-11 | A kind of reading sense amplifier comparison circuit |
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| CN201210007613.9A CN103208300B (en) | 2012-01-11 | 2012-01-11 | A kind of reading sense amplifier comparison circuit |
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| CN103208300A CN103208300A (en) | 2013-07-17 |
| CN103208300B true CN103208300B (en) | 2016-06-08 |
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|---|---|---|---|---|
| CN111462802B (en) * | 2019-01-22 | 2022-05-13 | 上海汉容微电子有限公司 | Reading circuit of NOR flash memory |
| CN110415739B (en) * | 2019-07-17 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Charge transfer type sensitive amplifier and reference voltage generating circuit applied to same |
| CN115996044B (en) * | 2023-03-22 | 2023-06-02 | 江苏润石科技有限公司 | Fast comparator |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102117644A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | A memory readout circuit |
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| KR100618840B1 (en) * | 2004-06-29 | 2006-09-01 | 삼성전자주식회사 | Detection circuit of low power supply voltage flash memory device |
| US7239537B2 (en) * | 2005-01-12 | 2007-07-03 | International Business Machines Corporation | Method and apparatus for current sense amplifier calibration in MRAM devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102117644A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | A memory readout circuit |
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