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CN103107124A - Method of improving planarization of surface of shallow trench isolation silicon oxide film - Google Patents

Method of improving planarization of surface of shallow trench isolation silicon oxide film Download PDF

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Publication number
CN103107124A
CN103107124A CN2011103564197A CN201110356419A CN103107124A CN 103107124 A CN103107124 A CN 103107124A CN 2011103564197 A CN2011103564197 A CN 2011103564197A CN 201110356419 A CN201110356419 A CN 201110356419A CN 103107124 A CN103107124 A CN 103107124A
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China
Prior art keywords
silicon oxide
trench isolation
shallow trench
oxide film
etching
Prior art date
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Pending
Application number
CN2011103564197A
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Chinese (zh)
Inventor
刘俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Hua Hong NEC Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CN2011103564197A priority Critical patent/CN103107124A/en
Publication of CN103107124A publication Critical patent/CN103107124A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a method of improving planarization of surface of a shallow trench isolation silicon oxide film. The method of improving the planarization of surface of the shallow trench isolation silicon oxide film includes the following steps of with regard to silicon oxide filling a shallow trench, lapping the silicon oxide by means of chemical machinery of shallow trench isolation (STI) at first, and then etching the silicon oxide of an active area (AA) compact zone by means of mask, thereby improving the planarization of surface of the shallow trench isolation silicon oxide film. The method of improving the planarization of surface of the shallow trench isolation silicon oxide film can greatly lower requirements to photoetching registration precision, and for instance, a requirement of original 0.1 micrometer is relaxed up to 0.3 micrometer. Due to the fact that etching quantity is reduced, applying a wet etching technology with higher selectivity can be considered. In addition, the method of improving the planarization of surface of the shallow trench isolation silicon oxide film can increase flexibility of the technology, namely, the method of improving the planarization of surface of the shallow trench isolation silicon oxide film can adjust etching time according to different products so as to independently adjust the height of the silicon oxide of the shallow trench isolation in AA compact zone within a certain range (such as +/- 5000A).

Description

Improve the method for shallow-trench isolation silicon oxide film flattening surface
Technical field
The present invention relates to a kind of method of shallow-trench isolation silicon oxide film flattening surface, particularly relate to a kind of method of improving shallow-trench isolation silicon oxide film flattening surface.
Background technology
In semiconductor fabrication, shallow trench isolation is from (Shallow Trench Isolation, STI) to have an isolation effect good for technique, the advantages such as area occupied is little, typical STI technological process comprises: the cmp (CMP) of the inserting of the silica on silicon substrate (pad oxide) and silicon nitride deposition, STI silicon groove etching, silica (HDP Oxide), silica, the removal of silicon nitride and silica (pad oxide).
In the manufacture craft process of (STI), CMP technique is used to remove and the high-density plasma silica (HDP oxide) of filling out (over-filled) is crossed in leveling at shallow trench isolation.Depression (dishing) and erosion (erosion) effect due to CMP, the method of traditional shallow-trench isolation silicon oxide film flattening surface be first by reverse mask (anti-mask) dry etching AA (active area: the active area) silica of compact district, then adopt cmp (CMP) to reach planarization.
Yet traditional reverse mask technique (as shown in Figure 1) has certain requirement for the mask alignment precision, the special place that dotted line marks in Fig. 1, and left avertence or right avertence all can cause the deleterious of planarization.In addition, for reverse mask etching, if half SiO of etching only 2, help limited to the silicon oxide film flattening surface; Etch into Si 3N 4, the flexibility of technique just is restricted, and namely can not follow according to different products, does to adjust flexibly.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method of improving shallow-trench isolation silicon oxide film flattening surface, and the method can significantly reduce the requirement to this layer photoetching alignment precision, and increases technological flexibility.
For solving the problems of the technologies described above, the method of improving shallow-trench isolation silicon oxide film flattening surface of the present invention, comprise: for the silica that fills up shallow slot, the first cmp (CMP) by STI, then adopt the silica of mask (mask) etching AA compact district, thereby improve the planarization on shallow-trench isolation silicon oxide film surface.
Said method, its concrete steps comprise:
(1) complete filling up of silica in shallow slot by existing STI technique after, carry out STI CMP, then, carry out the photoetching of opening in the AA compact district;
(2) to the SiO of silicon nitride high selectivity 2Carry out etching, make the SiO of AA compact district 2The loose zone of film height and AA is consistent, or reaches desired height;
(3) remove photoresist.
In described step (2), the method for etching comprises: wet etching, dry etching; The time of etching can adjust accordingly according to the needs of product, namely according to different products, adopts different etch periods.
Beneficial effect of the present invention is as follows:
(1) can significantly reduce requirement to the lithography alignment precision, such as from original 0.1 μ m left and right, more than being loosened to 0.3 μ m;
(2) due to the minimizing of etch amount, can consider the wet-etching technology of taking selectivity higher;
(3) increase the flexibility of technique, namely can follow according to product differently, done the adjustment of corresponding etch period, so that within the specific limits (such as ± 500A) be adjusted in separately AA compact district shallow trench isolation from the oxide layer height of (STI);
(4) when be adjusted in separately AA compact district shallow trench isolation from the oxide layer height time, do not affect other regional shallow trench isolations from the oxide layer height.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is traditional reverse mask artwork;
Fig. 2 is artwork of the present invention;
Fig. 3 is the photoetching figure that the carrying out in the present invention opened in the AA compact district;
Fig. 4 be in the present invention to STI SiO 2Carry out the schematic diagram of etching.
Embodiment
The method of improving shallow-trench isolation silicon oxide film flattening surface of the present invention, its artwork as shown in Figure 2, step comprises:
(1) according to existing STI technological process, carry out silica on silicon substrate and silicon nitride deposition, STI silicon groove etching, HDP silica insert (filling up) after, then after STI CMP, carry out the photoetching (as shown in Figure 3) of opening in the AA compact district, in this photoetching process, photoresist thickness is about 1 μ m, uses the I-line mask aligner to expose;
Wherein, the AA compact district can for: in any 10 μ m of chip internal * 10 μ m scopes, the AA area occupied surpass the gross area 40% or more than;
(2) use the SiO to silicon nitride high selectivity (greater than 10: 1) of set time 2Wet etching or dry etching, as shown in Figure 4, make AA compact district shallow trench isolation from SiO 2The loose zone of film height and AA is consistent, or reach desired height (such as in ± 500A scope all can);
In this step, before and after the etching, can to AA compact district shallow trench isolation from oxide layer (SiO 2Film) thickness is measured, so that the monitoring etch amount;
Due to the minimizing of etch amount, this step can be preferred, the wet-etching technology that selectivity is higher, simultaneously, can adopt different etch periods according to different products so that within the specific limits (such as ± 500A) be adjusted in separately AA compact district shallow trench isolation from the oxide layer height;
(3) use conventional dry method to add wet method, remove photoresist.
The present invention first passes through cmp, then adopt the silica of mask etching AA compact district, can reach the effect of improving shallow-trench isolation silicon oxide film flattening surface, and can significantly reduce requirement to the lithography alignment precision, as dotted portion indication part in Fig. 2, such as from about 0.1 original μ m, more than being loosened to 0.3 μ m.
In addition, the present invention can also increase the flexibility of etching technics, namely can follow according to product differently, does the adjustment of corresponding etch period so that within the specific limits (such as ± 500A) be adjusted in separately AA compact district shallow trench isolation from the oxide layer height.

Claims (6)

1. a method of improving shallow-trench isolation silicon oxide film flattening surface, is characterized in that, comprising: for the silica that fills up shallow slot, first by the cmp of STI, then adopt the silica of mask etching AA compact district.
2. the method for claim 1 is characterized in that: described method, and step comprises:
(1) complete filling up of silica in shallow slot by existing STI technique after, carry out STI CMP, then, carry out the photoetching of opening in the AA compact district;
(2) to the SiO of silicon nitride high selectivity 2Carry out etching, make the SiO of AA compact district 2The loose zone of film height and AA is consistent, or reaches desired height;
(3) remove photoresist.
3. method as claimed in claim 2, is characterized in that: in described step (2), to the silicon nitride high selectivity be: greater than 10: 1.
4. method as claimed in claim 2, it is characterized in that: in described step (2), the method for etching comprises: wet etching, dry etching.
5. method as claimed in claim 4, it is characterized in that: in described step (2), the method for etching is wet etching.
6. method as claimed in claim 2 is characterized in that: in described step (2), desired height is in ± 500A scope.
CN2011103564197A 2011-11-11 2011-11-11 Method of improving planarization of surface of shallow trench isolation silicon oxide film Pending CN103107124A (en)

Priority Applications (1)

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CN2011103564197A CN103107124A (en) 2011-11-11 2011-11-11 Method of improving planarization of surface of shallow trench isolation silicon oxide film

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CN2011103564197A CN103107124A (en) 2011-11-11 2011-11-11 Method of improving planarization of surface of shallow trench isolation silicon oxide film

Publications (1)

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CN103107124A true CN103107124A (en) 2013-05-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117317067A (en) * 2023-11-28 2023-12-29 晶科能源(海宁)有限公司 Solar cell manufacturing method and solar cell

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050148184A1 (en) * 2004-01-05 2005-07-07 Chia-Rung Hsu Chemical mechanical polishing process for forming shallow trench isolation structure
CN101207064A (en) * 2006-12-22 2008-06-25 中芯国际集成电路制造(上海)有限公司 Method for forming device isolation region

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050148184A1 (en) * 2004-01-05 2005-07-07 Chia-Rung Hsu Chemical mechanical polishing process for forming shallow trench isolation structure
CN101207064A (en) * 2006-12-22 2008-06-25 中芯国际集成电路制造(上海)有限公司 Method for forming device isolation region

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117317067A (en) * 2023-11-28 2023-12-29 晶科能源(海宁)有限公司 Solar cell manufacturing method and solar cell

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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

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Effective date: 20140107

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Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399

Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge

Applicant before: Shanghai Huahong NEC Electronics Co., Ltd.

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Application publication date: 20130515