CN102929811B - Device and method for updating dynamic access memory - Google Patents

Abstract

The invention relates to a method for updating a dynamic access memory, wherein a memory array is planned to be a plurality of storage units, and each storage unit has a counting value. The method includes detecting unused memory cells in the memory cells whose data is no longer used and remaining used memory cells whose data is still used. Thus, only the part of the memory cells which are still used are updated.

Description

Device and method for updating dynamic access memory

technical field

The invention relates to a refresh technology for dynamic memory access, which can increase the efficiency of refresh operations.

Background technique

Dynamic random access memory (DRAM) has been widely used in various digital processing circuit systems, the most common of which is computer systems, to store registered data required in the processing process. Both DRAM and Static Random Access Memory (SRAM) are volatile memories. When the power is turned off, the data stored in the memory will disappear. However, the basic structure of DRAM memory is composed of a MOS transistor and a storage capacitor. Therefore, It occupies less area on the chip and is therefore more commonly used.

FIG. 1 is a schematic diagram of the structure of a traditional DRAM memory. Referring to FIG. 1 , a DRAM memory 50 includes a MOS transistor 52 and a storage capacitor 54 . The source of transistor 52 is connected to the bit line. The drain of the MOS transistor 52 is connected to the storage capacitor 54, and the other end of the storage capacitor 54 is grounded. The gate of transistor 52 is connected to the word line. A character line is connected to multiple memories 50, and a bit line is also connected to multiple memories 50, so these memories 50 constitute a two-dimensional memory array, and each memory is accessed by a crossed bit line and a word line.

The transistor 52 is described by taking an NMOS transistor as an example. For example, when the data of “1” is to be written into the storage capacitor 54 , a voltage signal of 5V is applied to the corresponding connected bit line. At this time, a turn-on voltage, such as 5V, is applied to the corresponding connected word line to turn on the transistor 52 . At this time, the voltage on the bit line will charge the storage capacitor 54 to 5V. Then the transistor 52 can be turned off by the word line being in a low voltage state. Then turn off the voltage on the bit line, or continue writing to other memories 50 . On the contrary, if the data of “0” is to be written, a voltage signal of 0V will be applied to the bit line, so the voltage of the storage capacitor 54 is 0V. In this way, the data of “1” or “0” is stored according to the voltage level of the storage capacitor 54 .

The reading mechanism is described below. Figure 2 depicts a conventional read circuit for a memory. Referring to FIG. 2 , if the data on the memory 50 is to be read, the bit line connected to the memory 50 selected to be read is switched to a comparator 56 . The comparator 56 has a reference voltage VRef between 0V and 5V. When the word line turns on the memory 50, the voltage on the bit line is the voltage V of the storage capacitor 54, which is 0V or 5V. By comparing with the reference voltage VRef, it can be known that the voltage V of the storage capacitor 54 is 0V or 5V.

With regard to the structure of the DRAM memory 50, if the storage capacitor 54 is at a high voltage value for storing “1” data, its charge will be lost due to leakage current, resulting in a voltage drop. If the voltage value of the storage capacitor 54 is not updated for a long time, erroneous data will be generated. In order to update the voltage value of the storage capacitor 54 , the voltage value of the storage capacitor 54 can be updated generally as long as it is read out. The read operation can be real data acquisition or dummy read. As for rewriting the stored value, it will naturally update the data.

FIG. 3A is a schematic diagram of the mechanism of the traditional distribution update mode. Referring to FIG. 3A , generally n updates are required within a time interval. The traditional refresh operation can be performed on the memory every fixed time evenly distributed in a time interval, which is also called distributed refresh mode. Another update operation is, for example, a burst refresh mode. One pulse represents an update operation. FIG. 3B is a schematic diagram of the mechanism of the traditional cluster update mode. Referring to FIG. 3B , the plex update mode is to perform multiple consecutive update operations once in each time interval.

Contents of the invention

The present invention provides a method that can reduce the load of the update operation of the DRAM, so as to improve the use efficiency of the DRAM.

The invention provides an update method for dynamically accessing memory, wherein a memory array is planned with a plurality of storage units, and each storage unit has a count value. The method includes detecting an "unused part" of the storage units where data is no longer used, and performing an update operation only on a "still used part" of the storage units where data is still used.

The present invention provides an update device for dynamically accessing memory, wherein a memory array is planned to have multiple storage units, and each storage unit has a count value, and the update device includes an access control unit; a memory master; an update control unit; and a monitoring unit. The memory main controller accesses a frame data through the access control unit, and the frame data is stored in a part of the storage pages. The update control unit performs an update operation on the storage units according to a specified address. The monitoring unit detects an unused portion of the storage units that is no longer used, and notifies the update control unit to only perform the update operation on a still-used portion of the storage units.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of the structure of a traditional DRAM memory.

Figure 2 depicts a conventional read circuit for a memory.

FIG. 3A is a schematic diagram of the mechanism of the traditional distribution update mode.

FIG. 3B is a schematic diagram of the mechanism of the traditional cluster update mode.

FIG. 4 is a schematic diagram of a circuit structure of an updating device for dynamically accessing memory according to an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating the relationship between frame and additional information according to an embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating the correspondence between frame data and storage units according to an embodiment of the present invention.

FIG. 7 is a characteristic diagram of a down counter according to an embodiment of the present invention.

FIG. 8 is a characteristic diagram of a down counter according to an embodiment of the present invention.

FIG. 9 is a schematic flowchart of a method for updating a dynamic access memory according to an embodiment of the present invention.

Explanation of main component symbols

50: memory

52: Transistor

54: storage capacitor

60: Storage system

62: Memory main control unit

64: Access controller

66: memory array

68: DRAM control unit

70:Update control unit

72: Surveillance unit

74: Read/write command

76:Additional information

S200-S218: Steps

Detailed ways

Considering the traditional update method, no matter what the update mode is, the traditional method will update the memory on the entire DRAM, and some of the memory will still be updated and occupied by storing data that is outdated and will no longer be used. DRAM effectively takes normal read operation time, resulting in an unnecessary burden for update operations.

The update method of the DRAM memory proposed by the present invention can reduce the burden of the update operation of the DRAM, so as to improve the use efficiency of the DRAM. Some examples are given below to illustrate the present invention, but the present invention is not limited to the examples given.

FIG. 4 is a schematic diagram of a circuit structure of an updating device for dynamically accessing memory according to an embodiment of the present invention. Referring to FIG. 4 , a storage system 60 includes a memory master unit (memorymaster) 62 , a DRAM control unit 68 , an update control unit 70 , a monitoring unit 72 , and a memory array 66 . Also, the DRAM control unit 68 , the update control unit 70 and the monitoring unit 72 are in the access controller 64 . The memory array 66 is planned with a plurality of storage units, which will be as described in FIG. 6 later. The DRAM control unit 68 is used to control access to the memory array 66 . The memory main control unit 62 sends a read/write command 74 to the DRAM control unit 68 to access the frame data in the memory array 66 according to the external frame data to be written or read. This read/write command 74 will also be monitored by the monitoring unit 72 to determine the validity of the frame data, to determine which data of the storage units in the memory array 66 are no longer used, so the update control unit 70 is notified only Just perform an update operation on the storage unit that is still in use.

Here, to determine whether the storage unit is still in use or no longer in use, in addition to the read/write status of the frame data, the memory master can also provide additional information for each frame data ( side information) 76 to assist in judging the usage status of the detected storage unit.

The mechanism for using additional information is further described below. FIG. 5 is a schematic diagram illustrating the relationship between frame and additional information according to an embodiment of the present invention. Referring to FIG. 5 , the data of a frame is, for example, 480x640 image data, and the memory array 66 may store multiple frames at the same time, and the order of the frames is represented by F0, F1, F2 . . .

The additional information for frame F0 includes, for example, the start time denoted S and the end time denoted E. The start time S indicates that there will be valid data of the frame F0 after this time point. The end time E indicates that the data of the frame F0 is no longer used after this point in time. In the same mechanism, each frame is known by external operations, and the memory main control unit 62 provides additional information 76 to the monitoring unit 72 . In addition, the read/write command 74 issued by the memory main control unit 62 can also know the address of the storage unit used by the frame.

The content of the additional information 76 is used to assist in judging the usage status of the detected storage unit. That is to say, the content of the additional information 76 may also have other content, and is not limited to the aforementioned embodiments.

FIG. 6 is a schematic diagram illustrating the correspondence between frame data and storage units according to an embodiment of the present invention. Referring to FIG. 6 , the memory array 66 is, for example, planned to have N storage units denoted by P-0 to P-N. Frames F0, F1, . . . will be written into some corresponding storage units. Although the drawing uses continuous memory units to store frame data, this is not the only way, and it can be stored according to commonly known writing methods.

Here, a counter is provided corresponding to each storage unit in the monitoring unit 72 or in the update control unit 70 , to reflect how long the storage unit has not been updated by counting down or counting up. FIG. 7 is a characteristic diagram of a down counter according to an embodiment of the present invention. Referring to FIG. 7 , the counter in this embodiment is described by taking a countdown counter as an example. The down counter corresponding to each storage unit has a maximum constant value nmax when it is initially or completed updating. From the maximum fixed value nmax, the countdown value will be subtracted by 1 every fixed interval over time, such as nmax-1, nmax-2..., and count down to 0 over time.

However, if the memory cell is updated, its count-down value returns to nmax. Therefore, the countdown value can reflect how long the storage unit has been updated since the last time. If it is longer, the storage capacitor of the memory may change the storage value due to leakage current, resulting in erroneous data.

Based on this, if the down count value of the storage unit is lower than a critical value and the data stored in the storage unit is still being used, the storage unit needs to be refreshed.

Another way of judging whether the data of the storage unit continues to be used is to analyze and judge directly according to the reading frequency of the data, which does not need to refer to the additional information 76 . The method is, for example, the following method.

FIG. 8 is a characteristic diagram of a down counter according to an embodiment of the present invention. Referring to FIG. 8, the count counter is taken as an example. If the data is read or updated, the count value will be reset to the maximum value. In one case, for example, when the count value decreases below a threshold value, an update operation is initiated to reset the count value to the maximum value. With this feature, the count value can be directly detected to determine the usage of the data.

If the data of the storage unit is frequently read by an externally connected device within a short period of time after being written, the data of the storage unit will be updated with each read, so the countdown value will remain greater than the critical value, and the critical value is Set a small value or can also be 0. If the data of the storage unit is rewritten, it is naturally that new frame data is written.

However, if the frame data is no longer used, the storage unit used by it will not be updated, so the count-down value will be less than the critical value or reach 0 after a period of time. This means that the data of this frame is likely to be no longer used, so the storage unit whose down count value is less than the critical value can be judged to be no longer used, so at least one storage unit used by this frame does not need to be deliberate Do the update operation.

However, if the down count value of the storage unit is less than the critical value or is read again after reaching 0, a warning message that the data may be wrong may be issued. In addition, if the storage unit is written, it represents new data, so there is no need to keep the old data. In this way, the use status of the storage unit can be determined according to the reading frequency of the data without the assistance of additional information.

FIG. 9 is a schematic flowchart of a method for updating a dynamic access memory according to an embodiment of the present invention. Referring to FIG. 9 , according to the above description, the method for updating the dynamic access memory can be simply represented by a flow chart, for example.

In step S200, frame data is written into at least one storage unit. In step S202, it checks whether the frame data has additional information, and if yes, proceeds to step S204, and if not, proceeds to step S208. In step S204, it uses the additional information of the frame data to detect unused storage units. Then in step S206, it only updates other storage units that are still in use. In step S208, it checks whether the countdown value corresponding to the storage unit is less than a threshold value. This threshold is a set value and can also be 0. In step S210, if the value is less than a threshold value, the corresponding storage unit is set to be unused. In step S212, it monitors whether the memory unit set to be unused continues to be read. In step S214, if it is still being read, a read possible error status is issued. In step S216, if it is no longer read, it waits for the next write. In step S218, if the determination in step S208 is not less than the critical value, the storage unit is accessed normally. Then return to step S202 to continue reading and writing of the detection frame.

The actual operation process is not necessarily limited to the way shown in Figure 9, but it is mainly based on the auxiliary information of the frame or only based on the actual reading frequency of the storage units to determine which storage units are no longer used, so it can be The update operation of these memory cells that are no longer used is saved.

Although the utility model has been disclosed as above with the embodiments, it is not intended to limit the utility model, and any ordinary worker in the technical field may make some changes and modifications without departing from the spirit and spirit of the utility model. scope.

Claims (11)

1. a update method for dynamic access internal memory, wherein a memory array is cooked up multiple storage unit, and each storage unit has a count value, and the method comprises:

Detect that in those storage unit data no longer one are not used part by what use, and the other parts of those storage unit are considered as one still uses part; And

Only still part is still used to carry out a renewal rewards theory by this use to data in those storage unit,

Wherein this detect in those storage unit this do not use part to comprise:

By an internal memory main control unit to receive and write a drawing frame data of a memory array, at least one of the end time point that this drawing frame data of access is provided and those storage unit of using; And

When this end time, point was detected, this at least one storage unit that this corresponding drawing frame data uses is set to this and does not use part.

2. the update method of dynamic access internal memory according to claim 1, wherein just carries out this renewal rewards theory when this of those storage unit still uses this count value of any one of part to exceed a critical value.

3. the update method of dynamic access internal memory according to claim 1, wherein this detect in those storage unit this do not use part to comprise:

Monitoring whether those lower counting number values of those storage unit are less than a critical value, being wherein namely set as that this does not use part when there are those storage unit be less than corresponding to this critical value in those lower counting number values.

4. the update method of dynamic access internal memory according to claim 3, wherein deserves to have in those lower counting number values those storage unit be less than corresponding to this critical value when still being read by continuation, sends a false alarm.

5. the update method of dynamic access internal memory according to claim 3, wherein deserves to have those storage unit be less than corresponding to this critical value in those lower counting number values and still can be performed this renewal rewards theory according to demand.

6. a update method for dynamic access internal memory, wherein a memory array is cooked up multiple storage unit, and each storage unit has a count value, and the method comprises:

Detect that in those storage unit data no longer one are not used part by what use, and the other parts of those storage unit are considered as one still uses part; And

Only still part is still used to carry out a renewal rewards theory by this use to data in those storage unit,

Wherein this detect in those storage unit this do not use part to comprise:

By an internal memory main control unit to receive and write a drawing frame data of a memory array, at least one of the additional information that this drawing frame data is provided and those storage unit of using; And

Determine whether this at least one storage unit that this drawing frame data uses will be set as that this does not use part according to this additional information.

7. a updating device for dynamic access internal memory, wherein a memory array is cooked up multiple storage unit, and each storage unit has a lower counting number value, and this updating device comprises:

One storage control unit;

One internal memory primary controller, accesses a drawing frame data by this storage control unit, and this drawing frame data is stored in a part for those storage unit;

One upgrades control module, according to an address of specifying in order to do a renewal rewards theory to those storage unit; And

One monitor unit, detect do not re-use in those storage unit one do not use part, and notify that only other still one is still used part to carry out this renewal rewards theory by what use to this renewal control module in those storage unit,

An additional information is provided to comprise an end time point of this drawing frame data and at least one of those storage unit of using when wherein this internal memory primary controller accesses this drawing frame data,

Wherein this monitor unit, receive this additional information of internal memory main control unit, when this end time, point was detected, this at least one storage unit that this corresponding drawing frame data uses is set to this and does not use part, to notify this renewal control module, part is not used to carry out this renewal rewards theory to this.

8. the updating device of dynamic access internal memory according to claim 7, wherein just carries out this renewal rewards theory when this of those storage unit still uses this lower counting number value of any one of part to be less than a critical value.

9. the updating device of dynamic access internal memory according to claim 7, wherein this monitor unit monitors whether those lower counting number values of those storage unit are less than a critical value, is wherein namely set as that this does not use part when having those storage unit be less than corresponding to this critical value in those lower counting number values.

10. the updating device of dynamic access internal memory according to claim 9, wherein deserves to have in those lower counting number values those storage unit be less than corresponding to this critical value when still being read by continuation, sends a false alarm.

The update method of 11. dynamic access internal memories according to claim 9, wherein deserves to have those storage unit be less than corresponding to this critical value in those lower counting number values and still can be performed this renewal rewards theory according to demand.