CN102929811A - Device and method for updating dynamic access memory - Google Patents

Abstract

The invention relates to a device and a method for updating a dynamic access memory, wherein a memory array is planned with a plurality of memory cells, and each memory cell has a counting value. The method includes detecting unused memory cells in the memory cells whose data is no longer used and remaining used memory cells whose data is still used. Thus, only the part of the memory cells which are still used are updated.

Description

Device and method for updating dynamic access memory

technical field

The invention relates to a refresh technology for dynamic memory access, which can increase the efficiency of refresh operations. the

Background technique

Dynamic random access memory (DRAM) has been widely used in various digital processing circuit systems, the most common of which is computer systems, to store registered data required in the processing process. Both DRAM and Static Random Access Memory (SRAM) are volatile memories. When the power is turned off, the data stored in the memory will disappear. However, the basic structure of DRAM memory is composed of a MOS transistor and a storage capacitor. Therefore, It occupies less area on the chip and is therefore more commonly used. the

FIG. 1 is a schematic diagram of the structure of a traditional DRAM memory. Referring to FIG. 1 , a DRAM memory 50 includes a MOS transistor 52 and a storage capacitor 54 . The source of transistor 52 is connected to the bit line. The drain of the MOS transistor 52 is connected to the storage capacitor 54, and the other end of the storage capacitor 54 is grounded. The gate of transistor 52 is connected to the word line. A character line is connected to multiple memories 50, and a bit line is also connected to multiple memories 50, so these memories 50 constitute a two-dimensional memory array, and each memory is accessed by a crossed bit line and a word line. the

The transistor 52 is described by taking an NMOS transistor as an example. For example, when the data of “1” is to be written into the storage capacitor 54 , a voltage signal of 5V is applied to the corresponding connected bit line. At this time, a turn-on voltage, such as 5V, is applied to the corresponding connected word line to turn on the transistor 52 . At this time, the voltage on the bit line will charge the storage capacitor 54 to 5V. Then the transistor 52 can be turned off by the word line being in a low voltage state. Then turn off the voltage on the bit line, or continue writing to other memories 50 . On the contrary, if the data of "0" is to be written, a voltage signal of 0V will be applied to the bit line, so the voltage of the storage capacitor 54 is 0V. In this way, the data of “1” or “0” is stored according to the voltage level of the storage capacitor 54 . the

The reading mechanism is described below. Figure 2 depicts a conventional read circuit for a memory. Referring to FIG. 2 , if the data on the memory 50 is to be read, the bit line connected to the memory 50 selected to be read is switched to a comparator 56 . The comparator 56 has a reference voltage VRef between 0V and 5V. When the word line turns on the memory 50, the voltage on the bit line is the voltage V of the storage capacitor 54, which is 0V or 5V. By comparing with the reference voltage VRef, it can be known that the voltage V of the storage capacitor 54 is 0V or 5V. the

With regard to the structure of the DRAM memory 50, if the storage capacitor 54 is at a high voltage value for storing “1” data, its charge will be lost due to leakage current, resulting in a voltage drop. If the voltage value of the storage capacitor 54 is not updated for a long time, erroneous data will be generated. In order to update the voltage value of the storage capacitor 54 , the voltage value of the storage capacitor 54 can be updated generally as long as it is read out. The read operation can be real data acquisition or dummy read. As for rewriting the stored value, it will naturally update the data. the

FIG. 3A is a schematic diagram of the mechanism of the traditional distribution update mode. Referring to FIG. 3A , generally n updates are required within a time interval. The traditional refresh operation can be performed on the memory every fixed time evenly distributed in a time interval, which is also called distributed refresh mode. Another update operation is, for example, a burst refresh mode. One pulse represents an update operation. FIG. 3B is a schematic diagram of the mechanism of the traditional cluster update mode. Referring to FIG. 3B , the plex update mode is to perform multiple consecutive update operations once in each time interval. the

Contents of the invention

The present invention provides a method that can reduce the load of the update operation of the DRAM, so as to improve the use efficiency of the DRAM. the

The invention provides an update method for dynamically accessing memory, wherein a memory array is planned with a plurality of storage units, and each storage unit has a count value. The method includes detecting an "unused part" in which data is no longer used in these storage units, and only performing an update operation on a "still used part" in which data is still used in these storage units. the

The present invention provides an update device for dynamically accessing memory, wherein a memory array is planned to have multiple storage units, and each storage unit has a count value, and the update device includes an access control unit; a memory master; an update control unit; and a monitoring unit. The memory main controller accesses a frame data through the access control unit, and the frame data is stored in a part of the storage pages. The update control unit performs an update operation on the storage units according to a designated address. The monitoring unit detects an unused portion of the storage units that is no longer used, and notifies the update control unit to only perform the update operation on a still-used portion of the storage units. the

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings. the

Description of drawings

FIG. 1 is a schematic diagram of the structure of a traditional DRAM memory. the

Figure 2 depicts a conventional read circuit for a memory. the

FIG. 3A is a schematic diagram of the mechanism of the traditional distribution update mode. the

FIG. 3B is a schematic diagram of the mechanism of the traditional cluster update mode. the

FIG. 4 is a schematic diagram of a circuit structure of an updating device for dynamically accessing memory according to an embodiment of the present invention. the

FIG. 5 is a schematic diagram illustrating the relationship between frame and additional information according to an embodiment of the present invention. the

FIG. 6 is a schematic diagram illustrating the correspondence between frame data and storage units according to an embodiment of the present invention. the

FIG. 7 is a characteristic diagram of a down counter according to an embodiment of the present invention. the

FIG. 8 is a characteristic diagram of a down counter according to an embodiment of the present invention. the

FIG. 9 is a schematic flowchart of a method for updating a dynamic access memory according to an embodiment of the present invention. the

Description of main component symbols

50: memory

52: Transistor

54: storage capacitor

60: storage system

62: Memory master control unit

64: access controller

66: memory array

68: DRAM control unit

70: Update control unit

72: Surveillance unit

74: Read/write command

76: Additional Information

S200-S218: Steps

Detailed ways

Considering the traditional update method, no matter what the update mode is, the traditional method will update the memory on the entire DRAM, and some of the memory will still be updated and occupied by storing data that is outdated and will no longer be used. DRAM effectively takes normal read operation time, resulting in an unnecessary burden for update operations. the

The update method of the DRAM memory proposed by the present invention can reduce the burden of the update operation of the DRAM, so as to improve the use efficiency of the DRAM. Some examples are given below to illustrate the present invention, but the present invention is not limited to the examples given.

FIG. 4 is a schematic diagram of a circuit structure of an updating device for dynamically accessing memory according to an embodiment of the present invention. Referring to FIG. 4 , a storage system 60 includes a memory master unit (memory master) 62 , a DRAM control unit 68 , an update control unit 70 , a monitoring unit 72 , and a memory array 66 . Also, the DRAM control unit 68, the update control unit 70 and the monitoring unit 72 are in the access controller 64. The memory array 66 is planned with a plurality of storage units, which will be as described in FIG. 6 later. The DRAM control unit 68 is used to control access to the memory array 66 . The memory main control unit 62 sends a read/write command 74 to the DRAM control unit 68 to access the frame data in the memory array 66 according to the external frame data to be written or read. This read/write command 74 will also be monitored by the monitoring unit 72 to determine the validity of the frame data, to determine which data of the storage units in the memory array 66 are no longer used, so the update control unit 70 is notified only Just perform an update operation on the storage unit that is still in use. the

Here, to determine whether the storage unit is still in use or no longer in use, in addition to the read/write status of the frame data, the memory master can also provide additional information for each frame data ( side information) 76 to assist in judging the usage status of the detected storage unit. the

The mechanism for using additional information is further described below. FIG. 5 is a schematic diagram illustrating the relationship between frame and additional information according to an embodiment of the present invention. Referring to FIG. 5 , the data of a frame is, for example, 480x640 image data, and the memory array 66 may store multiple frames at the same time, and the order of the frames is represented by F0, F1, F2 . . . the

The additional information for frame F0 includes, for example, the start time denoted S and the end time denoted E. The start time S indicates that there will be valid data of the frame F0 after this time point. The end time E indicates that the data of the frame F0 is no longer used after this point in time. In the same mechanism, each frame is known by external operations, and the memory main control unit 62 provides additional information 76 to the monitoring unit 72 . In addition, the read/write command 74 issued by the memory main control unit 62 can also know the address of the storage unit used by the frame. the

The content of the additional information 76 is used to assist in judging the usage status of the detected storage unit. That is to say, the content of the additional information 76 may also have other content, and is not limited to the aforementioned embodiments. the

FIG. 6 is a schematic diagram illustrating the correspondence between frame data and storage units according to an embodiment of the present invention. Referring to FIG. 6 , the memory array 66 is, for example, planned to have N storage units denoted by P-0 to P-N. Frames F0, F1, . . . will be written into some corresponding storage units. Although the drawing uses continuous memory units to store frame data, this is not the only way, and it can be stored according to commonly known writing methods. the

Here, a counter is provided corresponding to each storage unit in the monitoring unit 72 or in the update control unit 70 , to reflect how long the storage unit has not been updated by counting down or counting up. FIG. 7 is a characteristic diagram of a down counter according to an embodiment of the present invention. Referring to FIG. 7 , the counter in this embodiment is described by taking a countdown counter as an example. The down counter corresponding to each storage unit has a maximum constant value nmax when it is initially or completed updating. From the maximum fixed value nmax, the countdown value will be subtracted by 1 every fixed interval over time, such as nmax-1, nmax-2..., and count down to 0 over time. the

However, if the memory cell is updated, its count-down value returns to nmax. Therefore, the countdown value can reflect how long the storage unit has been updated since the last time. If it is longer, the storage capacitor of the memory may change the storage value due to leakage current, resulting in erroneous data. the

Based on this, if the down count value of the storage unit is lower than a critical value and the data stored in the storage unit is still being used, the storage unit needs to be refreshed. the

Another way of judging whether the data of the storage unit continues to be used is to analyze and judge directly according to the reading frequency of the data, which does not need to refer to the additional information 76 . The method is, for example, the following method. the

FIG. 8 is a characteristic diagram of a down counter according to an embodiment of the present invention. Referring to FIG. 8, the count counter is taken as an example. If the data is read or updated, the count value will be reset to the maximum value. In one case, for example, when the count value decreases below a threshold value, an update operation is initiated to reset the count value to the maximum value. With this feature, the count value can be directly detected to determine the usage of the data. the

If the data of the storage unit is frequently read by an externally connected device within a short period of time after being written, the data of the storage unit will be updated with each read, so the countdown value will remain greater than the critical value, and the critical value is Set a small value or can also be 0. If the data of the storage unit is rewritten, it is naturally that new frame data is written. the

However, if the frame data is no longer used, the storage unit used by it will not be updated, so the count-down value will be less than the critical value or reach 0 after a period of time. This means that the data of this frame is likely to be no longer used, so the storage unit whose down count value is less than the critical value can be judged as no longer used, so at least one storage unit used by this frame is not needed Deliberately do update operations. the

However, if the down count value of the storage unit is less than the critical value or is read again after reaching 0, a warning message that the data may be wrong may be issued. In addition, if the storage unit is written, it represents new data, so the old data also needs to be retained. In this way, the use status of the storage unit can be determined according to the reading frequency of the data without the assistance of additional information. the

FIG. 9 is a schematic flowchart of a method for updating a dynamic access memory according to an embodiment of the present invention. Referring to FIG. 9 , according to the above description, the method for updating the dynamic access memory can be simply represented by a flow chart, for example. the

In step S200, frame data is written into at least one storage unit. In step S202, it checks whether the frame data has additional information, and if yes, proceeds to step S204, and if not, proceeds to step S208. In step S204, it uses the additional information of the frame data to detect unused storage units. Then in step S206, it only updates other storage units that are still in use. In step S208, it checks whether the countdown value corresponding to the storage unit is less than a threshold value. This threshold is a set value and can also be 0. In step S210, if the value is less than a threshold value, the corresponding storage unit is set to be unused. In step S212, it monitors whether the memory unit set to be unused continues to be read. In step S214, if it is still being read, a read possible error status is issued. In step S216, if it is no longer read, it waits for the next write. In step S218, if the determination in step S208 is not less than the critical value, the storage unit is accessed normally. Then return to step S202 to continue reading and writing of the detection frame. the

The actual operation process is not necessarily limited to the way shown in Figure 9, but it is mainly based on the auxiliary information of the frame or only based on the actual reading frequency of the storage units to determine which storage units are no longer used, so it can be The update operation of these memory cells that are no longer used is saved. the

Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any ordinary worker in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. the

Claims (13)

1. A method for updating dynamic access memory, wherein a memory array is planned out with a plurality of storage units, and each storage unit has a count value, the method comprising: detecting an unused portion of the storage units in which data is no longer used, while the other portion of the storage units is considered a still-used portion; and An update operation is only performed on the still-used portion of the data in the storage units. 2. The updating method of the dynamic access memory according to claim 1, wherein the updating operation is performed when the count value of any one of the still-used parts of the storage units exceeds a threshold value. 3. The updating method of the dynamic access memory according to claim 1, wherein the detection of the unused portion of the storage units comprises: For a frame data received and written into a memory array by a memory master control unit, an end time point for accessing the frame data and at least one of the memory units used are provided; and When the end time point is detected, the corresponding at least one storage unit used by the frame data is set as the unused portion. 4. The updating method of the dynamic access memory according to claim 1, wherein the detection of the unused portion of the storage units comprises: providing, by a memory master unit, an additional information of a frame data received and written into a memory array and at least one of the memory units used; and It is determined whether the at least one storage unit used by the frame data is to be set as the unused portion according to the additional information. 5. The updating method of the dynamic access memory according to claim 1, wherein the detection of the unused portion of the storage units comprises: Monitoring whether the downcount values of the storage units are less than a critical value, wherein the storage units corresponding to the downcount values smaller than the critical value are set as the unused portion. 6 . The updating method of the dynamic access memory according to claim 5 , wherein an error warning is issued when the storage units corresponding to the down count values smaller than the critical value are still being read. 7. The updating method of the dynamic access memory according to claim 5, wherein the updating operation can still be performed on the storage units corresponding to the down count values smaller than the critical value according to the requirement. 8. An update device for dynamically accessing memory, wherein a memory array is planned with a plurality of storage units, each storage unit has a countdown value, and the update device includes: an access control unit; a memory master, accessing a frame data through the access control unit, the frame data is stored in a part of the storage units; an update control unit, used to perform an update operation on the storage units according to a specified address; and A monitoring unit detects an unused portion of the storage units that is no longer used, and notifies the update control unit to only perform the update operation on an in-use portion of the storage units that is still used. 9. The updating device for dynamic access memory according to claim 8, wherein the updating operation is performed when the downcount value of any one of the still-used parts of the storage units is less than a threshold value. 10. The updating device for dynamic access memory according to claim 8, wherein when the memory main control unit accesses the frame data, it provides an additional information including an end time point of the frame data and the used at least one of the memory cells, Wherein the monitoring unit receives the additional information from the memory main control unit, and when the end time point is detected, the at least one storage unit used by the corresponding frame data is set as the unused part to notify The update control unit does not perform the update operation on the unused portion. 11. The update device for dynamic access memory according to claim 8, wherein the monitoring unit monitors whether the down count values of the storage units are less than a critical value, wherein when any of the down count values is less than The storage units corresponding to the critical value are set as the unused portion. 12 . The updating device for dynamic access memory according to claim 11 , wherein an error warning is issued when the storage units corresponding to the down count values smaller than the critical value are still being read. 13 . 13. The updating method of the dynamic access memory according to claim 11, wherein the updating operation can still be performed on the storage units corresponding to the down count values smaller than the critical value according to the requirement.

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