CN102487007A - Method of forming semiconductor device - Google Patents
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- CN102487007A CN102487007A CN2010105693925A CN201010569392A CN102487007A CN 102487007 A CN102487007 A CN 102487007A CN 2010105693925 A CN2010105693925 A CN 2010105693925A CN 201010569392 A CN201010569392 A CN 201010569392A CN 102487007 A CN102487007 A CN 102487007A
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Abstract
The invention provides a method for forming a semiconductor device, comprising the following steps of: providing a substrate, carrying out first ion implantation on the substrate and forming an ion trap; forming a grid structure on the surface of the substrate; taking the grid structure as a mask, carrying out second ion implantation on the substrate and forming lightly-doped regions comprising lightly-doped source regions and lightly-doped drain regions; forming side walls at the two sides of the grid structure, taking the side walls as masks, carrying out third ion implantation on the substrate and forming heavily-doped regions comprising heavily-doped source regions and heavily-doped drain regions, wherein one or more of a first ion implantation environment, a second ion implantation environment and a third ion implantation environment also comprise one or combination of deuterium ions, fluorine ions or chloride ions. According to the method, the deuterium ions, the fluorine ions or the chloride ions are used for saturating silicon dangling bonds at the interface position between the substrate and the grid structure, so as to restrain the hot electron effect.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of formation method of semiconductor device.
Background technology
The integrated circuit especially main devices in the very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor is called for short MOS).Integrated circuit is since invention, and its progress on performance and function is advanced by leaps and bounds, and the physical dimension of MOS device constantly dwindling always, and its characteristic size has got into nanoscale at present.
In the scaled process of MOS device, drain voltage does not reduce thereupon, and this just causes the increase of the channel region electric field between source electrode, drain electrode; Under the highfield effect; Electronics can accelerate to the speed than high times of heat movement speed between twice collision, so kinetic energy is very big, and these electronics are called as hot electron; Said hot electron can inject to gate dielectric layer, thereby causes thermoelectronic effect (hot electroneffect).This effect belongs to the small-size effect of device, and said effect can cause gate electrode electric current and Semiconductor substrate electric current, influences the reliability of device and circuit.
Above-mentioned thermoelectronic effect is a key factor that influences MOS device lifetime (TTF): thermoelectronic effect more a little less than, device lifetime is long more; Otherwise thermoelectronic effect is obvious more, and device lifetime is short more.In order to improve MOS device lifetime, need to suppress thermoelectronic effect.For nmos device, thermoelectronic effect is particularly outstanding.Because the charge carrier of NMOS is an electronics, and the charge carrier of PMOS is the hole, with the hole relatively, the electronics interface potential barrier between Semiconductor substrate and the gate dielectric layer of jumping over more easily, thus make electronics injection grid dielectric layer more easily, cause injury to gate dielectric layer.
Publication number is a kind of nmos device with pocket (pocket) structure of doping that provides in the one Chinese patent application of CN1393935A, has suppressed thermoelectronic effect to a certain extent.Said structure is as shown in Figure 1, comprising: Semiconductor substrate 001 is provided, on said Semiconductor substrate 001, injects the boron ion, form P type trap 002 and channel region (not indicating among the figure); On said Semiconductor substrate 001 surface, form gate dielectric layer 003 and gate electrode 004 successively, the Semiconductor substrate of said gate electrode 004 both sides is source region and drain region; In said source region and drain region, inject indium ion, to form pocket area 005; Continuation is injected phosphonium ion in said source region and drain region, form light doping section 006; Both sides at gate dielectric layer 003 and gate electrode 004 form sidewall 007; At last, mixed deeply in said source region and drain region, to form source electrode 008 and drain electrode 009.
The improvement of prior art mainly is the improvement that concentrates on source-and-drain junction, leaks (LDD) etc. like above-mentioned employing lightly-doped source.Above-mentioned improvement will effectively reduce channel region drain terminal electric field, reduce the charge carrier that is excited, thereby improve hot carrier's effect.But these improvement do not relate to the minimizing charge carrier catches probability in gate oxide, promptly how effectively to reduce the interfacial state in the gate oxide, mainly is to reduce the interface trap of catching charge carrier.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of semiconductor device, improves the thermoelectronic effect of the semiconductor device of prior art formation.
For addressing the above problem, the present invention provides a kind of formation method of semiconductor device, comprising:
Substrate is provided, said substrate is carried out first ion inject, form ion trap;
On said substrate surface, form grid structure;
With said grid structure is mask, said substrate is carried out second ion inject, and forms light doping section, comprises light dope source region and lightly doped drain;
Form side wall in the both sides of said grid structure, and be mask, said substrate is carried out the 3rd ion inject, form heavily doped region, comprise heavy doping source region and heavy doping drain region with said side wall;
Wherein, said first ion injects a kind of ion injection environment or a plurality of ion injection environment that environment, second ion injection environment and the 3rd ion inject environment, also includes a kind of or combination in deuterium ion, fluorine ion or the chloride ion.
Optional, said ion trap is N type trap or P type trap.
Optional, if P type trap, said first ion is the boron ion; If N type trap, said first ion is arsenic or phosphonium ion.
Optional, the implantation dosage of said deuterium ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev, implant angle is 0～60 degree.
Optional, the implantation dosage of said fluorine ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev, implant angle is 0～60 degree.
Optional, the implantation dosage of said chloride ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev, implant angle is 0～60 degree.
The present invention also provides a kind of formation method of semiconductor device, comprising:
Substrate is provided, said substrate is carried out first ion inject, form ion trap;
On said substrate surface, form grid structure;
With said grid structure is mask, said substrate is carried out second ion inject, and forms light doping section, comprises light dope source region and lightly doped drain;
Form side wall in the both sides of said grid structure, and be mask, said substrate is carried out the 3rd ion inject, form heavily doped region, comprise heavy doping source region and heavy doping drain region with said side wall;
After a kind of ion implantation technology of inject at said first ion, second ion injecting and the 3rd ion injects or a plurality of ion implantation technology, also include a kind of or combination that deuterium ion injects, fluorine ion injects or chloride ion injects.
Optional, said ion trap is N type trap or P type trap.
Optional, if P type trap, said first ion is the boron ion; If N type trap, said first ion is arsenic or phosphonium ion.
Optional, the implantation dosage of said deuterium ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev, implant angle is 0～60 degree.
Optional, the implantation dosage of said fluorine ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev, implant angle is 0～60 degree.
Optional, the implantation dosage of said chloride ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev, implant angle is 0～60 degree.
Compared with prior art, the present invention has following advantage: one or more of deuterium ion, fluorine ion and chloride ion are introduced in said ion trap, light doping section and the heavily doped region, with the silicon dangling bonds of saturated substrate surface.The bond energy of said silicon deuterium, fluosilicic and silicon chlorine key is all bigger simultaneously, in the process environments in the external world, is not easy to cause scission of link, reduces to be positioned at the silicon dangling bonds of said ion trap near substrate surface, suppresses thermoelectronic effect.
Description of drawings
Fig. 1 is the structural representation of the semiconductor device of prior art.
Fig. 2 is that the semiconductor device of one embodiment of the invention forms the method flow sketch map.
Fig. 3 to Fig. 8 is the semiconductor device formation method structural representation of one embodiment of the invention.
Embodiment
The present invention provides a kind of formation method of semiconductor device, comprises substrate is provided, and said substrate is carried out first ion inject, and forms ion trap; On said substrate surface, form grid structure; With said grid structure is mask, said substrate is carried out second ion inject, and forms light doping section, comprises light dope source region and lightly doped drain; Form side wall in the both sides of said grid structure, and be mask, said substrate is carried out the 3rd ion inject, form heavily doped region, comprise heavy doping source region and heavy doping drain region with said side wall; Wherein said first ion injects a kind of ion injection environment or a plurality of ion injection environment that environment, second ion injection environment and the 3rd ion inject environment, also includes a kind of or combination in deuterium ion, fluorine ion or the chloride ion.
As shown in Figure 2, the formation method of said semiconductor device comprises:
Step S1 provides substrate, said substrate is carried out first ion inject, and forms ion trap, and said ion trap is P type trap or N type trap, and said first ion injects environment and includes a kind of of deuterium ion, fluorine ion or chloride ion or combination;
Step S2 forms grid structure on said substrate surface;
Step S3 is a mask with said grid structure, said substrate is carried out second ion inject, and forms light doping section, and said second ion injects environment and includes a kind of of deuterium ion, fluorine ion or chloride ion or combination;
Step S4; Form side wall in the both sides of said grid structure, and be mask, said substrate is carried out the 3rd ion inject with said side wall; Form source region and drain region, said the 3rd ion injects environment and includes a kind of of deuterium ion, fluorine ion or chloride ion or combination.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed practical implementation.
Fig. 3 to Fig. 8 is the formation method structural representation of the semiconductor device of one embodiment of the invention.
As shown in Figure 3, substrate 110 is provided, said Semiconductor substrate 110 can be silicon or SiGe, also can be silicon-on-insulator (SOI), perhaps can also comprise other material, for example III-V compounds of group such as GaAs.Also be formed with isolation structure 120 in the said substrate 110, be used to isolate the active area of follow-up formation.
Continuation is carried out first ion and is injected with reference to figure 3 in said Semiconductor substrate 110, form ion trap 130, and said ion trap 130 is P type trap or N type trap.
If said ion trap 130 is a P type trap, can be 1～5 * 10 through implantation dosage
13/ cm
2Boron, the injection energy is 10～500Kev, is preferably 200Kev.If said ion trap 130 is a N type trap, then can select through implantation dosage is 1～5 * 10
13/ cm
2Arsenic or phosphorus, the injection energy is 10～500Kev, is preferably 200Kev.
Wherein, said first ion injects environment, except being used for doped P-type or N type first ion, also includes in deuterium ion, fluorine ion and the chloride ion one or more.In the present embodiment, be the combination of deuterium ion, fluorine ion and chloride ion.Particularly, can produce deuterium ion, ionization boron fluoride generation fluorine ion through ionization deuterium gas, ionization hydrogen chloride produces chloride ion.
Through said method said deuterium ion, fluorine ion and chloride ion are introduced in the said ion trap, with the silicon dangling bonds of saturated said ion trap near substrate surface.The bond energy of said silicon deuterium, fluosilicic and silicon chlorine key is all bigger simultaneously, in the process environments in the external world, is not easy to cause scission of link, reduces to be positioned at the silicon dangling bonds of said ion trap near substrate surface, suppresses thermoelectronic effect.
The implantation dosage of said deuterium ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev; The implantation dosage of said fluorine ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev; The implantation dosage of said chloride ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev.
In the present embodiment, said ion trap 130 is a P type ion trap, and said first ion is the boron ion, at the acceleration energy and about 3.0 * 10 of 200Kev
13/ cm
2Dosage under, the boron ion is injected in the Semiconductor substrate 110, thereby forms P type trap 130; Simultaneously, said first ion injects environment also to include dosage is 3.0 * 10
14/ cm
2Deuterium ion, dosage be 3.0 * 10
14/ cm
2Fluorine ion, dosage is 3.0 * 10
14/ cm
2Chloride ion, be used for the silicon dangling bonds of saturated said P type trap 130 near substrate surface.
Further, can also be at the acceleration energy and about 5.0 * 10 of 20Kev
12/ cm
2Dosage under, inject the boron ion and form the channel region (figure does not indicate) that is arranged in substrate 110 upper surfaces, with the adjusting threshold voltage.
As shown in Figure 4, be formed with grid structure on the said substrate 110.Said grid structure comprises gate dielectric layer 140 and gate electrode 150.
In the present embodiment, said gate dielectric layer 140 comprises silica, silicon nitride, and the formation technology of said gate dielectric layer 140 is following, comprising:
1 steam original position generates that (situ stream-generated ISSG) or rapid thermal treatment (RTO), forms basic oxide layer, and the temperature range of said formation is 700～1100 ℃, and the thickness of said base oxide is 0.5～3nm;
2 in nitrogen environment, carry out decoupled plasma nitrogen handle (decoupled plasma nitridation, DPN);
3 carry out after annealing handles, and forms gate dielectric layer 140.
Continue also to be included on the said gate dielectric layer 140 and to form polysilicon layer with reference to shown in Figure 4, form gate electrode layer 150, said gate electrode layer 150 formation methods can be chemical vapour deposition technique.
As shown in Figure 5, to said gate dielectric layer 140 and gate electrode layer 150 patternings, and said gate dielectric layer 140 of etching and gate electrode layer 150 successively, form grid structure.Particularly, on said gate electrode layer 150, forming the photoresist layer (not shown) of patterning, is mask with said photoresist layer, and said gate electrode layer 150 of etching and gate dielectric layer 140 form grid structure successively.The substrate that is positioned at said grid structure both sides is source region and drain region.
As shown in Figure 6, be mask with said grid structure, the substrate 110 that is positioned at said grid structure both sides is carried out second ion doping, form the light dope ion district 160 that is positioned at said grid structure both sides.In the present embodiment, said second ion is a phosphonium ion.
Particularly, utilize gate dielectric layer 140 and gate electrode layer 150, at acceleration energy and the about 1E14～2.5E14/cm of 1～5kev as mask
2Dosage under, the substrate that is positioned at said grid structure both sides 110 is injected phosphonium ions, be mixed with the light doping section 160 of phosphonium ion with formation, it injects degree of depth is tens of to the hundreds of dust.As an embodiment, the acceleration energy of choosing is 4kev, and the implantation dosage of phosphonium ion is 2.0E14/cm
2
Wherein said second ion injects environment, also includes in deuterium ion, fluorine ion and the chloride ion one or more.In the present embodiment, be the combination of deuterium ion, fluorine ion and chloride ion.Particularly, can produce deuterium ion, ionization boron fluoride generation fluorine ion through ionization deuterium gas, ionization hydrogen chloride produces chloride ion.
Through said method said deuterium ion, fluorine ion and chloride ion are introduced in the said light doping section 160; With the saturated silicon dangling bonds at the interface that are positioned at said light doping section 160 and said gate dielectric layer 140; The bond energy of said silicon deuterium, fluosilicic and silicon chlorine key is all bigger, in the process environments in the external world, is not easy to cause scission of link; Reduce the silicon dangling bonds at the interface that are positioned at said light doping section 160 and said gate dielectric layer 140, suppress thermoelectronic effect.
The implantation dosage of said deuterium ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev; The implantation dosage of said fluorine ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev; The implantation dosage of said chloride ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev.
After forming said lightly doped region 160 formation; Said Semiconductor substrate 101 is heat-treated; The dopant ion of lightly doped region is taken place vertically and horizontal diffusion, its part is diffused in the substrate 110 of gate dielectric layer 140 belows, form light dope source electrode and lightly doped drain.
As shown in Figure 7, form side wall in the grid structure both sides.Specifically comprise: on said substrate 110, form the dielectric layer (not shown); In the present embodiment; Said dielectric layer is a silica material; Generation type can be low-pressure chemical vapor phase deposition (LPCVD), and thickness is higher than the height of said gate electrode layer 150, and said dielectric layer also can be selected oxide layer-silicon nitride-oxide layer (ONO) structure for use; Then said dielectric layer is returned (etch back) technology at quarter, form side wall 170 in said grid structure both sides.Said side wall 170 act as grill-protected electrode layer 150.
As shown in Figure 8, be mask with said side wall 170, be positioned at dark doping of substrate 110 row of said side wall 170 both sides, form source electrode and drain electrode.
Specifically comprise: as shown in Figure 8, on said substrate 110 surfaces, be mask with side wall 170, to light doping section 160, comprise that light dope source region and lightly doped drain carry out the 3rd ion and inject, form heavily doped region 190, comprise heavy doping source region and heavy doping drain region.Said heavy doping source region is as transistorized source electrode, and said heavy doping drain region is as transistor drain.
The 3rd ionic type that injects in the embodiment of the invention is the N type, like phosphorus, arsenic, antimony.The ion dose that said source electrode, drain electrode are injected is 10
14～10
15/ cm
2The order of magnitude injects ion energy and is 10 to 100Kev.
Said the 3rd ion injects environment, removes said the 3rd ion, as as outside the dopant ions such as phosphorus, arsenic, antimony, also includes in deuterium ion, fluorine ion and the chloride ion one or more.In the present embodiment, be the combination of deuterium ion, fluorine ion and chloride ion.Particularly, can produce deuterium ion, ionization boron fluoride generation fluorine ion through ionization deuterium gas, ionization hydrogen chloride produces chloride ion.
Through said method said deuterium ion, fluorine ion and chloride ion are introduced in the said heavily doped region 190; With the saturated silicon dangling bonds at the interface that are positioned at said heavily doped region 190 and said gate dielectric layer 140; The bond energy of said silicon deuterium, fluosilicic and silicon chlorine key is all bigger, in the process environments in the external world, is not easy to cause scission of link; Reduce the silicon dangling bonds at the interface that are positioned at said heavily doped region 190 and said gate dielectric layer 140, suppress thermoelectronic effect.
The implantation dosage of said deuterium ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev; The implantation dosage of said fluorine ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev; The implantation dosage of said chloride ion is 1 * 10
13～1 * 10
16/ cm
2, the injection energy is 200ev～25Kev.
In the present embodiment, inject environment, second ion injection environment and the 3rd ion injection environment at first ion and all contain a kind of of deuterium ion, fluorine ion and chloride ion or combination simultaneously.As other embodiment, can also inject environment, second ion at first ion optionally and inject one or more ions that environment and the 4th ion inject environment and inject environment and contain a kind of of deuterium ion, fluorine ion and chloride ion or combination.
The inventor finds; After first ion, second ion and the 3rd ion inject, high annealing is also arranged, through said high annealing; Effective implantation dosage of said deuterium ion, fluorine ion and chloride ion will reduce, and reduces the effect of the silicon dangling bonds in the saturated substrate.
For addressing the above problem, the present invention provides a kind of formation method of semiconductor device, comprising: substrate is provided, said substrate is carried out first ion inject, form ion trap; On said substrate surface, form grid structure; With said grid structure is mask, said substrate is carried out second ion inject, and forms light doping section, comprises light dope source region and lightly doped drain; Form side wall in the both sides of said grid structure, and be mask, said substrate is carried out the 3rd ion inject, form heavily doped region, comprise heavy doping source region and heavy doping drain region with said side wall; After a kind of ion implantation technology of wherein inject, second ion injecting and the 3rd ion injects or a plurality of ion implantation technology, also include a kind of or combination that deuterium ion injects, fluorine ion injects or chloride ion injects at said first ion.
Said deuterium ion, fluorine ion and chloride ion carry out after first ion, second ion or the 3rd ion inject, comprise the high-temperature annealing process that ion injects; Improve the valid density of said deuterium ion, fluorine ion, chloride ion, improve the effect of the silicon dangling bonds in the saturated substrate.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (12)
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|---|---|---|---|
| CN2010105693925A CN102487007A (en) | 2010-12-01 | 2010-12-01 | Method of forming semiconductor device |
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|---|---|---|---|
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| CN105047566A (en) * | 2015-08-11 | 2015-11-11 | 上海华力微电子有限公司 | Method for restraining reverse short channel effect and manufacturing method of NMOS (N-Channel Metal Oxide Semiconductor) device |
| CN105679712A (en) * | 2015-12-31 | 2016-06-15 | 上海华虹宏力半导体制造有限公司 | Technique for SONOS device |
| CN109103111A (en) * | 2018-09-27 | 2018-12-28 | 武汉新芯集成电路制造有限公司 | A kind of forming method of PMOS structure |
| KR20220055522A (en) * | 2020-10-26 | 2022-05-04 | 티이엠씨 주식회사 | Gas mixture for Ion Implantation. |
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| CN101572251A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device, n-type MOS transistor and manufacturing method thereof |
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