CN102479806A - Super junction semiconductor device and manufacturing method thereof - Google Patents
Super junction semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102479806A CN102479806A CN2010105535353A CN201010553535A CN102479806A CN 102479806 A CN102479806 A CN 102479806A CN 2010105535353 A CN2010105535353 A CN 2010105535353A CN 201010553535 A CN201010553535 A CN 201010553535A CN 102479806 A CN102479806 A CN 102479806A
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Abstract
The invention discloses a super junction semiconductor device. P type and N type semiconductor thin layer structures are alternatively arranged on an N<+> silicon substrate, wherein P type impurity concentration varies along a groove direction; the impurity concentration of a part close to the upper surface of a P/N thin layer is higher than the concentration of P type impurities required by charge balance; the impurity concentration of a part close to the lower surface of the P/N thin layer is lower than the concentration of P type impurities required by charge balance; and the maximum concentration variation gradients of the part close to the lower surface of the P/N thin layer is higher than that of the part close to the upper surface of the P/N thin layer. The invention further discloses a manufacturing method of the super junction semiconductor device. According to the invention, the uniformity of the reverse breakdown voltage of the device and the reliability of the device can be enhanced.
Description
Technical field
The present invention relates to the semiconductor integrated circuit field, particularly relate to a kind of super junction-semiconductor device.The invention still further relates to a kind of manufacture method of super junction-semiconductor device.
Background technology
The device of super-junction structures replaces the N drift region among traditional VDMOS (longitudinal double diffusion metal oxide semiconductor transistor) through the structure of utilizing P/N to replace assortment.The VDMOS technology that its combination is known in the industry just can be made the MOSFET (metal oxide semiconductor field effect tube) that obtains super-junction structures; It can through using the epitaxial loayer of low-resistivity, significantly reduce the conducting resistance of device under the reverse breakdown voltage situation consistent with traditional VDMOS.The charge carrier distribution and their coupling of distribution of the charge carrier of N type impurity and p type impurity can influence Devices Characteristics in the P/N semiconductor lamella, comprises reverse breakdown voltage and current handling capability.
All adopts in the general designs and make the charge balance that reaches the best in the P/N semiconductor lamella alternately reverse breakdown voltage with the maximum that obtains device; But the reverse breakdown of device possibly occur in the N district and also possibly occur in the P district under such condition; And, hope that the reverse breakdown of device occurs in the N+ area near device in P district from the requirement of the current handling capability and the reliability of device.
Summary of the invention
The technical problem that the present invention will solve provides a kind of super junction-semiconductor device, can improve the uniformity of device reverse breakdown voltage and the reliability of device; For this reason, the present invention also will provide a kind of manufacture method of super junction-semiconductor device.
For solving the problems of the technologies described above, super junction-semiconductor device of the present invention is to adopt following technical scheme to realize:
On the N+ silicon substrate, have P type and the N type semiconductor laminate structure alternately arranged; Wherein, P type impurity concentration changes perpendicular to N+ silicon substrate direction on the edge; The concentration that is distributed in impurity concentration near the part of P/N semiconductor lamella upper surface required p type impurity when being higher than charge balance of p type impurity, the concentration of required p type impurity when being lower than charge balance near the impurity concentration of the part of P/N semiconductor lamella lower surface; Near the Cmax variable gradient of P/N semiconductor lamella bottom surface section greater than Cmax variable gradient near the part of P/N thin layer upper surface.
The p type impurity concentration of mid portion can be also can not changing of changing; When the p type impurity concentration of centre part be change the time, near the Cmax variable gradient of P/N semiconductor lamella bottom surface section Cmax variable gradient greater than the p type impurity of mid portion.
Said being meant from upper surface near upper surface portion played the part that the degree of depth is less than total p type impurity degree of depth 1/4; Said being meant from lower surface near bottom surface section played the part that the degree of depth is less than total p type impurity degree of depth 1/4; Said mid portion is meant in the p type impurity above-mentioned near upper surface portion with near the part between the upper surface portion.
The width of said P type semiconductor thin layer is less than or equal to the width of N type semiconductor thin layer.
The manufacture method of super junction-semiconductor device of the present invention is to adopt following technical scheme to realize, on the N+ silicon substrate, forms P type and the N type semiconductor thin layer of alternately arranging, wherein:
85% of p type impurity concentration when the P type semiconductor thin layer impurity concentration of bottom ground floor is lower than the N type semiconductor thin layer impurity concentration that makes same horizontal level and reaches optimum balance; 105% of p type impurity concentration when the P type semiconductor thin layer impurity concentration of the bottom second layer equals to make the N type semiconductor thin layer impurity concentration of same horizontal level to reach optimum balance; 115% of P type semiconductor thin layer impurity concentration when the P type semiconductor thin layer impurity concentration of top ground floor equals to make the N type semiconductor thin layer impurity concentration of same horizontal level to reach optimum balance; P type impurity concentration when the P type semiconductor thin layer impurity concentration of the top second layer equals to make the N type semiconductor thin layer impurity concentration of same horizontal level to reach optimum balance.
The 90%-110% of the P type semiconductor thin layer impurity concentration when the P type semiconductor thin layer impurity concentration in intermediate layer equals to make the N type impurity concentration of same horizontal level to reach optimum balance.
The present invention adopts the impurities concentration distribution mode of non-uniform Distribution to realize the P/N semiconductor lamella of alternately arranging; Wherein, through the design of uneven impurities concentration distribution in the P type semiconductor thin layer, make the reverse breakdown of device occur in the P district; And can in the processing range of producing, make reverse breakdown occur in the zone near the N+ silicon substrate in P district; Improve the big current handling capability (EAS) of device, the electric field strength of maximum when reducing the generation of device reverse breakdown, the reliability of raising device; Reduce the sensitivity that device reverse breakdown voltage changes impurity concentration, improve the rate of finished products of device.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1-2 is the schematic flow sheet of method embodiment one of the present invention;
Fig. 3 is through the embodiment one final super junction nmos device cellular construction sketch map that forms;
Fig. 4-the 5th, the schematic flow sheet of method embodiment two of the present invention;
Fig. 6 is through the embodiment two final super junction nmos device cellular construction sketch mapes that form;
Fig. 7 is the impurities concentration distribution sketch map that adopts in the P/N thin layer that method of the present invention obtains;
Fig. 8 is that p type impurity concentration edge evenly distributes perpendicular to N+ silicon substrate direction, under different p type impurity concentration, and electric field distribution map vertically in the N type semiconductor thin layer when reverse breakdown takes place;
Fig. 9 is a p type impurity concentration when evenly distributing perpendicular to N+ silicon substrate direction, under different p type impurity concentration, and electric field distribution map vertically in the P type semiconductor thin layer when reverse breakdown takes place;
Figure 10 is that p type impurity concentration edge is under the situation about changing perpendicular to N+ silicon substrate direction, and several p type impurity concentration are along the distribution map (through after whole thermal processs) perpendicular to N+ silicon substrate direction;
Figure 11 be p type impurity concentration by distribution shown in Figure 10, electric field distribution map vertically in the N type semiconductor thin layer when reverse breakdown takes place;
Figure 12 be p type impurity concentration by distribution shown in Figure 10, electric field distribution map vertically in the P type semiconductor thin layer when reverse breakdown takes place;
Figure 13 is near (p type impurity concentration is greater than 2.1E15/CM3) reverse breakdown occurs near the N+ silicon substrate time, the graph of a relation that puncture voltage and impurity concentration central value change under the uniform P type semiconductor thin layer of impurity concentration and two kinds of conditions of P type semiconductor thin layer heterogeneous.
Embodiment
Be that the device of 600V specifies to reverse breakdown voltage among the embodiment below; Used N type impurity concentration is C2=1E15/CM3; The width D 2 of N type semiconductor thin layer is 12 microns in each P/N semiconductor lamella unit; The width D 1 of P type semiconductor thin layer is 5 microns, and the best p type impurity concentration that reaches charge balance is that C2* (D2/D1) is 2.4E15/CM3.
Embodiment one
Said N-epitaxial loayer can be grown on the said N+ silicon substrate, also can be grown on the N-epitaxial buffer layer that is positioned on the N+ silicon substrate.
Process in step 2, the repeating step one (is 2 growths of N-epitaxial loayer; Form the figure of p type island region opening; P type ion injects), reach the thickness that needs after, again through the annealing of elevated temperature heat process with push away trap; Just can obtain the P type semiconductor thin layer and the N type semiconductor thin layer of alternately arrangement, as shown in Figure 2.The different p type impurity concentration of diverse location can be injected through different ions and obtain among Fig. 2.In order to obtain uniform impurity concentration in a zone, the injection after a photoetching can be adopted the repeatedly injection of different-energy; The mode that also can reduce each epitaxially grown thickness (but needing to increase the number of times that total epitaxial growth-photoetching-P type ion injects) realizes.
In conjunction with shown in Figure 3,, obtain the distribution of such p type impurity concentration: 85% of the p type impurity concentration when the p type island region 52-1 impurity concentration of bottom ground floor is lower than the N type impurity concentration that makes same horizontal level and reaches optimum balance through after the above technological process; 105% of p type impurity concentration when the p type island region 52-2 impurity concentration of the bottom second layer equals to make the N type impurity concentration of same horizontal level to reach optimum balance; The 90%-110% (not shown in the figures, the intermediate layer can have, and also can not have) of the p type impurity concentration when the p type island region impurity concentration in intermediate layer equals to make the N type impurity concentration of same horizontal level to reach optimum balance; 115% of p type impurity concentration when the p type island region 52-4 impurity concentration of top ground floor equals to make the N type impurity concentration of same horizontal level to reach optimum balance; P type impurity concentration when the p type island region impurity concentration of top second layer 52-3 equals to make the N type impurity of same horizontal level to reach optimum balance.
In conjunction with shown in Figure 3, afterwards, utilize ripe VDMOS processing technology to obtain corresponding super junction NMOS (N NMOS N-channel MOS N) device unit construction; Comprise: the gate oxidation films 5 and polysilicon electrode 6 that are positioned at N-epitaxial loayer 2 upper ends; Be positioned at the P trap 7 on N-epitaxial loayer 2 and P type thin layer top, be arranged in the N+ source 8 of P trap 7, coat the inter-level dielectric film 9 of said polysilicon electrode 6; Be arranged in the source metal electrode 12 of contact hole 10 and inter-level dielectric film 9 tops; In the middle of the contact hole and be positioned at the P+ contact implanted layer 11 on P type thin layer top,, be positioned at the drain electrode 14 (back metal) of N+ silicon substrate 1 lower surface with the polycrystalline electrodes (not shown) that polycrystalline grid 6 are drawn.
Embodiment two
The sidewall of said groove 41 can be vertical, also can tilt.The bottom of said groove 41 can be smooth, also crooked radian can be arranged.
Said silicon oxide film 31 can obtain through thermal oxidation, also can realize through chemical vapor deposition (CVD).Can be to utilize silicon oxide film 31 as mask during etching groove, also can utilize photoresist as mask, the thickness suggestion of the silicon oxide film 31 after the etching be more than 1000 dusts.
In conjunction with shown in Figure 6, the impurity in the P type silicon here is used for the N type impurity of the adjacent N type semiconductor thin layer of balance and has following characteristics: 85% of the p type impurity concentration the when impurity concentration of the p type island region 42-1 of first area, bottom is lower than the N type impurity concentration that makes same horizontal level and reaches optimum balance; 105% of p type impurity concentration when the impurity concentration of p type island region 42-2 of bottom second area equals to make the N type impurity concentration of same horizontal level to reach optimum balance; The 90-110% (not shown in the figures, zone line can have, and also can not have) of the p type impurity concentration the when impurity concentration of the p type island region of zone line equals to make the N type impurity of same horizontal level to reach optimum balance; 115% of p type impurity concentration when the impurity concentration of the p type island region 42-1/ of first area, top equals to make the N type impurity concentration of same horizontal level to reach optimum balance; P type impurity concentration when the impurity concentration of the p type island region in 42-2/ territory, second district, top equals to make the N type impurity concentration of same horizontal level to reach optimum balance.
Described P type silicon can be monocrystalline silicon, polysilicon or indefinite form silicon.The growth temperature of p type single crystal silicon can be 650 ℃ to 1200 ℃, and the growth temperature of P type polysilicon can be 580 ℃ to 650 ℃, and the growth temperature of P type indefinite form silicon can be 510 ℃ to 579 ℃.In the present embodiment, what fill in the groove 41 all is P type silicon, utilizes cmp or returns the P type silicon removal of carving groove 41 surfaces; And, the P type of arrangement and the structure of N type semiconductor thin layer have just been obtained replacing with silicon oxide film 31 removals;
In conjunction with shown in Figure 6, afterwards, utilize ripe VDMOS processing technology to obtain corresponding super junction NMOS (N NMOS N-channel MOS N) device unit construction; Comprise: the gate oxidation films 5 and polysilicon electrode 6 that are positioned at N-epitaxial loayer 2 upper ends; Be positioned at the P trap 7 on N-extension and P type thin layer top, be arranged in the N+ source 8 of P trap 7, coat the inter-level dielectric film 9 of said polysilicon electrode 6; Be arranged in the source metal electrode 12 of contact hole 10 and inter-level dielectric film 9 tops; In the middle of the contact hole and be positioned at the P+ contact implanted layer 11 on P type thin layer top,, be positioned at the drain electrode 14 (back metal) of N+ silicon substrate 1 lower surface with the polycrystalline electrodes (not shown) that polycrystalline grid 6 are drawn.
Among Fig. 3 and 6, A representes that the position of tying between the N type semiconductor in P trap 7 and N-epitaxial loayer 2 zones, B represent the position of tying between the P type semiconductor and N type semiconductor in the P type semiconductor coating region.
Fig. 7 is the impurities concentration distribution sketch map in the P/N thin layer that obtains of the above-mentioned two kinds of embodiment of above-mentioned employing; Wherein, Impurity concentration is evenly constant in N type thin layer; Impurity concentration is the highest approaching the device front in the P type thin layer, the p type impurity concentration when reaching best charge balance greater than the N type impurity that makes same horizontal level; Be minimum near the zone of N+ silicon substrate 1, the p type impurity concentration when reaching best charge balance less than the N type impurity that makes same horizontal level; And, near the variable gradient of the p type island region impurity concentration in the positive zone of device less than zone near N+ silicon substrate 1.
For implementing two; Through after the thermal process of back; P type impurity concentration is as shown in Figure 8 perpendicular to the distribution on N+ silicon substrate 1 direction; The thickness of total here N-epitaxial loayer 2 is 45 microns, and the degree of depth of groove 41 is 40 microns, and the distance between the top of the bottom of groove 41 and N+ silicon substrate 1 is 5 microns.Coordinate 0 place is the top of N+ silicon substrate 1 among Fig. 8, and-45 microns places are N-epitaxial loayer 2 tops in the front of device.
Is equally distributed situation to the p type island region impurity concentration in vertical direction, to different p type impurity concentration (1.3E15/CM3; 1.7E15/CM3; 2.1E15/CM3; 2.5E15/CM3; 2.9E15/CM3; 3.3E15/CM3) situation carried out TCAD (Computer-aided Design Technology) simulation; Maximum field point when the puncture that obtains takes place in p type island region and N type district, from this some edge perpendicular to the size of total electric field of the direction of N+ silicon substrate 1 shown in Fig. 8 (the N district) and Fig. 9 (in the P district).From figure, see,, puncture and occur in the position that device approaches upper surface when p type impurity concentration during less than 2.1E15/CM3; When p type impurity concentration greater than or etc. during 2.5E15/CM3, puncture and occur in the position that device approaches N+ silicon substrate 1.
To the p type island region impurity concentration is the situation of uneven distribution in vertical direction; Get the impurity concentration C1=C*85%*D2/D1 of bottom the one 1/4 caliper zones (like the 42-1 among Fig. 5); The impurity concentration C2=C*105%*D2/D1 of bottom the 2 1/4 caliper zones (like the 42-2 among Fig. 5); The impurity concentration C2 '=C*115% * D2/D1 of top the one 1/4 caliper zones (like the 42/-1 among Fig. 5), impurity concentration the C1 '=C*D2/D1 of top the 2 1/4 caliper zones (like the 42/-2 among Fig. 5); To several kinds of different impurity concentration C (1.3E15/CM3; 1.7E15/CM3; 2.1E15/CM3; 2.5E15/CM3; 2.9E15/CM3; 3.3E15/CM3) situation, shown in figure 10 through the p type impurity concentration distribution vertically after the thermal process of arts demand, coordinate 0 place is the top of N+ silicon substrate 1 among the figure ,-45 microns places are N-epitaxial loayer 2 tops in the front of device.Situation to different p type impurity concentration has been carried out the TCAD simulation; Maximum field point when the puncture that obtains takes place in p type island region and N type district, from this some edge perpendicular to the size of total electric field of the direction of N+ silicon substrate 1 shown in Figure 11 (the N district) and Figure 12 (in the P district); The centre concentration of the p type impurity here is meant that the value with C1 ' is displaced to the value shown in the figure from best C*D2/D1; From figure, see,, puncture and occur in the position that device approaches upper surface when p type impurity concentration during less than 2.1E15/CM3; When p type impurity concentration greater than or etc. during 2.5E15/CM3, puncture and occur in the position that device approaches the n+ substrate.
Data to the maximum field under top two kinds of situation compare; Obtain the data of following table 1, from table 1, see, with respect to the electric field maximum basically identical in the N type thin layer under the situation in two; In P type thin layer; Maximum field under non-homogeneous situation occurs in the P type thin layer owing to puncture less than evenly dividing the maximum field that plants, the current handling capability and the reliability that improves device that reduce to improve device of this electric field.
Table 1
Further; In order to improve the current handling capability of device; The occurrence positions that preferably makes puncture is not only in P type thin layer; And being in position near N+ silicon substrate 1, the electronics that punctures the secondary electron-hole centering that produces when taking place is that N+ silicon substrate 1 (high positive voltage) absorbs very soon, to the not influence of puncture voltage of device; During move toward the P+ contact hole of top device in the hole that produces; Because its top that will arrive is that the fixed charge quantity born is greater than desirable quantity puncturing when just taking place; The arrival in this hole has reduced this species diversity improves the puncture voltage of device; Formed the negative feedback of puncture voltage and number of cavities, it is right to help reducing follow-up secondary electron-hole, has improved the current handling capability of device; So hope the centre concentration of P type thin layer is used greater than 2.1E15/CM3;
Utilize TCAD to simulate, obtain under the situation of even and non-uniform doping, the relation that the puncture voltage of device and impurity concentration central value change, shown in figure 13; Can see that from figure under the situation of non-homogeneous CONCENTRATION DISTRIBUTION, for same p type impurity concentration change scope, the excursion of puncture voltage little when even promptly improved the stability of device electric breakdown strength.
In theory, uneven impurities concentration distribution also can have the foregoing description similar effects in the N type thin layer, but the requirement of N impurities concentration distribution is different with the foregoing description.
Owing to can make the impurity concentration in P type and the N type semiconductor thin layer have a kind of impurity concentration at least, can improve the uniformity of device reverse breakdown voltage and the reliability of device along being uneven perpendicular to the distribution on the direction of N+ silicon substrate.
More than through specific embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.
Claims (14)
1. super junction-semiconductor device; On the N+ silicon substrate, have P type and the N type semiconductor laminate structure alternately arranged; It is characterized in that: p type impurity concentration changes perpendicular to N+ silicon substrate direction on the edge; The concentration that is distributed in impurity concentration near the part of P/N semiconductor lamella upper surface required p type impurity when being higher than charge balance of p type impurity, the concentration of required p type impurity when being lower than charge balance near the impurity concentration of the part of P/N semiconductor lamella lower surface; Near the Cmax variable gradient of the part of P/N semiconductor lamella lower surface greater than Cmax variable gradient near the part of P/N semiconductor lamella upper surface.
2. device as claimed in claim 1; It is characterized in that: the p type impurity concentration of P/N semiconductor lamella mid portion can be also can not changing of changing; When the p type impurity concentration of centre part be change the time, near the Cmax variable gradient of P/N semiconductor lamella bottom surface section Cmax variable gradient greater than the p type impurity of mid portion.
3. device as claimed in claim 1 is characterized in that: said being meant from upper surface near upper surface portion played the part that the degree of depth is less than total p type impurity degree of depth 1/4; Said being meant from lower surface near bottom surface section played the part that the degree of depth is less than total p type impurity degree of depth 1/4; Said mid portion is meant in the p type impurity above-mentioned near upper surface portion with near the part between the bottom surface section.
4. device as claimed in claim 1 is characterized in that: the width of P type semiconductor thin layer is less than or equal to the width of N type semiconductor thin layer.
5. the manufacture method of a super junction-semiconductor device forms P type and the N type semiconductor thin layer of alternately arranging on the N+ silicon substrate, it is characterized in that:
85% of p type impurity concentration when the P type semiconductor thin layer impurity concentration of bottom ground floor is lower than the N type semiconductor thin layer impurity concentration that makes same horizontal level and reaches optimum balance; 105% of p type impurity concentration when the P type semiconductor thin layer impurity concentration of the bottom second layer equals to make the N type semiconductor thin layer impurity concentration of same horizontal level to reach optimum balance; 115% of P type semiconductor thin layer impurity concentration when the P type semiconductor thin layer impurity concentration of top ground floor equals to make the N type semiconductor thin layer impurity concentration of same horizontal level to reach optimum balance; P type impurity concentration when the P type semiconductor thin layer impurity concentration of the top second layer equals to make the N type semiconductor thin layer impurity concentration of same horizontal level to reach optimum balance.
6. manufacture method as claimed in claim 5 is characterized in that: the 90%-110% of the P type semiconductor thin layer impurity concentration when the P type semiconductor thin layer impurity concentration in intermediate layer equals to make the N type impurity concentration of same horizontal level to reach optimum balance.
7. manufacture method as claimed in claim 5 is characterized in that, said P type of alternately arranging and N type semiconductor thin layer adopt following method to obtain:
Step 1, on the N+ silicon substrate growth regulation one deck N-epitaxial loayer;
Step 2, the P type semiconductor coating region that utilizes photoetching to open will to inject carry out P type ion and inject;
Step 3, repetition above-mentioned steps needing to obtain the P type and the N type semiconductor thin layer alternately arranged of thickness.
8. manufacture method as claimed in claim 7 is characterized in that: the N-of ground floor described in step 1 epitaxial loayer can be grown on the said N+ silicon substrate, also can be grown on the N-epitaxial buffer layer that is positioned on the N+ silicon substrate.
9. manufacture method as claimed in claim 5 is characterized in that, said P type of alternately arranging and N type semiconductor thin layer adopt following method to obtain:
Step 1, the N-epitaxial loayer of on the N+ silicon substrate, growing form deielectric-coating again on this N-epitaxial loayer, utilize chemical wet etching to form groove;
Step 2, in said groove, fill P type silicon, or P type silicon adds medium, or P type silicon adds plain silicon, and fill up this groove, form the P type semiconductor thin layer;
Step 3, utilize back and carve or cmp is removed the P type semiconductor thin layer and the deielectric-coating of said flute surfaces.
10. manufacture method as claimed in claim 9 is characterized in that: the type of P described in the step 2 silicon, the temperature of growth are 650 ℃-1200 ℃.
11. manufacture method as claimed in claim 9 is characterized in that: the type of P described in the step 2 silicon is monocrystalline silicon, polysilicon or unformed silicon.
12. manufacture method as claimed in claim 9 is characterized in that: the sidewall of groove described in the step 1 can be vertical, also can tilt.
13. manufacture method as claimed in claim 9 is characterized in that: the bottom of groove described in the step 1 can be smooth, also crooked radian can be arranged.
14. manufacture method as claimed in claim 9 is characterized in that: groove described in the step 1 can penetrate said N-epitaxial loayer, also can be parked in the N-epitaxial loayer.
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| CN102760647A (en) * | 2012-07-26 | 2012-10-31 | 上海宏力半导体制造有限公司 | Superstructure power device manufacturing method and semiconductor device manufacturing method |
| CN103050523A (en) * | 2012-12-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN104733535A (en) * | 2015-03-17 | 2015-06-24 | 北京中科新微特科技开发股份有限公司 | Power MOSFET |
| CN105097932A (en) * | 2014-12-26 | 2015-11-25 | 杭州士兰微电子股份有限公司 | High-voltage power device and forming method thereof |
| CN106158642A (en) * | 2015-04-08 | 2016-11-23 | 北大方正集团有限公司 | The manufacture method of MOSFET element and MOSFET element |
| CN112117330A (en) * | 2020-09-21 | 2020-12-22 | 南京华瑞微集成电路有限公司 | A device structure and process method for improving the withstand voltage of deep trench superjunction MOSFET |
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| US20030232477A1 (en) * | 2001-11-09 | 2003-12-18 | Gerald Deboy | High-voltage semiconductor component |
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| US20030232477A1 (en) * | 2001-11-09 | 2003-12-18 | Gerald Deboy | High-voltage semiconductor component |
| CN1494160A (en) * | 2002-09-25 | 2004-05-05 | ��ʽ���綫֥ | power semiconductor components |
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| CN102760647A (en) * | 2012-07-26 | 2012-10-31 | 上海宏力半导体制造有限公司 | Superstructure power device manufacturing method and semiconductor device manufacturing method |
| CN102760647B (en) * | 2012-07-26 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | Super junction power device manufacture method and method, semi-conductor device manufacturing method |
| CN103050523A (en) * | 2012-12-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN103050523B (en) * | 2012-12-14 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Insulated gate bipolar transistor and manufacture method thereof |
| CN105097932A (en) * | 2014-12-26 | 2015-11-25 | 杭州士兰微电子股份有限公司 | High-voltage power device and forming method thereof |
| CN105097932B (en) * | 2014-12-26 | 2019-02-26 | 杭州士兰微电子股份有限公司 | High voltage power device and forming method thereof |
| CN104733535A (en) * | 2015-03-17 | 2015-06-24 | 北京中科新微特科技开发股份有限公司 | Power MOSFET |
| CN106158642A (en) * | 2015-04-08 | 2016-11-23 | 北大方正集团有限公司 | The manufacture method of MOSFET element and MOSFET element |
| CN112117330A (en) * | 2020-09-21 | 2020-12-22 | 南京华瑞微集成电路有限公司 | A device structure and process method for improving the withstand voltage of deep trench superjunction MOSFET |
| CN112117330B (en) * | 2020-09-21 | 2024-05-07 | 南京华瑞微集成电路有限公司 | A device structure and process method for improving the withstand voltage of deep trench super junction MOSFET |
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