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CN102446974B - Finfet及其制造方法 - Google Patents

Finfet及其制造方法 Download PDF

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CN102446974B
CN102446974B CN201110307170.0A CN201110307170A CN102446974B CN 102446974 B CN102446974 B CN 102446974B CN 201110307170 A CN201110307170 A CN 201110307170A CN 102446974 B CN102446974 B CN 102446974B
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林宏达
傅竹韵
黄信烨
杨淑婷
陈宏铭
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Mosaid Technologies Inc
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Abstract

本公开关于一种鳍片场效应晶体管(FinFET)。FinFET的示例性结构包括具有顶面的基板；在基板顶面上并具有锥形顶面的第一绝缘区域和第二绝缘区域；延伸在第一和第二绝缘区域之间的基板顶面上的基板的鳍片，其中鳍片包括凹陷部分，其具有低于第一和第二绝缘区域的锥形顶面的顶面，其中鳍片包括非凹陷部分，其具有高于所述锥形顶面的顶面；和在所述鳍片的非凹陷部分上的栅极堆叠。

Description

FINFET及其制造方法
技术领域
本发明涉及集成电路制造，更具体地说是涉及鳍片场效应晶体管。
背景技术
由于在追求高器件密度、高性能和低成本中半导体工业已经进步到纳米技术工艺节点，来自制造和设计方面的挑战已经导致了三维设计如鳍片场效应晶体管(FinFET)的发展。使用从通过如蚀刻掉一部分硅层而形成的基板延伸的薄垂直“鳍片”(或鳍片结构)制造典型的FinFET。将FinFET的沟道形成在所述垂直的鳍片中。将栅极提供在所述鳍片的上方(或缠绕)。沟道的两侧都具有栅极使得栅极从两侧控制沟道。另外，在FinFET的凹陷源极/漏极(S/D)部分中的，利用选择性生长硅锗(SiGe)的应变材料可用于提高载体迁移率。
然而，在互补金属-氧化物-半导体(CMOS)的制造中实现这些部件和工艺有挑战。例如，应变材料的非均匀分布导致施加到FinFET的沟道区域上的应力的非均匀性，从而增加器件不稳定和/或器件失灵的可能性。
因此，需要的是改进的器件和制造应变结构的方法。
发明内容
在一个实施例中，鳍片场效应晶体管(FinFET)包括含有顶面的基板；在包括锥形顶面的基板顶面上顶面的第一绝缘区域和第二绝缘区域；延伸到在第一和第二绝缘区域之间的基板顶面上方的基板鳍片，其中鳍片包括凹陷部分，所述凹陷部分具有位于第一和第二绝缘区域的锥形顶面下方的顶面，其中鳍片包括非凹陷部分，所述非凹陷部分具有高于锥形顶面的顶面；和位于鳍片的非凹陷部分上的栅极堆叠。
根据本发明所述的FinFET，其中所述锥形顶面包括平坦部分和锥形侧壁。
根据本发明所述的FinFET，其中所述平坦部分的宽度与所述第一绝缘区域的最大宽度的比率为0.05到0.95。
根据本发明所述的FinFET，其中所述锥形顶面包括弧形顶部。
根据本发明所述的FinFET，其中所述锥形顶面包括在所述锥形顶面中间的最高点。
根据本发明所述的FinFET，其中所述锥形顶面的最低点和所述基板的所述顶面的距离在约100到200nm的范围内。
根据本发明所述的FinFET，其中所述第一绝缘区域还包括在栅极堆叠下的具有平坦顶面的部分。
根据本发明所述的FinFET，其中所述锥形顶面的平坦部分的宽度小于所述平坦顶面的最大宽度。
根据本发明所述的FinFET，其中所述平坦顶面与所述锥形顶面的最高点共平面。
根据本发明所述的FinFET，其中所述平坦顶面高于所述锥形顶面的最高点。
根据本发明所述的FinFET，其中所述平坦顶面和所述锥形顶面的所述最高点之间的距离在约0.1到0.3nm的范围内。
根据本发明所述的FinFET，其中所述鳍片的非平坦部分的所述顶面和所述锥形顶面的最高点之间的距离在约100到200nm的范围内。
根据本发明所述的FinFET还包括：应变材料，在所述鳍片的所述凹陷部分上方，其中所述应变材料具有基本平坦的表面。
在又一个实施例中，制造鳍片场效应晶体管(FinFET)的方法包括提供具有第一绝缘区域和第二绝缘区域(各自具有顶面)的基板，以及位于第一和第二绝缘区域之间的鳍片，其中第一和第二绝缘区域的顶面在鳍片的顶面下方；在一部鳍片上和在一部分第一和第二绝缘区域上形成栅极堆叠；凹陷一部分未被栅极堆叠覆盖的鳍片从而形成鳍片的位于第一和第二绝缘区域的顶面下方的凹陷部分；蚀刻未被栅极堆叠覆盖的第一和第二绝缘区域的顶面的拐角从而形成第一和第二绝缘区域的锥形顶面；然后在鳍片的凹陷部分和第一以及第二绝缘区域的锥形顶面上选择性地生长应变材料。
根据本发明所述的方法，其中所述应变材料生长为具有基本平坦的表面。
根据本发明所述的方法，其中使用湿法蚀刻工艺蚀刻未被所述栅极堆叠覆盖的所述第一和第二绝缘区域的所述顶面的拐角。
根据本发明所述的方法，其中所述湿法蚀刻工艺包括在含有HF的溶液中蚀刻未被所述栅极堆叠覆盖的所述第一和第二绝缘区域的所述顶面的拐角。
根据本发明所述的方法，其中使用非偏干蚀刻工艺蚀刻未被所述栅极堆叠覆盖的所述第一和第二绝缘区域的所述顶面的拐角。
根据本发明所述的方法，其中使用CHF3作为蚀刻气体实施所述非偏干蚀刻工艺。
根据本发明所述的方法，其中使用BF3作为蚀刻气体实施所述非偏干蚀刻工艺。
以下参考附图的实施例给出了详细描述。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的数量和尺寸可以被任意增加或减少。
图1是根据本发明的各个方面，示出制造FinFET的方法的流程图；以及
图2A-图10C是根据本发明的各个实施例，示出制造的各个阶段的FinFET的透视图和横截面视图。
具体实施方式
据了解为了实施本发明的不同部件，以下公开提供了许多不同的实施例或示例。以下描述元件和布置的特定示例以简化本公开。当然这些仅仅是示例并不打算限定。例如，以下本描述中第一部件形成在第二部件上可包括其中第一部件和第二部件以直接接触形成的实施例，并且也可包括其中额外的部件形成插入到第一部件和第二部件中的实施例，使得第一部件和第二部件不直接接触。另外，本公开可在各个示例中重复参照数字和/或字母。该重复是为了简明和清楚，而且其本身没有指定所述各种实施例和/或结构之间的关系。
参照图1，示出了根据本公开的各个方面制造鳍片场效应晶体管(FinFET)的方法100的流程图。方法100开始于提供基板的步骤102。方法100的下一步是在基板中形成鳍片的步骤104。方法100继续到步骤106其中介电材料沉积到基板上，而且移除介电层的顶部部分从而形成第一和第二绝缘区域，因此第一和第二绝缘区域的顶面低于鳍片的顶面。方法100继续到步骤108其中在一部分鳍片上和一部分第一和第二绝缘区域上形成栅极堆叠。方法100继续到步骤110其中凹陷一部分未被栅极堆叠覆盖的鳍片从而形成鳍片的位于第一和第二绝缘区域的顶面下方的凹陷部分。方法100继续到步骤112，其中蚀刻未被栅极堆叠覆盖的第一和第二绝缘区域的顶面的拐角从而形成第一和第二绝缘区域的锥形顶面。方法100继续到步骤114其中在鳍片的凹陷区域和第一和第二绝缘区域的锥形顶面上选择性地生长应变材料。
如本公开中所使用的，FinFET200指任何基于鳍片的、多栅极晶体管。微处理器、存储单元、和/或其它集成电路(IC)中可包括FinFET200。可注意到图1的方法不生产完整的FinFET200。可使用互补金属-氧化物-半导体(CMOS)技术加工工艺制造完整的FinFET200。因此，可以理解可在图1的方法100之前，中间和之后提供额外的工艺，而且本文中只会简要地描述一些其它工艺。同样，为了更好地理解本公开的发明主旨，简化了图1到图10C。例如，虽然附图示出了FinFET200，可以理解IC可包括多个其它含有电阻器、电容器、电感器、保险丝等的器件。
参考图2A-图10C，示出了根据本发明的各个实施例的在制造的各个阶段的FinFET200的各个透视图和横截面视图。
图2A为根据实施例的处于制造的各个阶段之一上的具有基板202的FinFET200的透视图，且图2B为沿着图2A的线a-a取的FinFET的横截面视图。在一个实施例中，基板202包括晶体硅基板(如晶圆)。取决于设计需求(如p-型基板或n-型基板)基板202可包括各种掺杂区域。在一些实施例中，可使用p-型或n-型掺杂剂掺杂所述掺杂区域。例如，可使用p-型掺杂剂如硼或BF2；n-型掺杂剂如磷或砷；和/或其组合掺杂所述掺杂区域。可为n-型FinFET配置掺杂区域，或可替换地为p-型FinFET配置。
在一些可替换的实施例中，可由一些其它合适的元素半导体如金刚石或锗；合适的化合物半导体如砷化镓、碳化硅、砷化铟或磷化铟；或合适的合金半导体如碳锗硅、磷砷镓、或磷铟镓制造基板202。基板202还可包括为了提高性能可被应变的外延层(外延层)，和/或可包括硅上绝缘体(SOI)结构。
通过蚀刻到基板202中形成鳍片。在一个实施例中，在半导体基板202上形成焊接层204a和掩模层204b。焊接层204a可为含有氧化硅(如使用热氧化工艺形成)的薄膜。焊接层204a可作为半导体基板202和掩模层204b之间的粘结层。焊接层204a也可用作蚀刻掩模层204b的蚀刻停止层。在至少一个实施例中，掩模层204b由氮化硅形成，例如使用低压化学气相沉积(LPCVD)或等离子体增强化学气相沉积(PECVD)。在后续的光刻工艺中将掩模层204b用作硬掩模。在掩模层204b上形成光敏层206，然后图案化光敏层206，在光敏层206中形成开口208。
图3A为根据实施例的处于制造的各个阶段之一上的FinFET200的透视图，且图3B为沿着图3A的线a-a取的FinFET的横截面视图。穿过开口208蚀刻掩模层204b和焊接层204a从而暴露出下面的半导体基板202。然后蚀刻暴露的半导体基板202从而形成带有半导体基板202的顶面202s的沟槽210。半导体基板202位于沟槽210之间的部分形成半导体鳍片212。沟槽210可为互相平行的条纹(从FinFET200的顶部看)，且紧密地互相间隔。每个沟槽210具有宽度W、深度D，且通过间距S与相邻的沟道间隔分离。例如，沟槽210之间的间距S可小于约30nm。然后移除光敏层206。接着，实施清洗从而移除半导体基板202的原生氧化层。可使用稀释的氢氟酸(DHF)实施清洗。
在一些实施例中，沟槽210的深度D可在约2100埃到约2500埃的范围内，而沟槽210的宽度W可在约300埃到约1500埃的范围内。在示例性实施例中，沟槽210的纵横比(D/W)大于约7.0。在一些其它实施例中，纵横比甚至可能大于8.0。在又一些实施例中，纵横比小于约7.0或在7.0和8.0之间。然而，本领域的技术人员应意识到所有描述中重复的尺寸和值都仅仅是示例而且可以改变从而适应集成电路的不同尺寸。
然后将衬底氧化物(未示出)选择性地形成在沟槽210中。在实施例中，衬底氧化物可以是具有约20埃到约500埃之间厚度的热氧化物。在一些实施例中，可使用现场水汽生成(ISSG)和类似技术形成衬底氧化物。衬底氧化物围绕沟槽210的拐角形成，其降低了电场而因此改进了所得集成电路的性能。
图4A为根据实施例的处于制造的各个阶段之一上的FinFET200的透视图，且图4B为沿着图4A的线a-a取的FinFET的横截面视图。使用介电材料214填充沟槽210。介电材料214可包括氧化硅，因此在本公开中也可称其为氧化物214。在一些实施例中，也可使用其它介电材料如氮化硅、氮氧化硅、掺杂氟硅酸盐玻璃(FSG)或低-K介电材料。在实施例中，可使用高密度等离子体(HDP)CVD工艺，使用硅烷(SiH4)和氧气(O2)作为反应前体形成氧化物214。在其它实施例中，可使用次大气压CVD(SACVD)工艺或高纵横比工艺(HARP)形成氧化物214，其中工艺气体可包括四乙氧基硅烷(TEOS)和/或臭氧(O3)。在又一个实施例中，可使用旋布电介质(SOD)工艺如氢化倍半氧硅烷(HSQ)或甲基倍半氧硅烷(MSQ)形成氧化物214。
图4A和4B示出了介电材料214沉积之后所得到的结构。然后实施化学机械抛光，接着移除掩模层204b和焊接层204a。图5A和5B示出了所得的结构。图5A为根据实施例的处于制造的各个阶段之一上的FinFET200的透视图，且图5B为沿着图5A的线a-a取的FinFET的横截面视图。在下文将沟槽210中氧化物214的剩余部分称为绝缘区域216。在至少一个实施例中，掩模层204b由氮化硅形成，可使用利用热H3PO4的湿法工艺移除掩模层204b，同时可使用稀释的HF酸移除焊接层204a(如果由氧化硅形成)。在一些可替换的实施例中，在凹陷绝缘区域216之后实施掩模层204b和焊接层204a的移除，图6A和6B示出了凹陷步骤。
CMP工艺和掩模层204b以及焊接层204a的移除产生了图5A/5B中示出的结构。如图6A和6B所示，通过蚀刻步骤凹陷绝缘区域216从而导致了凹陷218。在一个实施例中，可使用湿法蚀刻工艺例如通过将基板202下沉到氢氟酸(HF)中实施蚀刻步骤。在另一个实施例中，可使用干法蚀刻工艺实施蚀刻步骤，例如可使用CHF3或BF3作为蚀刻气体实施干法蚀刻工艺。
剩余的绝缘区域216可包括平坦的顶面216t。剩余的绝缘区域216可包括第一隔离区域216a和第二隔离区域216b。而且，半导体鳍片212的上部部分222从剩余的绝缘区域216的平坦顶面216t上方伸出，因此将其用于形成FinFETs200的沟道区域。半导体鳍片212的上部部分222可包括顶面222t和侧壁222s。半导体鳍片212的上部部分222的高度H在约15nm到约50nm的范围内。在一些实施例中，高度H大于50nm或小于15nm。为了简化，在下文中将位于第一和第二绝缘区域216a、216b之间的半导体鳍片212的上部部分222称为沟道鳍片222a从而示出半导体鳍片212的每个上部部分，其中第一和第二绝缘区域216a、216b的平坦顶面216t低于半导体鳍片212的顶面222t。
至此的工艺步骤已经提供了具有第一绝缘区域216a和第二绝缘区域216b(具有各自的顶面216t)的基板202，以及处于第一和第二绝缘区域216a、216b之间的鳍片212，其中第一和第二绝缘区域的顶面216t低于鳍片212的顶面222t。
图7A为根据实施例的处于制造的各个阶段之一上的FinFET200的透视图，且图7B为沿着图7A的线a-a取的FinFET的横截面视图。将栅极堆叠220形成在基板202上，形成在沟道鳍片222a的非凹陷部分的顶面222t和侧壁222s上并且延伸到第一和第二绝缘区域216a、216b的平坦顶面216t上。在一些实施例中，栅极堆叠220包括栅极介电层220a和位于栅极介电层上的栅极电极层220b。
在图7A和7B中，将栅极介电层220a形成为覆盖沟道鳍片222a的顶面222t和侧壁222s。在一些实施例中，栅极介电层220a可包括氧化硅、氮化硅、氮氧化硅或高-k电介质。高-k电介质包括金属氧化物。用于高-k电介质的金属氧化物的示例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物，和/或其混合物。在本实施例中，栅极介电层220a为具有约10到30埃厚度的高-k介电材料。可使用合适的工艺如原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)、热氧化、UV-臭氧氧化或其组合形成栅极介电层220a。栅极介电层220a还包括界面层(未示出)从而减少栅极介电层220a和沟道鳍片222a之间的损伤。
然后在栅极介电层220a上形成栅极电极层220b。在至少一个实施例中，栅极电极层220b覆盖多个半导体鳍片212的上部部分222，因此得到的FinFET200包括多个鳍片。在一些可替换的实施例中，可使用半导体鳍片212的每个上部部分222形成独立的FinFET200。在一些实施例中，栅极电极层220b可包括单层或多层结构。在本实施例中，栅极电极层220b可包括多晶硅。而且，可使用均匀或非均匀掺杂使栅极电极层220b为掺杂的多晶硅。在一些可替换的实施例中，栅极电极层220b可包括金属如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi、其它具有与基板材料兼容的逸出功的导电材料、或其组合物。在本实施例中，栅极电极层220b包括介于约30nm到约60nm范围内的厚度。可使用合适的工艺如ALD、CVD、PVD、电镀、或其组合物形成栅极电极层220b。
再参考图7A，FinFET200还包括在基板202上且沿着栅极堆叠220的边的介电层224。在一些实施例中，介电层224可包括氧化硅、氮化硅、氮氧化硅、或其它合适的材料。介电层224可包括单层或多层结构。可通过CVD、PVD、ALD、或其它合适的技术形成介电层224的疏水层。然后在介电层224上实施各向异性蚀刻从而在栅极堆叠220的两侧形成间隔224。介电层224具有约5到15nm的厚度。
图8A为根据实施例的处于制造的各个阶段之一上的FinFET200的透视图，且图8B为沿着图8A的线b-b取的FinFET的横截面视图。将半导体鳍片212上未被栅极堆叠220和间隔224覆盖的部分凹陷从而形成鳍片212的凹陷部分226，所述凹陷部分226具有低于第一和第二绝缘区域216a、216b的平坦顶面216t的顶面212r。在一个实施例中，使用一对间隔224作为硬掩模，实施偏蚀刻工艺以凹陷未被保护或被暴露的沟道鳍片222a的顶面222t从而形成半导体鳍片212的凹陷部分226。在实施例中，可在约1mTorr到1000mTorr的压力、约50W到1000W的功率、约20V到500V的偏电压、约40℃到60℃的温度下，使用蚀刻气体HBr和/或C12实施蚀刻工艺。同样，在所提供的实施例中，可以调整蚀刻工艺中使用的偏电压从而更好地控制蚀刻方向以得到半导体鳍片212的凹陷部分226的目标轮廓。
图9A为根据实施例的处于制造的各个阶段之一上的FinFET200的透视图，且图9B为沿着图9A的线b-b取的FinFET的横截面视图。半导体鳍片212的凹陷部分226形成之后，蚀刻未被栅极堆叠220覆盖的第一和第二绝缘区域216a、216b的平坦顶面216t的拐角从而形成第一和第二绝缘区域216a、216b的锥形顶面216u。在一个实施例中，可使用湿法蚀刻工艺实施蚀刻步骤，例如通过将基板202下沉到氢氟酸(HF)中。在另一个实施例中，可使用非偏干法蚀刻工艺实施蚀刻步骤，例如使用CHF3或BF3作为蚀刻气体实施干法蚀刻工艺。
在一个实施例中，第一和第二绝缘区域216a、216b的锥形顶面216u包括平坦的部分和倾斜的或斜面的侧壁(如图9A和9B中所示)。因此，锥形顶面216u的平坦部分的宽度W2小于平坦顶面216u的最大宽度W1。在一个实施例中，平坦部分的宽度W2与第一绝缘区域216a的最大宽度W3的比率为0.05到0.95。锥形顶面216u的最低点和基板202的顶面202s的距离D1在约100到200nm的范围内。
图9C为另一个FinFET200实施例的横截面视图。在图9C示出的实施例中，进一步移除未被栅极堆叠220覆盖的第一和第二绝缘区域216a、216b的平坦顶面216t的拐角直到锥形顶面216u的平坦部分消失从而形成锥形顶部表面216u(图9C中所示)的弧形顶部。可以观察到相邻的半导体鳍片212之间的间隔具有中线228，中线228高于靠近半导体鳍片222的锥形顶面216u的弧形顶部。换句话说，锥形顶面216u包括处于圆锥形顶面216u中间的最高点P。而且，锥形顶面216u的最低点和基板202的顶面202s的距离D2在约100到200nm之间。在一个实施例中，平坦顶面216t与锥形顶面216u的最高点P共平面。在另一个实施例中，平坦顶面216t高于平坦顶面216u的最高点P。平坦顶面216t和锥形顶面216u的最高点P之间的距离D3在约0.1到0.3nm的范围内。在又一个实施例中，半导体鳍片212还包括在栅极堆叠220下方具有比锥形顶面216u高的顶面222t的非凹陷部分。半导体鳍片212的非凹陷部分的顶面222t和锥形顶面216u的最高点P之间的距离D4在约100到200nm的范围内。
图10A为根据实施例的处于制造的各个阶段之一上的FinFET200的透视图，且图10B为沿着图10A的线b-b取的FinFET的横截面视图。图10C为另一个具有形成在图9C所示结构上的应变材料230的FinFET200实施例的横截面视图。然后，通过选择性地在半导体鳍片212的凹陷部分226上生长应变材料230以及延伸到第一和第二绝缘区域216a、216b的锥形顶面216u上产生图10A、10Ba和10C所示的结构。由于应变材料230的晶格常数与基板202不同，因此拉紧或压缩半导体鳍片212的沟道区域以实现器件的载体迁移率和提高器件性能。在至少一个实施例中，通过LPCVD工艺外延生长应变材料230如碳化硅(SiC)从而形成n-型FinFET的源极和漏极区域。在约400到800℃的温度，约1到200Torr的压力下，使用Si3H8和SiH3CH作为反应气体实施LPCVD工艺。在至少另一个实施例中，通过LPCVD工艺外延增长应变材料230如锗硅(SiGe)从而形成p-型FinFET的源极和漏极区域。在约400到800℃的温度，约1到200Torr的压力下，使用SiH4和GeH4作为反应气体实施LPCVD工艺。
在本实施例中，应变材料230的选择性增长继续直到材料230在基板202的表面202a的上方垂直延伸的距离介于10到100nm之间且横向延伸在第一和第二绝缘区域216a、216b的锥形顶面216u上。应该注意到第一和第二绝缘区域216a、216b的锥形顶面216u使得增长前体在应变材料230从半导体鳍片212的不同凹陷部分226选择性增长期间更容易接触到增长表面从而消除合并的应变材料230下方的空隙。在一些实施例中，合并的应变材料230下方的空隙降低了应变材料230的应变效率，如带有空隙的应变材料230向FinFEt的沟道区域中提供的应力比应变材料230中未形成空隙的结构少，从而增加了期间不稳定和/或器件失灵的可能性。在本实施例中，当将从不同的凹陷部分226生长来的应变材料230合并时应变材料230具有基本平坦的表面。因此，制造FinFET200的本方法可制造空隙降低的应变结构从而提高载体迁移率和器件性能。
可以了解FinFET200可经历进一步的CMOS工艺从而形成各种部件如触点/通孔、互连金属层、介电层、钝化层等。可以观察到改进过的绝缘和应变结构提供一定数量的应力给FinFET的沟道区域，从而提高器件性能。
虽然通过示例和根据优选的实施例描述了本发明，但是应理解本发明不限于公开的实施例。相反地，本发明意图涵盖各种改进和相似的布置(对本领域的技术人员来说显而易见的)。因此，所附权利要求的范围应与最广泛的解释一致以涵盖所有这些改进和相似的布置。

Claims (20)

1.一种鳍片场效应晶体管FinFET，包括：
基板，包含顶面；
第一绝缘区域和第二绝缘区域，在所述基板顶面上且包含锥形顶表面；
所述基板的鳍片，延伸在所述第一和第二绝缘区域之间的所述基板顶面上，其中所述鳍片包括凹陷部分，所述凹陷部分的顶面低于所述第一和第二绝缘区域的所述锥形顶面，其中所述鳍片包括非凹陷部分，所述非凹陷部分的顶面高于所述锥形顶面，在所述鳍片的所述凹陷部分和所述第一和第二绝缘区域的所述锥形顶面上选择性地生长应变材料；以及
栅极堆叠，其在所述鳍片的所述非凹陷部分上。
2.根据权利要求1所述的FinFET，其中所述锥形顶面包括平坦部分和锥形侧壁。
3.根据权利要求2所述的FinFET，其中所述平坦部分的宽度与所述第一绝缘区域的最大宽度的比率为0.05到0.95。
4.根据权利要求1所述的FinFET，其中所述锥形顶面包括弧形顶部。
5.根据权利要求1所述的FinFET，其中所述锥形顶面包括在所述锥形顶面中间的最高点。
6.根据权利要求1所述的FinFET，其中所述锥形顶面的最低点和所述基板的所述顶面的距离在100到200nm的范围内。
7.根据权利要求1所述的FinFET，其中所述第一绝缘区域还包括在栅极堆叠下的具有平坦顶面的部分。
8.根据权利要求7所述的FinFET，其中所述锥形顶面的平坦部分的宽度小于所述平坦顶面的最大宽度。
9.根据权利要求7所述的FinFET，其中所述平坦顶面与所述锥形顶面的最高点共平面。
10.根据权利要求7所述的FinFET，其中所述平坦顶面高于所述锥形顶面的最高点。
11.根据权利要求10所述的FinFET，其中所述平坦顶面和所述锥形顶面的所述最高点之间的距离在0.1到0.3nm的范围内。
12.根据权利要求1所述的FinFET，其中所述鳍片的非平坦部分的所述顶面和所述锥形顶面的最高点之间的距离在100到200nm的范围内。
13.根据权利要求1所述的FinFET还包括：
应变材料，在所述鳍片的所述凹陷部分上方，其中所述应变材料具有基本平坦的表面。
14.一种制造鳍片场效应晶体管FinFET的方法，包括：
提供基板，所述基板具有分别包括顶面的第一绝缘区域和第二绝缘区域，和介于所述第一和第二绝缘区域之间的鳍片，其中所述第一和第二绝缘区域的所述顶面低于所述鳍片的顶面；
在一部分所述鳍片和一部分所述第一和第二绝缘区域上方形成栅极堆叠；
凹陷一部分未被所述栅极堆叠覆盖的所述鳍片，从而形成所述鳍片的凹陷部分，所述鳍片的凹陷部分低于所述第一和第二绝缘区域的顶面；
蚀刻未被所述栅极堆叠覆盖的所述第一和第二绝缘区域的顶面的拐角从而形成所述第一和第二绝缘区域的锥形顶面；以及
在所述鳍片的所述凹陷部分和所述第一和第二绝缘区域的所述锥形顶面上选择性地生长应变材料。
15.根据权利要求14所述的方法，其中所述应变材料生长为具有基本平坦的表面。
16.根据权利要求14所述的方法，其中使用湿法蚀刻工艺蚀刻未被所述栅极堆叠覆盖的所述第一和第二绝缘区域的所述顶面的拐角。
17.根据权利要求16所述的方法，其中所述湿法蚀刻工艺包括在含有HF的溶液中蚀刻未被所述栅极堆叠覆盖的所述第一和第二绝缘区域的所述顶面的拐角。
18.根据权利要求14所述的方法，其中使用非偏干蚀刻工艺蚀刻未被所述栅极堆叠覆盖的所述第一和第二绝缘区域的所述顶面的拐角。
19.根据权利要求18所述的方法，其中使用CHF3作为蚀刻气体实施所述非偏干蚀刻工艺。
20.根据权利要求18所述的方法，其中使用BF3作为蚀刻气体实施所述非偏干蚀刻工艺。
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