CN102122816B - Semiconductor device - Google Patents

Abstract

A semiconductor device comprising: an input/output pad; a data transfer unit including a MOS transistor whose main body is coupled to a power supply terminal VDD or a ground voltage terminal VSS, the MOS transistor responding to an individual A data transmission path is formed between the input/output pad and the internal circuit by a control signal; and a parasitic diode is arranged between the input/output pad and the power supply in parallel with the MOS transistor. between the terminal VDD or the ground voltage terminal VSS to discharge the incoming electrostatic discharge ESD.

Description

Semiconductor device

Cross References to Related Applications

This application claims priority from Korean Patent Application No. 10-2010-002161 filed Jan. 11, 2010, which is hereby incorporated by reference in its entirety.

technical field

Example embodiments of the present invention relate to semiconductor design technology, and more particularly, to an ESD circuit for protecting an internal circuit from electrostatic discharge (ESD) introduced thereinto.

Background technique

In general, an ESD circuit is provided within a semiconductor device including a display driving IC (DDI) in order to protect internal circuits from ESD. ESD refers to the phenomenon that accumulated electric charges move at high speed between objects with different electric potentials from hundreds of picoseconds (ps) to microseconds (μs). With recent advances in fabrication process technology, such ESD is so strong that it degrades internal circuits with ultra-small dimensions. Therefore, the importance of ESD circuits is often emphasized.

Meanwhile, the ESD circuit is generally disposed between a pad and an internal circuit, and includes a normal diode, a bipolar junction transistor (BJT), a grounded gate NMOS (GGNMOS), a gate coupled NMOS (GCNMOS), and the like.

For reference, a GGNMOS has a structure in which a gate, a source, and a body are coupled to a ground voltage terminal. Due to the breakdown phenomenon, the internal structure of GGNMOS operates like a BJT to generate a large amount of current. GGNMOS is quite immune to relatively long-term ESD, but weak against ESD introduced into internal circuits before the actual discharge operation. GCNMOS has a structure in which the silicide stopper layer is removed. GCNMOS is quite immune to relatively short-term ESD, but weak to relatively long-term ESD. The components of the ESD circuit are determined according to the preference reference of the circuit design.

FIG. 1 is a circuit diagram illustrating a conventional ESD circuit using a normal diode.

The input/output pad 110, the ESD circuit 120, and the internal circuit 130 are illustrated in FIG. 1 .

The ESD circuit 120 protects the internal circuit 130 from ESD introduced through the input/output pad 110 . The ESD circuit 120 includes first and second normal diodes D1 and D2 and a resistor R, the first and second normal diodes D1 and D2 are configured to transfer from the input/output pad to the power supply voltage terminal VDD or the ground voltage terminal VSS 100 introduces ESD, the resistor R is configured to reduce the ESD voltage.

The size of the first and second normal diodes D1 and D2 and the resistor R may vary according to design, but the first and second diodes D1 and D2 are generally designed to have a relatively large size. For reference, if the resistor R has a small resistance, the operation of protecting the internal circuit 130 from ESD introduced through the input/output pad 110 is degraded. If the resistor R has a large resistance, data loss may occur during data input/output operations. Therefore, it is important to design the resistors with proper dimensions.

Meanwhile, the semiconductor device is subjected to a test operation before mass production in order to test whether the internal circuit 130 is protected from ESD introduced through the input/output pad 110 during normal operation. In a test operation, generally all nodes are set in a floating state, and ESD is only applied to the nodes under test corresponding to the ESD.

In other words, when positively charged ESD is applied to the input/output pad 110 , the power supply voltage terminal VDD is set in a floating state, and the ground voltage is applied to the ground voltage terminal VSS. In this case, the positively charged ESD introduced from the input/output pad 110 is transferred to the power voltage terminal VDD through the first normal diode D1, and then released to the ground voltage terminal VSS through a power clamp. Such a discharge operation is also performed in normal operation, and the internal circuit 130 is protected from ESD by the above-described operation of the ESD circuit 120 .

As technology advances, semiconductor devices have been reduced in size. Size reduction is a factor that can maintain dominance in price competition. However, size reduction has reached a limit in recent years. The ESD circuit 120 must include first and second diodes D1 and D2 and a resistor R in order to protect the internal circuit 130 from ESD, and it is difficult to reduce the size of each element.

Contents of the invention

One embodiment of the present invention relates to a semiconductor device in which an internal circuit can replace an existing ESD circuit.

According to an embodiment of the present invention, a semiconductor device includes: an input/output pad; a data transfer unit, the data transfer unit includes a MOS transistor, the main body of the MOS transistor is coupled to a power supply terminal VDD or a ground voltage terminal VSS, The MOS transistor forms a data transfer path between the input/output pad and an internal circuit in response to an individual control signal; and a parasitic diode arranged in parallel with the MOS transistor at the input/output pad Between the output pad and the power supply terminal VDD or the ground voltage terminal VSS to discharge the incoming electrostatic discharge ESD.

According to another embodiment of the present invention, a semiconductor device includes: an input/output pad; a normal MOS transistor configured to form a data transfer path between the input/output pad and an internal circuit in response to a control signal; and a virtual A MOS transistor configured to form a parasitic diode between the input/output pad and its power supply terminal to discharge introduced ESD.

According to still another embodiment of the present invention, a semiconductor device includes: an input/output pad; first and second normal MOS transistors configured to form data between the input/output pad and an internal circuit in response to a control signal. a transfer path; and first and second dummy MOS transistors arranged correspondingly to the first and second normal MOS transistors, respectively, and configured to form a parasitic diode between the input/output pad and its power supply terminal, so as to introduce positively charged ESD and negatively charged ESD discharges of the input/output pads described above.

Description of drawings

FIG. 1 is a circuit diagram illustrating a conventional ESD circuit.

FIG. 2 is a circuit diagram illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a layout diagram illustrating a circuit layout of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a semiconductor device according to another embodiment of the present invention.

FIG. 5 is a plan view illustrating the semiconductor device of FIG. 4 from a process point of view.

detailed description

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, like numerals refer to like parts in the various figures and embodiments of the invention.

FIG. 2 is a circuit diagram illustrating a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2 , the semiconductor device includes an input/output pad 210 and a data transfer unit 220 . The data transfer unit 220 is included in the internal circuit.

The I/O pad 210 receives or outputs data during normal operation, and ESD may be introduced through the I/O pad 210 . The data transfer unit 220 forms a data transfer path between the input/output pad 210 and an internal circuit in response to the control signals CTR and /CTR during normal operation. The data transfer unit 220 includes a first MOS transistor TR1 and a second MOS transistor TR2. The first MOS transistor TR1 may be a PMOS transistor forming a source-drain path in response to a control signal /CTR and having a body coupled to a power supply voltage terminal VDD. The second MOS transistor TR2 may be an NMOS transistor forming a source-drain path in response to the control signal CTR and having a body coupled to the ground voltage terminal VSS.

Meanwhile, the data transfer unit 220 according to an embodiment of the present invention may perform a discharge operation on ESD introduced from the input/output pad 210 .

As can be seen from FIG. 2, the first parasitic diode PR_D1 is formed between the input/output pad 210 and the body of the first MOS transistor TR1, and the second parasitic diode PR_D2 is formed between the input/output pad 210 and the body of the second MOS transistor TR2. between subjects. It is thus possible to guarantee discharge operation against undesired ESD introduced during normal operation and pseudo ESD introduced during test operation.

For example, when positively charged ESD is applied to the input/output pad 210 during a test operation, the power supply voltage terminal VDD is set in a floating state, and a ground voltage is applied to the ground voltage terminal VSS. In this case, ESD input from the input/output pad 210 is transferred to the power voltage terminal VDD through the first parasitic diode PR_D1, and then released to the ground voltage terminal VSS through the power clamp (not shown). This means that the internal circuits are protected from ESD. When negatively charged ESD is applied, a discharge operation is performed through the second parasitic diode PR_D2. Thus, the output signal OUT of the data transfer unit 220 is not affected by the positively charged ESD and the negatively charged ESD.

FIG. 3 is a layout diagram illustrating a circuit layout of the semiconductor device according to the embodiment of the present invention.

Referring to FIG. 3 , a semiconductor device may be divided into a peripheral area 310 and a core area 320 . The data transfer unit 220 may be disposed in a region 330 adjacent to the input/output pad 210 . Such an arrangement makes it possible for the data transfer unit 220 to protect the input/output pad 210 from ESD. When the data transfer unit 220 is arranged adjacent to the input/output pad 210 , the data transfer unit 220 may more efficiently perform a discharge operation.

Referring again to FIG. 2 , the size of the first and second parasitic diodes PR_D1 and PR_D2 may be large for more efficient operation when ESD is introduced. The size of the first and second parasitic diodes PR_D1 and PR_D2 may vary according to the design of the first and second MOS transistors TR1 and TR2. Another circuit configuration will be described with reference to FIGS. 4 and 5 .

FIG. 4 is a circuit diagram illustrating a semiconductor device according to another embodiment of the present invention. For convenience, a circuit configuration corresponding to the second MOS transistor TR2 of FIG. 2 will be representatively described, and the input/output pad 210 and the output signal OUT of FIG. 2 are also used in FIG. 4 .

A dummy MOS transistor 420 and a normal MOS transistor 410 corresponding to the second MOS transistor TR2 of FIG. 2 are illustrated in FIG. 4 .

The normal MOS transistor 410 forms a data transmission path between the input/output pad 210 and the internal circuit in response to the control signal CTR, and transmits the output signal OUT of the normal MOS transistor 410 to the internal circuit.

The dummy MOS transistor 420 forms a parasitic diode between the input/output pad 210 and the ground voltage terminal VSS, thereby releasing ESD introduced from the input/output pad 210 . The dummy MOS transistor 420 may be implemented with a plurality of NMOS transistors NM1, NM2, and NM3. In this case, the gates of the NMOS transistors NM1 , NM2 and NM3 are coupled together, and the bodies of the NMOS transistors NM1 , NM2 and NM3 are coupled to the ground voltage terminal VSS. The gates coupled together may be coupled to a ground voltage terminal VSS.

As can be seen from FIG. 4 , parasitic diodes 425 indicated by dotted lines are formed between the bodies of the NMOS transistors NM1 , NM2 , and NM3 and the input/output pad 210 . Therefore, the semiconductor device according to an embodiment of the present invention releases undesired ESD introduced during normal operation and false ESD introduced during test operation by using these parasitic diodes.

As described above, a circuit configuration corresponding to the second MOS transistor TR2 of FIG. 2 is illustrated in FIG. 4 . Since the circuit configuration corresponding to the first MOS transistor TR1 is similar to that of FIG. 4 , a detailed description thereof will be omitted. The parasitic diode formed in the dummy MOS transistor corresponding to the first MOS transistor TR1 may discharge negatively charged ESD.

For reference, in the case of the normal MOS transistor 410 of FIG. 4, the body is not coupled to the ground voltage terminal VSS. However it may vary according to design. A parasitic diode formed in the dummy MOS transistor 420 is similarly formed in the normal MOS transistor 410 in a case where the body of the normal MOS transistor 410 is coupled to the ground voltage terminal VSS. In this case, the MOS transistor and the dummy MOS transistor may have substantially the same body area. This will act as a factor that can increase the size of the overall parasitic diode.

FIG. 5 is a plan view illustrating the circuit of FIG. 4 from a process point of view.

A normal MOS transistor and a dummy MOS transistor are illustrated in FIG. 5 . The gates of the dummy MOS transistors are coupled together, and the region 510 coupled to the input/output pad 210 is in contact with the body region 520 . The normal MOS transistor and the dummy MOS transistor have the same body region 520 , and the guard ring region 530 surrounds the body region 520 . A parasitic diode 525 indicated by a dotted line is formed between the body of the dummy NMOS transistor and the input/output pad. Therefore, the semiconductor device according to an embodiment of the present invention releases undesired ESD introduced during normal operation and pseudo ESD introduced during test operation by using these parasitic diodes.

A semiconductor device according to an embodiment of the present invention may form a parasitic diode (indicated by a dotted line) between the body region 520 and the guard ring region 530 . Accordingly, the body region 520 and the guard ring region 530 have complementary conductivity types. In addition, the body region 520 and the guard ring region 530 may be spaced apart from each other by a predetermined distance.

Meanwhile, the size of the parasitic diode can be increased by increasing the area of the junction region of the normal transistor. However, the case where the dummy gate is formed on the increased junction region can obtain an effect of increasing the magnitude of the breakdown voltage of the junction region when ESD is introduced, compared to the case where the area of the junction region is increased.

As described above, a semiconductor device according to an embodiment of the present invention performs a discharge operation by using an internal circuit instead of an existing ESD circuit, thereby reducing the area occupied by the existing ESD circuit. In addition, the size of the data transfer unit used to form the parasitic diode can be large in order to achieve efficient operation. For this purpose, dummy MOS transistors are used in this embodiment. When a dummy MOS transistor according to an embodiment of the present invention is applied to a DDI chip, the area gain can be increased by approximately 30% compared to the size of an existing ESD circuit.

The area of a semiconductor device can be reduced by using an internal circuit as an ESD circuit. Also, the price competitiveness of semiconductor devices can be improved.

Although the present invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims.

Furthermore, the locations and types of logic gates and transistors set forth above may be implemented differently depending on the polarity of the input signal.

Claims (24)

1. A semiconductor device, comprising: I/O pads; a data transfer unit comprising a MOS transistor whose body is coupled to a power supply terminal VDD or a ground voltage terminal VSS, the MOS transistor forming a data transfer path in response to a separate control signal; and a parasitic diode arranged in parallel with the MOS transistor between the input/output pad and the power supply terminal VDD or the ground voltage terminal VSS to discharge incoming electrostatic discharge ESD, Wherein, the data transmission unit is included in an internal circuit. 2. The semiconductor device according to claim 1, wherein the MOS transistor forms a source-drain path corresponding to the data transfer path in response to the control signal. 3. The semiconductor device according to claim 2, wherein the parasitic diode is formed between the input/output pad and a body of the MOS transistor. 4. The semiconductor device according to claim 1, wherein the data transfer unit is arranged in a region adjacent to the input/output pad. 5. The semiconductor device according to claim 2, wherein the body region and the guard ring region of the MOS transistor are separated from each other by a predetermined distance. 6. The semiconductor device according to claim 5, wherein the body region and the guard ring region have complementary conductivity types. 7. A semiconductor device, comprising: I/O pads; a normal MOS transistor configured to form a data transfer path in response to a control signal; and a dummy MOS transistor unit configured to form a parasitic diode between the input/output pad and its power supply terminal to discharge introduced electrostatic discharge, wherein the dummy MOS transistor unit includes at least one dummy MOS transistor, Wherein, the normal MOS transistor and the dummy MOS transistor are included in an internal circuit. 8. The semiconductor device according to claim 7, wherein the normal MOS transistor and the dummy MOS transistor have the same body region. 9. The semiconductor device according to claim 7, wherein the dummy MOS transistor comprises a plurality of MOS transistors having gates coupled together and bodies coupled to the power supply terminal. 10. The semiconductor device according to claim 9, wherein the parasitic diode is formed between the input/output pad and a body of the normal MOS transistor. 11. The semiconductor device according to claim 9, wherein the parasitic diode is formed between the input/output pad and a body of the dummy MOS transistor. 12. The semiconductor device according to claim 7, wherein the normal MOS transistor includes a MOS transistor configured to form a source-drain path corresponding to the data transfer path in response to the control signal, the MOS transistor The body of the transistor is coupled to the power supply terminal. 13. The semiconductor device according to claim 12, wherein the parasitic diode is formed between the input/output pad and a body of the normal MOS transistor. 14. The semiconductor device according to claim 12, wherein the parasitic diode is formed between the input/output pad and a body of the dummy MOS transistor. 15. The semiconductor device according to claim 7, wherein the normal MOS transistor and the dummy MOS transistor are arranged in a region adjacent to the input/output pad. 16. The semiconductor device according to claim 7, wherein body regions and guard ring regions of the normal MOS transistor and the dummy MOS transistor cells are separated from each other by a predetermined distance. 17. The semiconductor device of claim 16, wherein the body region and the guard ring region have complementary conductivity types. 18. A semiconductor device comprising: I/O pads; first and second normal MOS transistors configured to form a data transfer path in response to a control signal; and First and second dummy MOS transistors are respectively arranged corresponding to the first and second normal MOS transistors, and are configured to form a parasitic diode between the input/output pad and its power supply terminal, so as to positively charged ESD and negatively charged ESD discharges of the input/output pads described above, Wherein, the first and second normal MOS transistors and the first and second dummy MOS transistors are included in an internal circuit. 19. The semiconductor device according to claim 18, wherein the first normal MOS transistor and the first dummy MOS transistor have the same body region, and the second normal MOS transistor and the second dummy MOS transistor have the same body area. 20. The semiconductor device according to claim 18, wherein each of said first and second dummy MOS transistors comprises a plurality of MOS transistors having gates coupled together and coupled to the main body of the power terminal. 21. The semiconductor device according to claim 20, wherein the parasitic diode is formed between the input/output pad and a body of the MOS transistor. 22. The semiconductor device according to claim 18, wherein each of the first and second normal MOS transistors includes a source- a drain path MOS transistor, the body of which is coupled to the supply terminal. 23. The semiconductor device according to claim 22, wherein the parasitic diode is formed between the input/output pad and a body of the MOS transistor. 24. The semiconductor device according to claim 18, wherein the first and second normal MOS transistors and the first and second dummy MOS transistors are arranged adjacent to the input/output pad.