CN102104009B - A method for manufacturing a three-dimensional silicon-based capacitor - Google Patents

Abstract

The invention discloses a method for manufacturing high-density three-dimensional silicon-based stacked capacitors by using semiconductor PN junction capacitance and through-silicon via technology, including: using mature deep reactive ion etching, deposition, bonding and other microelectronic processing techniques, By etching the single-layer silicon-based capacitor chip, a large aspect ratio via hole is formed, and copper is deposited to make gold bumps, and the same multi-layer silicon-based capacitor is aligned and bonded to form a multi-layer Stacked three-dimensional silicon-based capacitors. This capacitor can replace traditional chip capacitors and be used in high-frequency and high-speed circuits. It is characterized by simple structure, large capacitance, adjustable capacitance, and compatibility with existing microelectronic technology.

Description

A method for manufacturing a three-dimensional silicon-based capacitor

technical field

The invention relates to the technical field of microelectronic devices, in particular to a method for manufacturing a three-dimensional silicon-based stacked capacitor using semiconductor PN junction capacitance and through-silicon vias (TSV through silicon vias) technology. Compared with a single-layer semiconductor junction capacitor, the capacitor It has the characteristics of large unit capacitance and can be used in medium and high frequency decoupling and other occasions.

Background technique

With the development of people's requirements for electronic products in the direction of miniaturization, multi-function, and environmental protection, people strive to make electronic systems smaller and smaller, with higher integration, more functions, and stronger . Thereby many new technologies, new materials and new designs have been produced, such as stacked chip packaging technology and technologies such as System-in-Package SiP (System-in-Package SiP, System-on-Package SoP) closely related to the present invention are exactly these technologies typical representative. The former is referred to as 3D packaging technology, which refers to the packaging technology of stacking two or more chips in the same package in the vertical direction without changing the size of the package. It originated from the flash memory (NOR/NAND) and SDRAM. package-on-package. And TSV is one of the key technologies in realizing 3D packaging. This is due to the fact that TSV, compared with traditional interconnection methods, can realize full-silicon packaging, is compatible with semiconductor CMOS technology, and can increase the density of components in proportion, reduce the problem of interconnection delay, and achieve high-speed interconnection. The integration technology of capacitors is an essential technology to realize SOP. This kind of integrated capacitor is generally connected between the power supply and the ground in the power supply network in the electronic system. Using the principle that the higher the frequency of the capacitor, the smaller the impedance, the high-frequency noise in the power supply network is reduced, thereby reducing the noise in the power supply network. to inhibition. 3D technology can be used for passive device integration IPD (Integration Passive Devices), the bare chip of the passive device is like the active chip, through the process of etching, punching and stacking, etc., the device is stacked to achieve higher performance of the device, which is applied to wider field.

Silicon substrate micro-vias have their unique features: 1) The diameter of the silicon substrate via hole is much smaller than that of the printed circuit board; 2) The aspect ratio of the silicon substrate via hole is much larger than the depth and width of the printed circuit board via hole Ratio; 3) The density of silicon substrate through holes is much greater than that of printed circuit board through holes. Based on the above characteristics, the processing of micro-vias on silicon substrates is different from traditional through-hole processing methods, so its research plays an extremely important role in the development of MEMS and semiconductor technology.

In practical applications, due to the inherent parasitic inductance and resistance of capacitors, it is impossible for any kind of capacitor to achieve full-band decoupling from low frequency to high frequency. Generally speaking, the larger the capacitance of the capacitor, the better the decoupling effect at low frequencies, but the larger the volume, the greater the parasitic inductance and resistance, and the worse the decoupling effect at high frequencies; the smaller the capacitance of the capacitor, The smaller the volume, the smaller the parasitic inductance and resistance, so it can be used for high frequencies, but due to the small capacitance, the decoupling effect at low frequencies is poor. Therefore, multiple capacitors with different capacitances are generally connected in parallel, large capacitance capacitors decouple low frequency components, and small capacitance capacitors decouple high frequency components. This solution is feasible when there are no restrictions on the space of the electronic system, but it is not feasible when there are strict restrictions on the space of the electronic system.

So far, based on the metal-insulator-metal (MIM) structure, especially the capacitance density of buried capacitors on silicon substrates has a typical value of 0.7~0.9nF/mm2, which is ideal for low-value applications, such as radio frequency medium impedance matching. However, due to the limitation of its small capacitance density, it is difficult to be used for problems such as decoupling under radio frequency, and it is difficult to meet the requirements of 1-100nF capacitance. The emergence of trench capacitance is to increase the effective capacitance area. For example, Wan Lixi et al. proposed a capacitor made of semiconductor PN junction capacitance. It proposes a space charge region formed at the interface between the semiconductor P region and N region. It has unique capacitive properties, and at the same time, the silicon base is engraved to increase the effective area of the capacitor to increase the capacitance, which is used for intermediate frequency decoupling, but the requirements for capacitance are still limited.

Taiwan ProMOS Technology Co., Ltd. Li Yuechuan et al. in "Forming Trench Capacitors on Substrates and Trench Capacitors" and Winbond Electronics Co., Ltd. Shi Bencheng in "Semiconductor Devices Containing Trench Capacitors and Their Manufacturing Methods" There is also a detailed description of the manufacturing process of the MIM structure trench capacitor. Leonard et al. from the University of Arkansas even made the capacitor into a MIMIMI...M structure.

The invention introduces the three-dimensional stacking concept of chips into the three-dimensional stacking of passive devices, utilizes the key technology of 3D packaging, etches micro through-silicon holes on the PN junction multi-groove channel capacitor with silicon as the base material, and stacks them in multiple layers Parallel connection is realized to achieve large capacitance density on the silicon base while reducing the required process and enhancing its high-frequency performance. This process is also in line with the new concept of all-silicon packaging. For the designed and manufactured channel capacitors with a capacitance density greater than 2nF/ ^mm2 at 2.5GHz, theoretically, the capacitance density of stacked ten layers can reach 20nF/ ^mm2 , so that the capacitor of the present invention can be used for decoupling in a wide range of medium and high frequencies .

Contents of the invention

(1) Technical problems to be solved

The purpose of the present invention is to provide a method for manufacturing a three-dimensional silicon-based capacitor, and propose a concept of integrated capacitor. Through the TSV technology, the capacitors made of silicon are stacked and interconnected in multiple layers, so that the capacitors between the layers are connected in parallel, so as to increase the capacitance per unit two-dimensional area.

(2) Technical solutions

In order to achieve the above object, the present invention provides a method for manufacturing a three-dimensional silicon-based capacitor, comprising the following steps:

Fabricate a PN junction on a silicon wafer to form a semiconductor junction capacitance, and use the junction capacitance as a basic unit to stack a three-dimensional capacitor;

Thinning of silicon wafers;

Deposit a barrier layer on the back of the thinned silicon wafer, which also serves as an etching stop layer;

The silicon wafer is reversed, and through holes are formed on the silicon wafer by deep reactive ion etching or laser etching;

Copy the pattern of the mask layer, and form a layer of SiO ₂ on the surface of the through hole as a physical protection layer and an electrical insulation layer;

Deposit copper into the through hole through electrochemical reaction to make the electrical connection of the through hole complete;

Use chemical mechanical polishing and etching to remove excess copper and make the surface flat;

The silicon wafer is then reversed, the barrier layer is removed by wet etching to expose the through hole, and polished again;

Make bumps on the copper surface filled with through-silicon holes, and align and bond multiple layers of the same capacitor chips to realize the connection between the through-holes of each layer;

The bonded silicon chip is placed on the silicon substrate, and then plastic packaging, cutting and testing procedures are performed to complete the production of the entire capacitor.

In the above scheme, the step of thinning the silicon wafer includes: thinning the silicon wafer to a certain thickness, the value of which depends on whether the junction capacitance has a vertical structure, and if there is a vertical structure, the thickness should exceed the vertical structure; if there is no vertical structure structure, the thickness should be as small as possible.

In the above solution, the formation of a layer of SiO ₂ on the surface of the through hole is to grow SiO ₂ on the surface of the through hole by PECVD or thermal oxidation.

In the above solution, the electrochemical reaction to deposit copper into the through hole is to fill the through hole with copper by electroplating or other methods.

In the above solution, the forming of bumps on the copper surface filled with through-silicon vias is to perform polishing treatment on both sides of each layer of silicon wafers, and to form bumps at the positions of the through-holes.

In the above solution, the bonded silicon wafers are placed on the silicon substrate, and the formed three-dimensional stacked silicon wafers are welded to the substrate in a flip-chip manner, and then plastic packaging, cutting and testing are performed to form a complete capacitor.

(3) Beneficial effects

The present invention has several advantages over conventional three-dimensional capacitors. Firstly, the present invention breaks away from the constraints of traditional MIMIM ... multi-layer "sandwich" structure to form capacitors, and integrates devices from the perspective of three-dimensional packaging. Second, the junction electricity of the PN junction is directly used as the basic unit capacitance, so that the entire capacitance is made of silicon as the base material, which is relatively cheap and has a mature process. Third, according to theoretical analysis, the capacitance density of the capacitor produced by the present invention can reach 10nF to 15nF per square millimeter, which can replace surface mount capacitors at high frequencies, and is especially important in the field of all-silicon packaging.

Description of drawings

Figure 1a is a basic schematic diagram of the result of multilayer stacking of silicon-based chips

Figure 1b is a structural cross-sectional view of the multilayer stack capacitor in application after the preparation of the present invention, wherein:

101-a chip die with silicon as the base body, which is a PN junction bare chip capacitor in the present invention;

102-silicon slides based on silicon dioxide;

103 - Filling glue for protecting laminated devices;

104 - through-silicon connection via TSV;

105-Solder ball array connected to the silicon substrate and the PCB;

106-Gold Au bumps connected to each layer of TSV;

Figure 2a to Figure 2b are cross-sectional views of the structure of capacitors formed by two different electrodes, which are schematic diagrams of bare chips for stacked multi-groove trench capacitors

201-P type low resistance silicon substrate;

202-medium layer;

203 - photoresist material;

204—n+ region formed by diffusion doping;

205-Al electrode layer.

3a to 3d are top views of the PN junction trench capacitor bare chip used in the present invention. in:

301 - the P-type electrode of the capacitor;

302 - the N-type electrode of the capacitor;

303—a channel formed by a method of etching;

304-P type low resistance silicon substrate;

304 - TSV vias in the present invention.

4a to 4g are cross-sectional views of the process of completing the multilayer stack capacitor. in:

401-The capacitor chip unit silicon wafer used for the invention;

402—is the barrier layer used for etching protection and supporting the silicon wafer in the present invention;

403-the oxide layer used as physical protection and electrical insulation in the present invention;

404-Metal copper Cu through holes for electrical connection in the present invention;

405—Gold Au bumps for connecting TSVs of various layers in the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

4a to 4g are schematic flow charts of multilayer stacked three-dimensional structure capacitors manufactured according to the present invention.

In step 1, the silicon substrate capacitor shown in FIG. 2 is used as the basic structural unit of the present invention, and the present invention selects four-time silicon wafers that distribute the basic capacitor structural unit in an array. The capacitor is fabricated and has an overall thickness of approximately 300 to 400 microns. After the capacitor is cleaned, the substrate on the back of the silicon wafer needs to be thinned to about 200 microns to facilitate the next step of etching. A barrier layer 402 needs to be thermally oxidized or deposited on the back, as shown in Figure 4a.

In step 2, as shown in FIG. 4b , deep reactive ion etching (DRIE) and laser etching are used to form TSVs with a high aspect ratio. Taking deep reactive ion etching as an example, the Bosch process can be used. The plasma gas can be a mixed gas of SF6 and C2H4, which is etched and protected at the same time. Finally, a through-silicon hole with a diameter of about 20 microns and a depth of 200 microns is formed. The position and distribution of vias on each capacitor can be seen in Figure 3d.

In step 3, as shown in FIG. 4c, a dielectric layer 403 is formed on the surface of the through hole, which is used for the mask required in the manufacturing process and the physical protection and electrical insulation of the device. Wherein the dielectric layer can be, for example, a silicon oxide layer, and its thickness can be about 2 micrometers, and the formation method is, for example, performing thermal oxidation at a temperature of 850-950 degrees Celsius or plasma-enhanced chemical vapor deposition ( PECVD) and other methods.

Step 4, as shown in FIG. 4d , deposits copper metal 404 in the through hole through electrochemical reaction. It is necessary to copy and protect the pattern on the place where copper is not required to be deposited through the mask, and then deposit copper on the entire surface of the capacitor, and use a chemical method to form a seed layer on the surface, then remove the protective pattern, and electroplate copper. A thick layer of copper is quickly electroplated on the seed layer until the entire via is filled.

In step 5, as shown in FIG. 4e , the barrier layer is removed by chemical mechanical polishing or grinding and etching. After the removal of the barrier layer is completed, copper metal on the upper and lower surfaces is required.

Step 6, as shown in FIG. 4f , make gold bumps on the lower surface of the copper metal vias.

Step 7, as shown in FIG. 4g , after aligning two capacitor chips of the same size, they are bonded together through metal to form a path for upper and lower electrical connections.

Step 8, by analogy, multiple capacitor chips can be bonded to form a stack.

Step 9, placing the device in an annealing furnace for annealing, and slicing to form corresponding small units, as shown in FIG. 4h.

In addition, if the position of the capacitor electrode is changed, the position of the TSV will also change accordingly. The present invention designs capacitors deposited at two different positions, as shown in Figure 2, the former is center-symmetric, and the latter is left-right symmetric Figures 3a to 3b also show the bottom view of the centrally symmetrical electrodes and the positions for forming TSVs, and Figures 3c to 3d show the bottom views of the left and right symmetrical electrodes and the positions for forming TSVs.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (6)

1. A method for manufacturing a three-dimensional silicon-based capacitor, comprising the following steps: Fabricate a PN junction on a silicon wafer to form a semiconductor junction capacitance, and use the junction capacitance as a basic unit to stack a three-dimensional capacitor; Thinning of silicon wafers; Deposit a barrier layer on the back of the thinned silicon wafer, which also serves as an etching stop layer; The silicon wafer is reversed, and through holes are formed on the silicon wafer by deep reactive ion etching or laser etching; Copy the pattern of the mask layer, and form a layer of SiO ₂ on the surface of the through hole as a physical protection layer and an electrical insulation layer; Deposit copper into the through hole through electrochemical reaction to make the electrical connection of the through hole complete; Use chemical mechanical polishing and etching to remove excess copper and make the surface flat; The silicon wafer is then reversed, the barrier layer is removed by wet etching to expose the through hole, and polished again; Make bumps on the copper surface filled with through-silicon holes, and align and bond multiple layers of the same capacitor chips to realize the connection between the through-holes of each layer; Install the bonded silicon chip on the silicon substrate, and then carry out plastic packaging, cutting and testing procedures to complete the production of the entire capacitor. 2. The manufacturing method of the three-dimensional silicon-based capacitor according to claim 1, wherein the step of thinning the silicon wafer comprises: Thinning the silicon wafer to a certain thickness depends on whether the junction capacitance has a vertical structure. If there is a vertical structure, the thickness should exceed the vertical structure; if there is no vertical structure, the thickness should be as small as possible. 3 . The method for manufacturing a three-dimensional silicon-based capacitor according to claim 1 , wherein the formation of a layer of SiO ₂ on the surface of the through hole is to grow SiO ₂ on the surface of the through hole by PECVD or thermal oxidation. 4 . 4 . The method for manufacturing a three-dimensional silicon-based capacitor according to claim 1 , wherein the electrochemical reaction to deposit copper into the through hole is to fill the through hole with copper by electroplating or other methods. 5. The manufacturing method of the three-dimensional silicon-based capacitor according to claim 1, wherein the making bumps on the copper surface filled in the through-silicon holes is to perform polishing treatment on both sides of each layer of silicon wafers, and to make bumps in the through-holes. location to make bumps. 6. The manufacturing method of the three-dimensional silicon-based capacitor according to claim 1, wherein the bonding silicon chip is mounted on the silicon substrate by welding the formed three-dimensional stacked silicon chip to the silicon substrate in a flip-chip welding manner. substrate, followed by molding, cutting and testing to form a complete capacitor.

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