CN102023948B - Direct interface method of USB 3.0 bus and high speed intelligent unified bus - Google Patents

Abstract

The invention discloses a direct interface method between a USB3.0 bus and a high-speed intelligent unified bus, which is used to solve the technical problem of low interconnection speed between the existing USB3.0 bus and other buses. The technical solution is to realize the analysis of the USB3.0 standard by designing the USB3.0 controller, correctly and completely receive the valid data on the USB3.0 bus, and realize the high-speed transmission and reception of the intelligent bus data through the high-speed transceiver SerDes using the fiber channel; through The high-speed buffer memory realizes the buffer storage of bidirectional data; the clock switching of different speed buses is realized through the clock control module, and the high-speed reliable and effective transmission of two kinds of bus data is realized.

Description

Direct interface method between USB3.0 bus and high-speed intelligent unified bus

technical field

The invention relates to a bus interface method, in particular to a direct interface method between a USB3.0 bus and a high-speed intelligent unified bus.

Background technique

After the USB interface technology has gone through USB1.0, USB1.1, and USB2.0, in 2008, the USB3.0 organization released the USB3.0 official standard white paper. On the basis of the previous versions, USB3.0 version has proposed more advanced standards and wider application fields. The goal of USB3.0 technology is to use the same architecture design as the existing USB to achieve a transmission speed that is more than 10 times faster than the current USB2.0 interface (its transmission rate can reach 5Gbps), and it also has the ease of use of traditional USB technology and plug-and-play functionality. The new standard optimizes the USB3.0 specification to achieve lower energy consumption and higher protocol efficiency, and supports both copper and optical fiber cables. The speed of using optical fiber connection can reach 20 times or even 30 times that of USB2.0, and its application fields include fast synchronous and instant transmission of personal computers, consumer and mobile products.

With the development of avionics systems, the integration scale of the system is getting larger and larger, and the division of labor and cooperation of each subsystem is mainly reflected in the bus interface communication and functional calculation, thus requiring massive sensor information and image information to be realized through the high-speed intelligent unified bus. It is urgently required that the USB3.0 bus and the 10 Gigabit high-speed intelligent unified bus can realize information sharing, but the current USB3.0 bus itself cannot be directly connected with the high-speed unified intelligent bus.

In the published literature, there is no literature on the interface conversion method between the USB3.0 bus and other bus forms. According to the USB protocol, USB3.0 devices can be backward compatible with USB1.0, USB1.1 and USB2.0 standards, although the data stream of the USB3.0 protocol can be converted into the USB2.0 standard, and then communicate with other devices through the USB2.0 bus The interface in the form of a bus can indirectly realize the conversion of the USB3.0 interface, but the advantage of the USB3.0 transmission speed will be greatly weakened, and the increase in the number of data turnover will definitely reduce the reliability and integrity of the transmission; It will lead to the weakening of the signal-to-noise ratio of the signal and deteriorate the sharing of information.

Contents of the invention

In order to overcome the shortcomings of the existing USB3.0 bus and other buses with low transmission rates, the present invention proposes a direct interface method between the USB3.0 bus and the high-speed intelligent unified bus. Standard analysis, correct and complete reception of valid data on the USB3.0 bus, and high-speed transceiver of the smart bus data through the high-speed transceiver SerDes using fiber optic channel; realize bidirectional data buffer storage through the high-speed buffer memory; realize through the clock control module The clock switching of buses with different rates can realize high-speed, reliable and effective transmission of two bus data.

The technical solution adopted by the present invention to solve its technical problems: a direct interface method between a USB3.0 bus and a high-speed intelligent unified bus, which is characterized in that it comprises the following steps:

(a) Based on the store-and-forward mechanism, the interconnection of two buses with different transmission rates is realized by switching the read and write clocks of the buffer. Create a transceiver cache inside the high-speed logic array, and automatically switch the read and write clocks of the transceiver cache according to the data source; manage USB 3.0 and high-speed smart bus resources by setting different priorities, and stipulate that the priority of receiving data from the bus is higher than that of writing data Priority, when data arrives on the USB3.0 bus, the status register USB3.0 flag in the bus scheduler is set to block the request to send data to the bus at this end; at this time, all data received from the high-speed transceiver SerDes will be Stored in the USB3.0 send buffer, the USB3.0 bus is idle, and the flag bit is cleared. vice versa. Thus effectively avoiding the occurrence of bus conflict and data loss.

(b) When the USB3.0 unit sends to the smart bus, the address of the part and the signal to be sent are encoded by the smart bus coding unit according to the bus coding rules, and then the sending information is sent to the two-way memory under the control of the low-frequency synchronous signal Waiting for sending; after receiving the command to send to the bus, turn off the low-frequency synchronization signal through the selection switch and turn on the high-frequency synchronization signal, and send the address and signal to the smart bus through data parallel conversion and control.

(c) The USB3.0 unit continuously and automatically receives and judges the permission to send signal from the smart bus and the address signal from other units through the high-speed logic array to determine the information required to send a signal to the bus or read USB3.0 from the bus ; If send signal to bus, then send according to the flow process of (b); If need to read bus signal, then write bidirectional memory under the control of bus synchronous signal, save required bus signal; After receiving, select switch Turn off the bus synchronization signal and turn on the low-frequency synchronization signal, send the read bus signal to the intelligent decoding unit for decoding, and store the data for use.

(d) Design frame format to realize bus ID identification, data routing, shielding reception.

(e) Large-capacity dual-port high-speed memory is used to avoid the loss of large amount of data transmitted from the high-speed intelligent bus to the USB3.0 bus, and realize the duplex operation of reading and writing to the memory; the internal modules of the high-speed logic array adopt parallel blocks and pipelines The design minimizes the delay of data transmission between the USB3.0 bus and the smart bus.

The beneficial effects of the present invention are: the interface between the USB3.0 bus and the smart bus is realized, and the effective and reliable interconnection between the USB3.0 bus and other bus forms can be realized through the smart bus interface; the priority setting of clock switching and data receiving and sending is adopted, And make full use of the characteristics of high-speed logic array parallelism and reconfigurability, realize the two-way data interaction between the low-speed USB3.0 bus and the high-speed intelligent bus, and improve the data transmission speed of the USB3.0 bus; The storage unit, parallel-to-serial conversion, selection switch and high-speed logic array use very high-frequency devices, while the rest only need devices that can meet the requirements of this unit, thereby reducing the requirements for interface hardware performance and increasing data transmission. reliability and reduce costs.

The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

Description of drawings

Fig. 1 is an interface diagram of the direct interface method between the USB3.0 bus and the high-speed intelligent unified bus of the present invention.

Fig. 2 is a communication control diagram of the bus arbitration mechanism of the present invention.

Fig. 3 is a schematic diagram of the state machine of the double-ended bus bidirectional communication of the present invention.

Fig. 4 is a flow chart of USB3.0 data transmission in the present invention.

Fig. 5 is a flow chart of USB3.0 data receiving in the present invention.

Fig. 6 is a format diagram of the intelligent bus data frame of the present invention.

Detailed ways

The present invention will be described in detail with reference to FIGS. 1 to 6 .

The invention is an interface method between a USB3.0 bus and an intelligent bus, which realizes the high-speed optical fiber transmission of the USB3.0 device through the high-speed intelligent bus and the data reception of high-speed optical fiber data based on the USB3.0 bus. The hardware structure of the invention includes a USB3.0 bus controller, an intelligent bus controller, a central bus arbitration controller and a high-speed mass memory.

In this embodiment, the scheduling and interface control of the two buses are mainly completed in the high-speed logic array FPGA, and the FPGA adopts the EP1C12 chip of the Cyclone series of Altera Corporation of the United States. The chip has a density of 12060 LE units, which can fully meet the needs of image processing algorithms and system logic control; 169 user-available I/O ports meet the system's multi-chip connection requirements for image acquisition and storage. USB3.0 protocol decoding and data frame encapsulation adopt NEC's UPD720200 chip, which is the world's first USB3.0 master chip; high-speed transceiver SerDes adopts BCM8152, which can reach 10 gigabit data sending and receiving speed; high-speed dual-port RAM Using the chip model IDT70V3079, its read and write speed can reach 4ns at the fastest. FPGA mainly performs two-way buffering and scheduling of data, bus arbitration and clock switching to realize duplex communication of the two buses, maximize the use of bus communication capabilities and avoid data loss.

The transmission rate of the USB3.0 bus is lower than that of the high-speed smart bus. The data sent from the USB3.0 is first cached in the high-speed buffer. When the buffer reaches a certain amount, the bus scheduler sends a request data transmission signal to the high-speed smart bus, and Allocate the time slice for sending data, and at the same time control the clock switching module to switch the memory synchronization clock; at this time, the high-speed intelligent bus controller sends a read buffer signal, and encodes the signal read from the buffer with the intelligent bus data frame, and the encoded data The frame is delivered to the transmit buffer of the high-speed transceiver SerDes and sent out at high speed when the clock edge arrives. The data transmitted to the high-speed transceiver SerDes through the fiber channel is also cached in the receiving buffer of the smart bus. When the bus scheduler detects the arrival of data, it performs bus arbitration. When the USB3.0 bus is idle, it immediately sends a request to send a signal. Allocate the time slice for sending data, and at the same time control the clock switching module to switch the memory reading and writing to low-speed mode; at this time, the USB3.0 controller sends a read buffer signal, and the read data is sent after being encoded by USB3.0.

This example adopts the priority-based control management method in the bus management. When there is data waiting to be sent in the buffer and data arrives at the same time, the bus arbitration mechanism will let the data send enter the waiting state, let the bus receive the data, wake up the data sending process after receiving, and resume the data sending.

The realization of the interface between the USB3.0 bus and the smart bus makes each low-speed bus connected to the smart bus exclusively enjoy the maximum bandwidth of the bus. Based on the invention, the interconnection between the USB3.0 bus and other buses can be realized, and the routing of bus data is intelligent. There are multiple low-speed bus interfaces on the smart bus, so the interconnection between USB3.0 and other buses based on the smart bus has the advantages of small size, low cost, low power consumption, and high-speed and reliable transmission.

Claims (1)

1. a direct interface method of USB3.0 bus and high-speed intelligent unified bus, it is characterized in that comprising the following steps: (a) Based on the store-and-forward mechanism, the interconnection of two buses with different transmission rates is realized through the switching of the read-write clock of the buffer; the transceiver cache is opened in the high-speed logic array, and the read-write clock of the transceiver cache is automatically switched according to the data source; through Set different priorities to manage the USB3.0 bus and high-speed intelligent unified bus resources, and stipulate that the priority of receiving data from the high-speed intelligent unified bus is higher than that of writing data. The status register USB3.0 bus flag in the bus scheduler is set to shield the request for sending data on the bus at this end; at this time, all the data received from the high-speed transceiver SerDes will be stored in the USB3.0 bus sending buffer, and the USB3. 0 The bus is idle, and the flag bit is cleared; when the USB3.0 bus sends data, the USB3.0 bus flag bit in the status register of the high-speed intelligent unified bus scheduler is set, and the request for receiving data on the bus of this end is shielded; the data to be sent All are stored in the receiving buffer of the USB3.0 bus, sent out through the high-speed transceiver SerDes, and the flag bit is cleared; thus effectively avoiding bus conflicts and data loss; (b) When the USB3.0 bus sends to the high-speed intelligent unified bus, the high-speed intelligent unified bus coding unit encodes the address of the part and the signal to be sent according to the bus coding rules, and then sends the sending information into the The two-way memory waits to be sent; after receiving the command to send to the high-speed intelligent unified bus, turn off the low-frequency synchronous signal through the selection switch and open the high-frequency synchronous signal, and send the address and signal to the high-speed intelligent unified bus through the data parallel conversion and control module; (c) The USB3.0 bus continuously and automatically receives and judges the transmission permission signal from the high-speed intelligent unified bus and the address signal from other units through the high-speed logic array, so as to determine whether to send a signal to the high-speed intelligent unified bus or to read from the high-speed intelligent unified bus The information required by the USB3.0 bus; if the signal is sent to the high-speed intelligent unified bus, it is sent according to the process of (b); if it is necessary to read the high-speed intelligent unified bus signal, it is written into the bidirectional memory under the control of the bus synchronization signal , save the required high-speed intelligent unified bus signal; after receiving, turn off the bus synchronization signal through the selection switch and open the low-frequency synchronization signal, send the read high-speed intelligent unified bus signal to the intelligent decoding unit for decoding, and store the data for use ; (d) Design frame format to realize bus ID identification, data routing, shielding reception; (e) Use large-capacity dual-port high-speed memory to avoid the situation that the high-speed intelligent unified bus transmits large amounts of data to the USB3.0 bus and loses large amounts of data, and realizes the duplex operation of reading and writing to the memory; the internal modules of the high-speed logic array adopt parallel blocks, The pipeline design minimizes the delay of data transmission between the USB3.0 bus and the high-speed intelligent unified bus.

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