CN102017418B - Systems and methods for controlling power consumption in a digital phase locked loop (DPLL) - Google Patents

Abstract

An apparatus includes a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain a same temporal relationship of triggering edges of the reference clock when switching between the distinct frequency clocks, the apparatus further includes a phase-locked loop (P LL), such as a digital phase-locked loop (DP LL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal, by maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, continuous and efficient operation of the phase-locked loop (P LL) is not significantly disturbed while the reference clock is changed, which can be used to control power consumption of the apparatus.

Description

Systems and methods for controlling power consumption in a digital phase locked loop (DPLL)

technical field

The present invention relates generally to phase locked loops (PLLs), and in particular to a system and method of controlling power consumption in a digital phase locked loop (DPLL).

Background technique

Communication devices typically include a local oscillator (LO) for synchronously transmitting signals to and receiving signals from other remote communication devices. Typically, these signals are sent or received via defined frequency channels. To select a particular frequency channel, the frequency of the LO is typically changed so that signals are properly transmitted or received via the selected channel. Typically, a phase locked loop (PLL), such as a digital phase locked loop (DPLL), is used to perform the change of the LO frequency.

A typical DPLL includes several digital devices such as an input accumulator, a low-pass filter (LPF) (often referred to as a "loop filter"), a digitally controlled oscillator (DCO), a DCO accumulator, a time-to-digital converter (TDC) and other digital devices. Some of these digital devices use a reference clock to perform their intended functions. For example, the input accumulator uses a reference clock to generate a signal indicative of the phase and frequency of the input signal to the DPLL. Also, the DCO accumulator and TDC use a reference clock to generate a signal indicative of the phase and frequency of the DCO's output signal.

The power consumption of such digital devices is usually proportional or positively related to the frequency of the reference clock. Therefore, the DPLL consumes more power when the frequency of the reference clock is relatively high, and consumes less power when the frequency of the reference clock is relatively low. Typically, communication devices using such DPLLs are portable devices that use a limited power supply (eg, batteries) for continuous operation. In order to prolong the continuous operation of such communication devices, it is preferable to have the devices operate in a low power mode whenever possible. One way this can be accomplished is by reducing the frequency of the reference clock when the communication device does not need to operate in a high performance mode.

One problem with changing the frequency of the reference clock is that it should be done without significantly affecting the loop control of the DPLL. Existing methods have been developed that allow changing the frequency of the reference clock without significantly affecting the loop control of the DPLL. However, these methods typically take a significant amount of time to perform frequency change and relock operations, which may not be acceptable in many applications.

Contents of the invention

An aspect of the invention relates to an apparatus comprising programmable frequency means adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency means is further adapted to operate at distinct frequencies The same timing relationship of the trigger edge of the reference clock is maintained when switching between clocks. The apparatus further includes a phase locked loop (PLL), such as a digital phase locked loop (DPLL), that uses a selected reference clock to establish a predetermined phase relationship between the input signal and the output signal. By maintaining substantially the same temporal relationship of the reference clocks when switching between clocks of differing frequency, the frequency of the reference clock is changed while not significantly disturbing the continuous and efficient operation of the phase locked loop (PLL). This can be used to control the power consumption of the device.

In yet another aspect of the invention, a programmable frequency device includes a source of distinct frequency clocks, which may include a chain of cascaded flip-flops adapted to be driven by an original reference clock. In yet another aspect, a programmable frequency device includes circuitry adapted to asynchronously receive an input frequency selection control signal indicative of a selection among distinct frequency clocks for a reference clock, and to synchronously generate such that at a particular time Selects the output frequency selection control signal for the reference clock. In yet another aspect, the output frequency selection control signal is generated once during a cycle of one of the distinct frequency clocks (eg, the clock with the longest period). In another aspect, the output frequency select control signal is generated in response to the distinct frequency clocks being at predetermined logic levels (eg, all high or all low).

Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

Description of drawings

1 illustrates a block diagram of an exemplary digital phase-locked loop (DPLL) in accordance with an aspect of the invention.

2 illustrates a schematic diagram of an exemplary programmable frequency device according to another aspect of the invention.

3 illustrates a timing diagram of exemplary signals generated within an exemplary programmable frequency device according to another aspect of the invention.

4 illustrates a block diagram of an exemplary communications device according to another aspect of the disclosure.

5 illustrates a flowchart of an exemplary method of controlling power consumption in an exemplary communication device according to another aspect of the disclosure.

Detailed ways

1 illustrates a block diagram of an exemplary digital phase-locked loop (DPLL) 100 in accordance with one aspect of the disclosure. In summary, the DPLL allows programmability of the frequency of the reference clock for power consumption purposes without significantly affecting the loop control of the DPLL. The DPLL performs this process by ensuring that the timing of the reference clock's trigger edge does not substantially change when the reference clock frequency changes. As previously discussed, the DPLL can be placed in a low power mode when the frequency of the reference clock is substantially reduced. Conversely, the DPLL can be placed in a high power mode when the frequency of the reference clock is substantially increased.

Specifically, a DPLL includes a programmable frequency device 102, an input accumulator 104, a first summing device 106, a low-pass filter (LPF) or loop filter 108, a digitally controlled oscillator (DCO) 110, a time-to-digital conversion device (TDC) 112 , DCO accumulator 114 , latch 116 , second summing device 118 and frequency controller 120 .

The programmable clock device 102 receives an original reference clock REF_IN and generates an output reference clock REFOUT based on input control signals ENABLE and DIVIN_<1:0>. The ENABLE signal implements the function of changing the frequency of the reference clock based on the frequency selection control signal DIVIN_<1:0>. For example, if the ENABLE signal is deactivated or not asserted, the programmable frequency device 102 only passes the raw reference signal REF_IN to its output (eg, ). On the other hand, if the ENABLE signal is activated or asserted, the programmable frequency device 102 generates an output reference clock REFOUT having a frequency related to that of the original reference clock REF_IN and based on the frequency selection control signals DIVIN_<1:0>.

For example, if DIVIN_<1:0> is 00, the programmable frequency device 102 divides the frequency of the original reference clock REF_IN by one (1) to generate the output reference clock REFOUT (eg, ). If DIVIN<1:0> is 01, the programmable frequency device 102 divides the frequency of the original reference clock REF_IN by two (2) times to generate the output reference clock REFOUT (eg, ). If DIVIN_<1:0> is 11, the programmable frequency device 102 divides the frequency of the original reference clock REF_IN by four (4) times to generate the output reference clock REFOUT (eg, ). Also, if DIVIN_<1:0> is 10, the programmable frequency device 102 divides the frequency of the original reference clock REF_IN by eight (8) times to generate the output reference clock REFOUT (eg, ).

As previously discussed, the programmable frequency device 102 performs changes in frequency in such a way that the timing or time relationship of the trigger edges does not substantially change with changes in frequency. This prevents or reduces the possibility of disruption in the loop control of DPLL 100 . The programmable frequency device 102 is also adapted to asynchronously receive an input frequency selection control signal DIVIN_<1:0>, and to synchronously generate an output frequency selection control signal that instructs other modules of the DPLL 100 with a selected frequency to output the reference clock REFOUT DIVRO_<1:0>.

The input accumulator 104 receives the PLL input and the output reference clock REFOUT, and generates an input phase signal. Essentially, the input accumulator 104 contains a counter that counts the periods of the output reference signal by a number dictated by the PLL input. For example, if the PLL input is 10, the counter counts through 10 (eg, 0, 10, 20, 30, etc.). The PLL input specifies the ratio of the frequency of the DCO output to the frequency of the output reference clock REFOUT. For example, if the frequency of the output reference clock REFOUT is 100MHz and the PLL input is 10, the frequency of the DCO output (when the loop is locked) is at about 1GHz. If the frequency selection control signal DIVRO_<1:0> is 00, the input accumulator 104 counts the period of the output reference clock REFOUT through the 1x PLL input (for example, because ). If the frequency selection control signal DIVRO_<1:0> is 01, the input accumulator 104 counts the period of the output reference clock REFOUT through the 2x PLL input (for example, because ). If the frequency selection control signal DIVRO_<1:0> is 11, the input accumulator 104 counts the period of the output reference clock REFOUT through the 4xPLL input (for example, because ). Also, if the frequency selection control signal DIVRO_<1:0> is 10, the input accumulator 104 counts the period of the output reference clock REFOUT through the 8x PLL input (for example, because ).

The first summing device 106 receives the input phase signal from the input accumulator 104 and the feedback phase signal from the second summing device 118 and generates a phase error signal indicative of a phase difference between the input phase signal and the feedback phase signal. For timing and error correction purposes, the first summing device 106 may receive the output reference clock REFOUT and the frequency selection control signal DIVRO_<1:0>. For example, the first summing device 106 may generate the phase error signal within one (1) clock cycle of the output reference clock REFOUT after it has received the phase signal from the input accumulator 104 and the second summing device 118 . Since the frequency (i.e. clock period) of the REFOUT clock can be changed by the programmable frequency means 102, the first summing means 106 receives a frequency selective control signal DIVRO_<1 for the purpose of setting an appropriate delay for outputting the phase error signal: 0> and output reference clock REFOUT.

An LPF or loop filter 108 filters the phase error signal from the first summing device 106 to generate a frequency control signal for the DCO 110 . The transfer function of the loop filter 108 may depend on the frequency of the output reference clock REFOUT. Therefore, the loop filter 108 also receives the output reference clock REFOUT and the frequency selection control signal DIVRO_<1:0> to inform the loop filter 108 of the current frequency of the reference clock REFOUT. Loop filter 108 uses this information to adjust its transfer function according to the current frequency of output reference clock REFOUT.

DCO 110 receives the frequency control signal and output reference clock REFOUT from loop filter 108 and produces a PLL output signal having a specified phase relationship to the input phase signal when the control loop is locked. DCO accumulator 114 produces a signal indicative of a rough measure of the phase of the PLL output signal. Essentially, the DCO accumulator 114 contains a counter that incrementally counts the periods of the PLL output signal. The latch 116 outputs coarse phase information in response to the trigger edge of the output reference clock REFOUT.

TDC 112 generates a signal indicative of a fine measure of the phase of the PLL output signal. In particular, TDC 112 includes a chain of delay elements that receive the PLL output signal. The outputs of the delay elements are respectively coupled to the data inputs of the flip-flops. The flip-flops are clocked by outputting a reference clock REFOUT. The Q output of the flip-flop is coupled to a thermometer decoder which produces a signal indicative of the fractional difference between the phase of the PLL output signal and the phase of the reference clock REFOUT. It should be understood that a frequency divider may be located between the output of DCO 110 and the input of DCO accumulator 114 and TDC 112 .

The second summing device 118 receives the coarse phase signal and the fine phase signal from the latch 116 and the TDC 112, respectively, and generates a feedback phase signal related to the phase of the PLL output signal. For timing and error correction purposes, the second summing device 118 may receive the output reference clock REFOUT and the frequency selection control signal DIVRO_<1:0>. For example, second summing device 118 may generate the feedback phase signal within one (1) clock cycle of output reference clock REFOUT after it has received phase information from latch 116 and TDC 112 . Since the frequency (that is, the clock period) of the output reference clock REFOUT can be changed by the programmable frequency device 102, the second summing device 118 receives the output reference clock REFOUT and the frequency selection control signal DIVRO_<1:0> to provide the second summation The sum means 118 informs the current frequency of the output reference clock REFOUT. The second summing means 106 uses this information to select an appropriate delay for outputting the feedback phase signal.

The frequency controller 120 generates the input frequency selection DIVIN_<1:0> and ENABLE control signals for the programmable frequency device 102 . Based on a specified power saving algorithm, frequency controller 120 may cause the frequency of reference clock REFOUT to be reduced by a factor of, for example, two (2), four (4), or eight (8) in order to place DPLL 100 in a specified power consumption mode middle. Frequency controller 120 can perform this reduction in the frequency of reference clock REFOUT when the DPLL does not need to operate in high performance mode, and the reduced power consumption caused by the frequency reduction will prolong the operation of the device through a limited power supply (e.g., battery) for continuous operation. When the DPLL 100 needs high performance, the frequency controller 120 can increase the frequency of the reference clock REFOUT, so that better loop control is achieved. The frequency controller 120 can also completely disable the frequency change function by deactivating or deasserting the ENABLE signal.

2 illustrates a block diagram of an exemplary programmable frequency device 200 according to another aspect of the invention. Programmable frequency device 200 is but one example of a detailed implementation of programmable frequency device 102 previously discussed. In particular, the programmable frequency device 200 is responsive to the control signal ENABLE to enable or disable the frequency division operation, and perform the appropriate frequency selection operation as specified by the input frequency selection control signal DIVIN_<1:0>. Also, as previously discussed, the programmable frequency device 200 performs frequency changes such that the timing relationship of the trigger edges (eg, rising edges) does not substantially change when switching between different frequencies of the output reference clock REFOUT. In this way, changes in the frequency of the reference clock REFOUT disturb the loop control minimally.

In particular, the programmable frequency device 200 comprises: a first AND gate 202; a chain of delay elements 204; a first inverter 206 and a second inverter 208; a plurality of D flip-flops 210, 212, 214, 218 , 220, 222, 224, 226, 228, 230, 232, 240 and 242; three input "AND" gate 234; three input "exclusive OR" (NOR) gate 236; second "AND" gate 238; multiplexer (MUX) 244; two-clock D flip-flop 246; and two-input MUX 248.

AND gate 202 includes a first input adapted to receive a raw reference clock REF_IN, and a second input adapted to receive an ENABLE control signal from frequency controller 120 . AND gate 202 includes an output coupled to an input of delay chain 204 . The delay chain 204 in turn includes an output coupled to an input of a first inverter 206 , which in turn includes an output coupled to an input of a second inverter 208 . As discussed in more detail below, three timing control signals REF_D, REF_DB, and REF_D1 are generated at the outputs of the delay chain 204, the first inverter 206, and the second inverter 208, respectively.

D flip-flop 210 includes a clock input adapted to receive a raw reference clock REF_IN, a QB output coupled to its data input, and a Q output coupled to the clock input of D flip-flop 212 . D flip-flop 212 in turn includes a QB output coupled to its data input, and a Q output coupled to the clock input of D flip-flop 214 . D flip-flop 214 includes a QB output coupled to its data input. Three cascaded flip-flops 210, 212, and 214 operate to divide the frequency of the original reference clock REF_IN to generate distinct frequency clocks DIV2, DIV4, and DIV8 at the Q outputs of D flip-flops 210, 212, and 214, respectively. . Clock DIV2 has a frequency that is substantially half the frequency of original reference clock REF_IN; clock DIV4 has a frequency that is substantially one quarter that of original reference clock REF_IN; and clock DIV8 has a frequency that is substantially half that of original reference clock REF_IN. one-eighth frequency.

D flip-flop 222 includes a data input adapted to receive clock DIV2 , a clock input to receive timing control signal REF_DB, and a QB output coupled to a first input of three-input AND gate 234 . Similarly, D flip-flop 224 includes a data input adapted to receive clock DIV4 , a clock input to receive timing control signal REF_DB, and a QB output coupled to a second input of three-input AND gate 234 . Additionally, D flip-flop 226 includes a data input adapted to receive clock DIV8 , a clock input to receive timing control signal REF_DB, and a QB output coupled to a third input of three-input AND gate 234 . As discussed in more detail below, D flip-flops 222, 224, and 226 assist in establishing the time for synchronously triggering changes in the frequency of the output reference clock REFOUT.

D flip-flop 228 includes a data input adapted to receive clock DIV2 , a clock input to receive timing control signal REF_D1 , and a QB output coupled to a first input of three-input XOR gate 236 . Similarly, D flip-flop 230 includes a data input adapted to receive clock DIV4 , a clock input to receive timing control signal REF_D1 , and a QB output coupled to a second input of three-input XOR gate 236 . Additionally, D flip-flop 232 includes a data input adapted to receive clock DIV8 , a clock input to receive timing control signal REF_D1 , and a QB output coupled to a third input of three-input XOR gate 236 . As discussed in more detail below, D flip-flops 228, 230, and 232 assist in establishing the time for synchronously triggering changes in the frequency of the output reference clock REFOUT.

Three-input AND gate 234 includes an output coupled to a first input of a second AND gate 238 . Three-input Exclusive-OR gate 236 includes an output coupled to a second input of a second AND-gate 238 . The output of second AND gate 238 is coupled to the clock input of D flip-flops 240 and 242 . D flip-flop 218 includes a data input adapted to receive input frequency selection control signal DIVIN_1 from frequency controller 120 , a clock input to receive timing control signal REF_DB, and a Q output coupled to the data input of D flip-flop 242 . D flip-flop 220 includes a data input adapted to receive input frequency selection control signal DIVIN_0 from frequency controller 120 , a clock input to receive timing control signal REF_DB, and a Q output coupled to the data input of D flip-flop 240 . Output frequency selection control signals DIVRO_0 and DIVRO_1 are generated at respective Q outputs of D flip-flops 240 and 242 .

Four-input MUX 244 includes four inputs adapted to receive raw reference clock REF_IN and distinct frequency clocks DIV2, DIV4, and DIV8. The four-input MUX includes two selection inputs adapted to receive output frequency selection control signals DIVRO_0 and DIVRI_1. Four-input MUX 244 includes an output coupled to the data input of two-clock D flip-flop 246 . The two-clock D flip-flop 246 in turn includes a first clock input adapted to receive the timing control signal REF_D, and a second clock input adapted to receive the timing control signal REF_DB. Two-clock D flip-flop 246 includes a Q output coupled to a first input of two-input MUX 248 . The two-input MUX 248 in turn includes a second input adapted to receive a raw reference clock REF_IN, and an output adapted to generate an output reference clock REFOUT. The operation of programmable frequency device 200 will now be discussed.

3 illustrates a timing diagram of exemplary signals generated within exemplary programmable frequency device 200 according to another aspect of the invention. The top graph illustrates the raw reference clock REF_IN. The next figure illustrates the timing control signal REF_D. It should be noted that the timing control signal REF_D is substantially a delayed version of the original reference clock REF_IN due to the delay chain 204 . The next figure illustrates the timing signal REF_DB substantially inverting the timing control signal REF_D. The next figure illustrates timing signal REF_D1 that is substantially a delayed version of timing signal REF_D. The next three figures illustrate distinct frequency clocks DIV2, DIV4, and DIV8, respectively. The next pair of figures illustrate examples of input frequency selection control signals DIVIN_1 and DIVIN_0 generated by frequency controller 120 . The next figure illustrates an example of the output frequency selection control signal DIVRO_0. Also, the last figure illustrates the output reference clock REFOUT.

The ENABLE control signal is used to enable or disable the frequency division function of the programmable frequency device 200 . A low logic level appears at the ENABLE input of AND gate 202 if the ENABLE control signal is not asserted (meaning the programmable frequency divide function is disabled). This basically disables the timing signals REF_D, REF_DB and REF_D1. This effectively disables substantially all of programmable frequency device 200 . Also, an unasserted ENABLE control signal causes MUX 248 to output raw reference clock REF_IN as output reference clock REFOUT. Therefore, by leaving the ENABLE control signal unasserted, the frequency division function can be bypassed.

On the other hand, if the ENABLE control signal is asserted, AND gate 202 allows raw reference clock REF_IN to be applied to the input of delay chain 204, thereby allowing timing control signals REF_D, REF_DB, and REF_D1 to be generated. In addition, the asserted ENABLE control signal causes MUX 248 to select the signal at the Q output of two-clock D flip-flop 246 as the output reference clock REFOUT.

In this exemplary timing diagram, the initial value (before time T1) of the input frequency selection control signal DIVIN_<1:0> is set to 00, which in turn causes D flip-flops 240 and 242 to switch between these flip-flops 240 and 242 Set the output frequency selection control signal DIVRO_<1:0> to 00 when timed. This causes MUX 244 to output the raw reference clock REF_IN. Since the two-clock D flip-flop 246 is clocked by two timing signals REF_D and REF_DB, the Q output is essentially the original reference clock REF_IN, except that it is substantially time aligned with the timing control signal REF_D. In this configuration, the timing control signal REF_D is used to clock out half of the period of the original reference clock REF_IN, and the timing control signal REF_DB is used to clock out the other half period of the original reference clock REF_IN.

The input frequency control signal DIVIN_<1:0> from the frequency controller 120 can be received by the programmable frequency device 200 asynchronously with the signals REF_IN, REF_D, REF_DB, etc. generated in the programmable frequency device 200 . In this example, the DIVIN_0 control signal transitions from a logic low level to a high logic level at time T1 as noted in the timing diagram. This makes the control signal DIVIN_<1:0> 01, which instructs the programmable frequency device 200 to output the clock DIV2 with half frequency as the output reference clock REFOUT.

When the distinct frequency clocks DIV2, DIV4, and DIV8 are all at low logic levels, the D flip-flops 222, 224, and 226 are substantially at the triggering edge (eg, rising edge) of the timing control signal REF_DB (eg, as shown in the timing diagram at time T2 indicated) clocks out a high logic level at its corresponding QB output. At this time T2, the input to three-input AND gate 234 is at a high logic level, thereby causing AND gate 234 to produce a high logic level. Similarly, when the different frequency clocks DIV2, DIV4, and DIV8 are all at high logic levels, the D flip-flops 228, 230, and 232 are substantially at the triggering edge (eg, rising edge) of the timing control signal REF_D1 (eg, at at time T3 indicated in the timing diagram) clocks out a low logic level at its corresponding QB output. At this time T3, the input to three-input XOR gate 234 is at a low logic level, thereby causing XOR gate 236 to produce a high logic level.

Thus, at time T3, both AND gate 234 and XOR gate 236 produce a high logic level at their respective outputs. Therefore, the input to AND gate 238 is also at a high logic level, causing AND gate 238 to transition its output from a low logic level to a high logic level. This produces trigger edges at the clock inputs of D flip-flops 240 and 242 . Since the input frequency selection control signal DIVIN_<1:0> is now at 01, the D flip-flops 240 and 242 will also clock the output frequency selection control signal DIVRO_<1:0> to 01. This is shown in the timing diagram as the rising edge of DIVRO_0 at time T3. The output frequency selection control signal DIVRO_<1:0> becomes 01 at time T3 causing the MUX 244 to output the frequency-divided clock DIV2. At time T4 as indicated in the timing diagram, the timing control signal REF_DB causes the two-clock D flip-flop 246 to clock the selected clock DIV2 . It should be noted that at time T4, the output reference clock REFIN and clock DIV2 are at a high logic level, therefore, the logic level of the output reference clock REFOUT does not change at that time. However, at time T5, the triggering edge (eg, rising edge) of timing control signal REF_D causes the two-clock D flip-flop to output a low logic level because the DIV2 clock is at a low logic level at this time.

In summary, the programmable clock device 102 generates the output reference clock REFOUT with substantially the same trigger edge as the trigger edge of the timing signal REF_D when enabled. This is shown in the timing diagram, where the triggering edge of the output reference clock REFOUT is substantially aligned with the timing edge of the timing control signal REF_D at times T6-T9. This is due to the timing control signal REF_D used to clock out the selected REF_IN, DIV2, DIV4 or DIV8 frequency. Thus, when changing between clocks REF_IN, DIV2, DIV4, and DIV8, the trigger edges are substantially aligned, and thus do not significantly interfere with the operation of the DPLL's control loop.

In addition, a circuit comprising D flip-flops 222, 224, 226, 228, 230, and 232, a three-input AND gate 234, a three-input EXCLUSIVE-OR gate 236, and an AND gate 238 generates trigger edges to cause output frequency selection Control signals DIVRO_<1:0> are changed at the select inputs of MUX 244 to cause frequency changes at specific times. In this example, triggering occurs every eight (8) cycles of the original reference clock REF_IN, or once every cycle of clock DIV8. A circuit comprising D flip-flops 218, 220, 240, 242 allows the input frequency selection control signal DIVIN_<1:0> to be received asynchronously and the output frequency selection control signal DIVRO_<1:0> to be generated synchronously to achieve Frequency changes.

The circuit comprising AND gate 202, delay chain 204, and inverters 206 and 208 operates to generate timing signals REF_D, REF_DB, and REF_D1 when the ENABLE control signal is asserted, and effectively disables the programmable The frequency division function of the frequency device 200. A circuit including D flip-flops 210, 212, and 214 generates distinct frequency clocks DIV2, DIV4, and DIV8, which are different frequency sources for outputting reference clock REFOUT. Finally, MUX 248 allows the frequency division function to be bypassed by passing only the raw reference clock REF_IN to its output when the ENABLE control signal is not asserted.

4 illustrates a block diagram of an exemplary communications device 400 (eg, transceiver) according to another aspect of the disclosure. In summary, transceiver 400 serves as one exemplary application of the previously discussed DPLL. In particular, the transceiver 400 includes a power management device that controls the frequency of the output reference clock REFOUT of the DPLL. In this way, the power management device reduces the frequency of the output reference clock REFOUT of the DPLL when high performance is not required, and increases the frequency of the output reference clock REFOUT when higher performance is required.

More specifically, transceiver 400 includes antenna 402, transmit/receive (TX/RX) isolation 404, receiver 406, local oscillator (LO) 408 including a DPLL as previously discussed, power management 410, and Emitter 412 . Antenna 402 is used to receive radio frequency (RF) signals from one or more remote communication devices via a wireless medium, and to transmit RF signals to one or more remote communication devices via a wireless medium. TX/RX isolation device 404 is used to route received signals to receiver 406 and transmit signals to antenna 402 while substantially isolating the input of receiver 406 from the transmit signals. The receiver 406 is used to down-convert the received RF signal to an intermediate frequency (IF) or baseband signal. Transmitter 412 is used to upconvert the IF or baseband outbound signal to an RF signal. A local oscillator (LO) 408 including a DPLL as discussed above provides a received local oscillator source LOR to the receiver 406 so it can perform its down conversion function. Similarly, a local oscillator (LO) 408 provides a transmit local oscillator source LOT for the transmitter 412 so that it can perform its frequency up conversion function.

As discussed in more detail below, the power management device 410 controls the frequency of the output reference clock REFOUT of the DPLL of the local oscillator 408 in response to performance and power consumption requirements. As an example, when high performance of the DPLL is required, the power management device 410 may set the frequency of the output reference clock REFOUT to be substantially the same as the frequency of the original reference clock REFIN (eg, frequency divisor=1). As another example, when the low performance of the DPLL is acceptable and power saving is desired, the power management device 410 may set the frequency of the output reference clock REFOUT to substantially the frequency of the DIV8 clock (eg, frequency divisor=8). As yet another example, when moderate performance of the DPLL is acceptable and power consumption is also required, the power management device 410 may set the frequency of the output reference clock REFOUT substantially to the frequency of the DIV2 or DIV4 clock (e.g., frequency divisor = 2 or 4).

5 illustrates a flowchart of an exemplary method 500 of controlling power consumption in an exemplary transceiver 400 according to another aspect of the invention. According to method 500, power management device 410 determines current performance requirements for transmitter 400 (block 502). The power management device 410 then adjusts the frequency of the output reference clock of the DPLL based on the current performance requirements of the transceiver 400 (block 504). This process may be repeated as necessary to achieve the desired trade-off between performance and power consumption over the continuous operation of transceiver 400 . Although a transceiver has been used to demonstrate a particular application of a DPLL, it should be understood that a DPLL may be used in other applications, for example, in receivers, transmitters, clock and data recovery devices, and the like.

In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Storage media may be any available media that can be accessed by a computer. By way of example and not limitation, the computer readable medium may comprise RAM, ROM, EEPROM, CD-ROM, or other optical disk storage, magnetic disk storage, or other magnetic storage, or may be used to carry or store instructions or data Any other medium that contains the desired program code in the form of a structure and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and Cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwave are included in the definition of media. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. way to reproduce the data. Combinations of the above should also be included within the scope of computer-readable media.

While the invention has been described in conjunction with various aspects, it should be understood that the invention is capable of other modifications. This application is intended to cover any variations, uses or adaptations of the invention which generally follow the principles of the invention and include such departures from the invention as are within known and customary practice within the art to which this invention pertains.

Claims (24)

1. A phase-locked loop device comprising: a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, and further adapted to maintain a trigger edge of the reference clock when the reference clock switches between the distinct frequency clocks substantially the same timing relationship, wherein maintaining the substantially same timing relationship of the trigger edges of the reference clock includes causing the reference clock to have substantially the same trigger edge as the timing control signal; and A phase locked loop (PLL) circuit adapted to establish a predetermined phase relationship between an input signal and an output signal using the reference clock. 2. The apparatus of claim 1, wherein the programmable frequency device comprises a source of the distinct frequency clocks. 3. The apparatus of claim 2, wherein the source of the distinct frequency clocks comprises a chain of cascaded flip-flops adapted to receive an original reference clock. 4. The apparatus of claim 1, wherein the programmable frequency means comprises circuitry adapted to asynchronously receive an input frequency selection indicative of a selection among the distinct frequency clocks for the reference clock control signal, and synchronously generating an output frequency selection control signal that causes said selection of said reference clock at a particular time. 5. The apparatus of claim 4, wherein the circuitry is adapted to synchronously generate the output frequency selection control signal in response to the distinct frequency clocks being at a predetermined logic level. 6. The apparatus of claim 4, wherein the programmable frequency device further comprises a first multiplexer adapted to output in response to the output frequency selection control signal from a selected one of the distinct frequency clocks. 7. The apparatus of claim 4, wherein the phase locked loop (PLL) includes an input accumulator adapted to generate the input signal based on the output frequency selection control signal. 8. The apparatus according to claim 4 , wherein said phase-locked loop (PLL) comprises phase error means adapted to generate a phase difference related to said input signal and said output signal a phase error signal, wherein the delay in generating the phase error signal is based on the output frequency selection control signal. 9. The apparatus of claim 1, further comprising a flip-flop adapted to clock out the reference clock in response to a timing control signal. 10. The apparatus of claim 1, wherein the phase locked loop (PLL) includes an input accumulator adapted to generate the input signal using the reference clock. 11. The apparatus of claim 1, wherein the phase-locked loop (PLL) comprises a latch or a time-to-digital converter (TDC) adapted to A signal related to the phase of the output signal is generated using the reference clock. 12. A phase-locked loop device comprising: a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, and further adapted to maintain a trigger edge of the reference clock when the reference clock switches between the distinct frequency clocks substantially the same timing relationship, wherein maintaining the substantially same timing relationship of the trigger edges of the reference clock includes causing the reference clock to have substantially the same trigger edge as the timing control signal; and a phase locked loop (PLL) circuit adapted to establish a predetermined phase relationship between an input signal and an output signal using the reference clock, wherein the programmable frequency device comprises circuitry adapted to asynchronously receive instructions for an input frequency selection control signal of the selection of the reference clocks among the distinct frequency clocks, and synchronously generating an output frequency selection control signal causing the selection of the reference clock at a particular time, and wherein the The circuit generates the output frequency selection control signal once in a cycle of one of the distinct frequency clocks. 13. The apparatus of claim 12, wherein the one of the distinct frequency clocks comprises the clock having the longest period among the distinct frequency clocks. 14. A phase-locked loop device comprising: a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, and further adapted to maintain a trigger edge of the reference clock when the reference clock switches between the distinct frequency clocks substantially the same timing relationship, wherein maintaining the substantially same timing relationship of the trigger edges of the reference clock includes causing the reference clock to have substantially the same trigger edge as the timing control signal; and a phase locked loop (PLL) circuit adapted to establish a predetermined phase relationship between an input signal and an output signal using the reference clock, wherein the programmable frequency device comprises circuitry adapted to asynchronously receive instructions for an input frequency selection control signal of the selection of the reference clocks among the distinct frequency clocks, and synchronously generating an output frequency selection control signal causing the selection of the reference clock at a particular time, and wherein the The phase locked loop (PLL) includes a filter including a transfer function based on the output frequency selective control signal. 15. A phase-locked loop device comprising: Programmable frequency means adapted to generate a reference clock selected from a set of distinct frequency clocks, and further adapted to maintain substantially the same timing of trigger edges of said reference clock when switching between said distinct frequency clocks relationship, wherein maintaining substantially the same time relationship of the trigger edges of the reference clock includes causing the reference clock to have substantially the same trigger edge as the timing control signal; and a phase locked loop (PLL) circuit adapted to establish a predetermined phase relationship between an input signal and an output signal using the reference clock, wherein the programmable frequency device comprises circuitry adapted to asynchronously receive instructions for an input frequency selection control signal for selection of the reference clock among the distinct frequency clocks, and synchronously generates an output frequency selection control signal causing the selection of the reference clock at a particular time, wherein the A phase-locked loop (PLL) comprising: an accumulator adapted to generate a first signal related to a rough value of said phase of said output signal; and a time-to-digital converter (TDC) adapted to generate a first signal related to said a second signal related to a fine value of said phase of the output signal; and means adapted to generate a feedback phase signal related to the combination of said first and second signals, and wherein in generating said feedback phase signal The delay is based on the output frequency selection control signal. 16. A method of providing a reference clock comprising: selecting a first clock from a set of distinct frequency clocks; providing the first clock as the reference clock; selecting a second clock from the set of distinct frequency clocks, wherein the first frequency of the first clock is different from the second frequency of the second clock; providing the second clock as the reference clock, wherein a timing relationship of a trigger edge of the second clock is substantially the same as a timing relationship of a trigger edge of the first clock; providing said reference clock to an input accumulator of a digital phase locked loop (DPLL); and The reference clock is provided to a time-to-digital converter (TDC) of the digital phase-locked loop (DPLL). 17. The method of claim 16, further comprising generating the distinct frequency clocks. 18. The method of claim 16, wherein the distinct frequency clocks comprise generating the distinct frequency clocks by dividing a frequency of an original reference clock. 19. The method of claim 16, further comprising receiving a first frequency selection control signal for selecting the second clock as the reference clock, wherein selecting is performed in response to the first frequency selection control signal The second clock is used as the reference clock. 20. The method of claim 19, wherein receiving the first frequency selective control signal comprises receiving the first frequency selective control signal asynchronously, and the method further comprises synchronously generating a second frequency selective control signal, And further wherein selecting the second clock as the reference clock is performed in response to the second frequency selection control signal. 21. The method of claim 20, wherein generating the second frequency selection control signal comprises generating the second frequency selection control signal in response to the distinct frequency clocks being at a predetermined logic level. 22. The method of claim 16, further comprising: The reference clock is provided to a digitally controlled oscillator (DCO) of the digital phase locked loop (DPLL). 23. A method of providing a reference clock comprising: selecting a first clock from a set of distinct frequency clocks; providing the first clock as the reference clock; selecting a second clock from the set of distinct frequency clocks, wherein the first frequency of the first clock is different from the second frequency of the second clock; providing the second clock as the reference clock, wherein a timing relationship of a trigger edge of the second clock is substantially the same as a timing relationship of a trigger edge of the first clock; receiving a first frequency selection control signal for selecting the second clock as the reference clock, wherein selecting the second clock as the reference clock is performed in response to the first frequency selection control signal, wherein receiving the said first frequency selective control signal comprises receiving said first frequency selective control signal asynchronously; and synchronously generating a second frequency selection control signal, wherein selecting the second clock as the reference clock is performed in response to the second frequency selection control signal, and wherein generating the second frequency selection control signal is included in the The second frequency selection control signal is generated once in a cycle of one of the different frequency clocks. 24. A phase locked loop device comprising: means for generating a reference clock selected from a set of distinct frequency clocks; means for maintaining substantially the same timing relationship of trigger edges of the reference clocks as the reference clocks switch between the distinct frequency clocks, wherein substantially the same timing relationship of the trigger edges of the reference clocks is maintained The timing relationship includes causing the reference clock to have substantially the same trigger edge as the timing control signal; means for establishing a predetermined phase relationship between an input signal and an output signal using said reference clock; means for asynchronously receiving a first frequency selection control signal indicative of a selection among said distinct frequency clocks for said reference clock; and means for synchronously generating a second frequency selective control signal causing said selection of said reference clock at a particular time, wherein said means for synchronously generating said second frequency selective control signal is adapted to be at The second frequency selection control signal is generated once in a cycle of one of the different frequency clocks.