CN104300970A - A DLL-based voltage-controlled ring vibration type two-stage time-to-digital conversion circuit - Google Patents

Abstract

The invention discloses a voltage-control ring vibration type two-section type time digital conversion circuit based on a DLL. TDC conversion with rough counting measuring and fine counting distinguishing is used in digital quantization of a tested time period. Delay time of a voltage-control delay unit is adjusted and controlled by the stage number a delay unit in a delay chain and the DLL. Under control of the DLL, a high-frequency stable clock is generated in a voltage-control ring vibration mode, multi-digit pseudorandom sequence LFSR counting is driven, and the function of rough counting measuring is achieved. High-section rough counting TDC has the effect of conversion range expanding, meanwhile, an N-stage voltage-control delay ring vibration structure is modulated by the DLL, by distinguishing of the evenly-distributed phases of nodes in a loop, rough measuring TDC quantization error time is subjected to fine quantization, and accordingly quantization accuracy is improved. A built-in identical-frequency redundancy coding processing mode is used in the low-band TDC, so that the common requirements of area lowering and data error code reducing are met at the same time.

Description

A kind of voltage-controlled loop oscillation type two-part time-to-digital conversion circuit based on DLL

Technical field

The present invention relates to and fill parallel operation, particularly a kind of voltage-controlled loop oscillation type two-part time-to-digital conversion circuit based on DLL a kind of digit time.

Background technology

Time figure conversion (Time-to-Digital Converter, TDC) circuit is used for the function of deadline accurate measurement, namely for measuring between two asynchronous signals or the time interval of pulse persistance, the analog signal of carrying temporal information is converted to digital signal, and then completes sampling and the digital processing of the time signal quantized.The most crucial requirement of time measurement improves time detecting resolution under particular measurement scope, and the key of therefore TDC design is the dynamic range improving time measurement.At present, TDC technology has general application in application study, national defence and the developments of the national economy such as Aero-Space, deep space communication, satellite launch and monitoring, geological mapping, navigational communications, electric power transfer and Scientific Measurement, even be deep into people different social sectors, almost without less than.Although traditional TDC circuit that digital CMOS technology realizes has the advantages such as technique is simple, cost is low, portability is good, working stability, circuit area are little, but the TDC circuit realized with analogue technique is similar, there is job insecurity equally, be subject to outside noise, the shortcoming such as temperature and voltage disturbance.

Along with improving constantly of requiring for the precision of time measurement and measuring range, unistage type TDC cannot meet the common prescription of precision and measuring range, and segmented TDC is while expansion measuring range, still can be good at the requirement taking into account certainty of measurement, thus the time measurement dynamic range under effective lifting high-resolution, meet the needs of different application better.Along with segmented TDC popularizes, the problems such as the chain type TDC structural area in segmental structure is excessive, first phase is indefinite are day by day obvious.Therefore, the ring developed by the chain type TDC TDC that shakes is widely used.The ring TDC that shakes can not only arrange the first phase of onboard clock signal, suppress the measure error item that first phase mismatch is brought, and ring shakes and can reuse, and extends measuring range, or realizing taking less chip area under same detection range.But traditional ring TDC structural resolution that shakes is limited by process technology limit, the frequency that its self-oscillation produces is very large by the impact of all kinds of noise disturbances such as power supply, flow-route and temperature drift, directly reduces low section ring and to shake the temporal resolution of TDC.

For the different disposal of time cycle, TDC time detecting is divided into two types.One is attribute, and Measuring Time is the integral multiple of count cycle, i.e. nTc, and max quantization error is the clock cycle; Another kind is phase-resolved type, and a count cycle is evenly divided into some deciles, and by relevant position judgement and decoding process, obtain translation data and export, max quantization error is reduced to time of delay corresponding to minimum phase difference.Obviously, counter TDC is applicable to the expansion of count upper-limit scope, and phase-resolved formula TDC is only a clock cycle because of range, is therefore particularly suitable for the lifting of certainty of measurement.For single TDC, cannot take into account or meet simultaneously the common prescription of time test range and measuring accuracy, for taking into account the joint demand of measuring range and precision, expand the dynamic range of time measurement, TDC must adopt the segmented system configuration more than based on counter and phase-resolved formula two-part of different nature.

Summary of the invention

Goal of the invention: for above-mentioned prior art, proposes a kind of voltage-controlled loop oscillation type two-part time-to-digital conversion circuit based on DLL, and this TDC possesses the time detecting resolution of degree of precision and working stability is not easily disturbed.

Technical scheme: a kind of two-part transducer digit time controlled based on delay chain phase-locked loop, comprises the low section of configurable ring differentiated based on clock phases and to shake TDC, high section attribute TDC, delay chain phase-locked loop, decoding circuit and latch; The described low section of configurable ring TDC that shakes comprises the voltage-controlled ring be made up of N level delay cell and to shake unit, and described high section attribute TDC comprises multidigit pseudo random sequence LFSR counter; Described delay chain phase-locked loop connects external reference clock, described voltage-controlled ring is shaken the delay cell progression regulation and control of unit of being shaken by described delay chain phase-locked loop and voltage-controlled ring time of delay of unit, and the described voltage-controlled ring unit that shakes exports high frequency clock and drives described multidigit pseudo random sequence LFSR counter to carry out measurement to the time to be measured to obtain high section count value; 2N the leggy node state that described N level delay cell is formed is carried out with redundancy decoding process frequently through described decoding circuit, when the Stop signal of time to be measured arrives, described latch obtains low section of count value after latching decoder output value, and high section count value when described low section of count value and Stop signal arrive by described latch carries out Serial output.

Further, the described voltage-controlled ring be made up of N level delay cell shakes in unit, and first order delay cell is the multiplexed selector of 2-1, and described second is the buffer that structure is identical to N level delay cell; Described first order delay cell is all identical to the time of delay of N level delay cell with second, the multiplexed selector of described 2-1 is anti-phase time delay, described second is same phase delay to N level delay cell, first input channel of the multiplexed selector of described 2-1 connects outside gate-control signal EN and logic control circuit, and the second input channel connects the feedback signal of N level delay cell; When described outside gate-control signal EN is low level, described logic control circuit controls voltage-controlled ring each the leggy node in unit that shakes and is predisposed to high level, after outside gate-control signal EN high level arrives, the voltage-controlled ring of startup shakes cell operation, when trailing edge saltus step appears in outside gate-control signal EN, the voltage-controlled ring unit that shakes quits work.

Further, the described voltage-controlled ring unit that shakes is made up of 8 grades of delay cells, described with redundancy decoding frequently by increasing 1bit decoded bits Y in decoding value highest order ₀as redundancy arbitration position, obtain decoding carry-out bit Y ₀-Y ₄expression formula be:

$Y_0=\stackrel{\‾}{B_8}=B_8\⊕1---\left(1\right)$

$Y_1=B_4\⊕B_8---\left(2\right)$

$Y_2=B_3\⊕B_7---\left(3\right)$

$Y_3=B_2\⊕B_6---\left(4\right)$

$Y_4=B_1\⊕B_5---\left(5\right)$

Wherein, B ₁~ B ₈be respectively the output phase state of the first order to the 8th grade of delay cell.

Based on the two-dimensional array testing circuit that delay chain phase-locked loop controls, comprise the low section of configurable ring differentiated based on clock phases and to shake TDC, delay chain phase-locked loop, decoding circuit and N number of pixel cell; Wherein, the described low section of configurable ring TDC that shakes comprises the voltage-controlled ring be made up of N level delay cell and to shake unit, and described each pixel cell comprises high section attribute TDC, latch; Described delay chain phase-locked loop connects external reference clock, described voltage-controlled ring shake unit time of delay by described delay chain phase-locked loop and voltage-controlled ring shake unit delay cell progression regulation and control, the described voltage-controlled ring unit that shakes exports high frequency clock and drives high section attribute TDC in described each pixel cell to carry out measurement to the time to be measured to obtain high section count value, and described decoding circuit is used for shaking 2N the real-time decoding of leggy node state that N level delay cell in unit forms to described voltage-controlled ring; When described N number of pixel cell receives the Stop signal of time to be measured corresponding to each pixel respectively, latch in each pixel obtains low section of count value of respective pixel unit after latching for the decoding value exported decoding circuit, high section count value when corresponding low section of count value and Stop signal arrive by the latch in each pixel carries out Serial output.

Further, the decoding unit in each pixel is the decoding unit adopting Gray code decoded mode.

Beneficial effect: a kind of two-part transducer digit time controlled based on delay chain phase-locked loop of the present invention, the digital quantization of tested period adopts thick count measurement to differentiate the TDC combined change with thin counting.Wherein, thick count measurement realizes based on high section attribute TDC, and thin counting adopts the low section of configurable ring differentiated based on the clock phases TDC that shakes to realize.Low section of configurable ring TDC that shakes comprises the voltage-controlled ring be made up of N level delay cell and to shake unit, voltage-controlled ring shakes and regulates and controls with the delay chain phase-locked loop be connected (DLL) by the progression of delay cell in delay chain time of delay of unit, DLL control under voltage-controlled ring shake unit produce high-frequency stabilization clock drive high section attribute TDC to count, realize thick count measurement function.High section slightly counts the effect that TDC bears expansion conversion range; Meanwhile, adopt the voltage-controlled ring of N level of DLL modulation to shake unit, by the equally distributed phase-resolved realization of node each in loop to the thin quantification of bigness scale amount TDC quantization error time, thus improve quantified precision.Reduce area and the common prescription reducing data errors for taking into account, low section of TDC adopts built-in same frequency redundancy decoding processing mode; Thick counting and thin enumeration data are by control logic Serial output, and realize seamless connection, wherein high section of TDC adopts external decoding, finally obtain the period measurement quantized data that binary code exports.

Improve the time detecting precision of two-part TDC, the key of high section TDC is stable counted clock cycle Tc, and the key of low section of TDC is even division to Tc phase place and resolution, and to the configuration of clock cycle Tc initial phase or control.The TDC structure that the non-DLL of tradition controls lacks closed loop feedback and controls due to the ring control voltage Vctrl that shakes, and electric source disturbance and analogue noise interference all can produce material impact to the stability of ring vibration frequency, and its centre frequency changes with temperature and process drift.In order to make ring vibration frequency stability, the voltage-controlled ring that the present invention adopts shakes and the wide region of clock frequency not only can be regulated to change, and by the stability contorting to voltage control signal, effectively can improve the stability of ring vibration frequency, reduces phase noise; Be specially when the TDC controlled based on DLL is disturbed, in DLL, the clock output feedack of voltage-controlled delay chain afterbody is to phase frequency detector, carry out phase compare with input clock, adjustment gate control voltage makes delay units delay in DLL keep stable, not by the impact of all kinds of running parameter; Namely by adjusting Vctrl voltage to adapt to voltage-controlled voltage needed for various condition of work, thus making the delay units delay time of voltage-controlled delay chain constant, making ring vibration frequency keep stable.Simultaneously, adopt the close-loop control mode that voltage control signal is provided by DLL circuit, its control performance is more superior relative to open loop structure, this is because when environment changes, DLL exists feedback loop, and can to maintain the shake delay chain of unit of voltage-controlled ring by self-regulation constant for time of delay.

Further, the status data of the voltage-controlled ring center of percussion delay chain of low section of TDC latch adopts the decoded mode process of same frequency code, this decoding belongs to middle transition decoding, data bit compression after decoding, but this intermediate code relative binary code, add a redundancy arbitration position in highest order, except highest order redundancy arbitration position, all the other each all complete the latch of decoding data with same frequency code form, its frequency keeps identical with ring vibration frequency, far below the lowest order frequency of binary decoding; The input fan-in number of each state node decoding is identical, and every one-level fan-in point exists same structure, and each branch resistance capacitive load in corresponding same frequency code decoding circuit is identical, thus realizes the delay match of every grade.Adopt intermediate translation, effectively taken into account the joint demand that decoding figure place reduces and minimum decoding data bit frequency reduces, the reduction of decoding carry-out bit frequency can make the error rate significantly reduce.The voltage-controlled ring be made up of delay cell shakes by DLL voltage control, and this control voltage determines by driving the reference clock signal of DLL.When reference clock is stablized, DLL is voltage-controlled stable, and ring shakes the frequency stabilization produced, and when external environment changes, ring vibration frequency is not easily affected.Variations in temperature, process drift and there is power supply noise condition of work under, voltage-controlled ring shakes within the relative change rate of oscillator clock frequency can be controlled in +/-0.2%.

A kind of two-part transducer digit time controlled based on delay chain phase-locked loop can detect from single picture point time extension of detecting capability to two-dimensional array, thus obtains the two-dimensional array testing circuit controlled based on delay chain phase-locked loop of the present invention.Shake TDC and decoding circuit of the low section of configurable ring wherein differentiated based on clock phases is that each pixel of system is shared, low section of configurable ring voltage-controlled ring shaken in TDC high frequency clock that unit produces that shakes is system global clock, and high section attribute TDC is exclusively enjoyed by each pixel cell, namely each pixel cell all comprises an independently high section of attribute TDC, and to shake the unified driving of high frequency clock signal that unit produces by system ring.High frequency clock signal is through H tree structure path transmission to each pixel cell, and such transmission structure can eliminate the impact of clock-skew, realizes consistency and the uniformity of pixel data.Adopt the system that low section of TDC system is shared, high section TDC pixel exclusively enjoys, two-part TDC simplifies because of circuit structure, and area is little; Two-part list pixel TDC is expanded to two-dimensional array type TDC, precision and quantification range all meet the needs of array image-forming application.

Accompanying drawing explanation

Fig. 1 is a kind of two-part converter structure digit time figure controlled based on delay chain phase-locked loop;

Fig. 2 is the 7bit LFSR (linear feedback shift register) that in two-part transducer digit time based on delay chain phase-locked loop control, high section attribute TDC adopts;

Fig. 3 is that in two-part transducer digit time controlled based on delay chain phase-locked loop, low section of configurable ring shakes the voltage-controlled delay unit of TDC;

Fig. 4 is a kind of low five digit wave form analogous diagram of the two-part transducer digit time final quantization output valve based on delay chain phase-locked loop control;

Fig. 5 is the simulation waveform figure that in two-part transducer digit time based on delay chain phase-locked loop control, 7bit LFSR exports;

Fig. 6 is the circuit framework that two-part time-to-digit converter expands to pixel two-dimensional array;

Fig. 7 is the pixel cell structure figure of pixel two-dimensional array.

Embodiment

Below in conjunction with accompanying drawing the present invention done and further explain.

As shown in Figure 1, based on two-part transducer digit time that delay chain phase-locked loop controls, comprise the low section of configurable ring differentiated based on clock phases and to shake TDC, high section attribute TDC, delay chain phase-locked loop (DLL), decoding circuit and latch.Low section of configurable ring TDC that shakes comprises the voltage-controlled ring be made up of N level delay cell and to shake unit; As shown in Figure 2, high section attribute TDC comprises 7 pseudo random sequence LFSR counters.Delay chain phase-locked loop adopts closed loop to postpone line type structure, and its voltage-controlled delay chain (VCDL) is 16 grades.Delay chain phase-locked loop meets external reference clock REF, voltage-controlled ring shake unit time of delay by delay chain phase-locked loop charge pump export voltage-controlled voltage Vctrl and voltage-controlled ring shake unit delay cell progression regulation and control.The voltage-controlled ring unit that shakes exports high frequency clock and drives 7 pseudo random sequence LFSR counters to carry out measurement to the time to be measured to obtain high section count value, realizes exporting the pseudorandom tally function of high frequency clock signal to the voltage-controlled ring unit that shakes.16 leggy node states of 8 grades of delay cell formations are carried out with redundancy decoding process frequently through decoding circuit; When the Stop signal of time to be measured arrives, latch obtains low section of count value after latching decoder output value, and high section count value when low section of count value and Stop signal arrive by latch carries out Serial output.

Wherein, the voltage-controlled ring be made up of 8 grades of delay cells shakes in unit, and first order delay cell is the multiplexed selector of 2-1, and the 2nd to the 8th grade of delay cell is the buffer that structure is identical, as shown in Figure 3.First order delay cell is all identical with the time of delay of the 2nd to the 8th grade of delay cell, and the multiplexed selector of 2-1 is anti-phase time delay, and the 2nd to the 8th grade of delay cell is same phase delay.First input channel of the multiplexed selector of 2-1 connects outside gate-control signal EN and logic control circuit, and the second input channel connects the feedback signal of N level delay cell.

Because DLL enters the time that lock-out state needs about 600ns, so before gate-control signal EN arrives, DLL answers prerequisite activity, and DLL reaches stable state before gate-control signal EN arrives.When gate-control signal EN is low level 0, control logic circuit makes the voltage-controlled ring inner every one-level delay cell of unit of shaking all be predisposed to high level, after gate-control signal EN high level arrives, at once start voltage-controlled ring to shake cell operation, therefore the shake first phase of inner each node of starting of oscillation moment ring is determined.When trailing edge saltus step appears in gate-control signal EN, ring shakes and at once disconnects, and quits work.And be in high level valid interval at gate-control signal EN, the arrival of gate-control signal EN is that its rising edge (or its fixed delay) starts counting, counting is then stopped, by high section attribute TDC record count result after the Stop signal rising edge arrival of time to be measured.Meanwhile, by the input gate signal controlling of 2-1 analog multichannel switch, the feedback loop that ring can be shaken under input EN gate-control signal is low level condition disconnects, and stops oscillation, reduces system average power consumption.

Produce and transmission two kinds of mode of operations for adapting to data, and reduce area occupied, low section of configurable ring TDC and high section attribute TDC that shakes all comprises data and produces and transfer of data two kinds of mode of operations, and the circuit structure that two kinds of mode multiplexings are identical.During EN gate is invalid, LFSR loop disconnects, and is switched to data serial shift mode, realizes the Serial output to TDC data.Due in low section of TDC, 2N the leggy node state be made up of N level delay cell be compressing and converting data after with redundancy decoding process frequently, after splicing with the thick enumeration data without decoding, the shift register serial mode configured by open loop LFSR is exported again; So the partial data exported also needs to split into original two sections again in backstage DSP or FPGA processor complete binary decoding respectively, splicing obtains complete binary system TDC translation data.

Voltage-controlled ring center of percussion 8 delay cells have 16 nodes, and when low section quantizes, in one-period, adjacent node changes time interval be (1/16) Tc, Tc is the external reference clock REF cycle.Voltage-controlled ring shakes the high frequency clock that exports often through one-period, and clock transfer is in the LFSR of 7bit, and high section count value is just corresponding adds 1.The frequency of outside defeated reference clock REF is 62.5MHz, cycle 16ns.Based on voltage-controlled feedback principle, every grade of delay units delay time is 1ns.The input signal propagate that ring shakes is under regulating with the same voltage-controlled voltage Vctrl of voltage-controlled delay chain, every grade of delay cell inherent delay time strictly copies voltage-controlled delay chain delay cell, every grade of time of delay is 1ns, the ring cycle of shaking is 16 × 1=16ns, and the shake inverse in cycle and frequency of ring is about 62.5MHz.For 16 phase clocks output signals, every phase clock adopts 1 DFF to latch, and needs 16 DFF altogether, considers the redundancy of node state information, only need store 8 (continuous print 8 or discontinuous independently 8) state node variablees; But longer delay chain still can take very large area, therefore first decoding is completed to node state each in delay chain, then the data after decoding are latched and transmits.Set up the retention time because d type flip flop exists, adopt traditional binary code and Gary code decoding circuit, lowest order signal intensity frequency can significantly increase, and causes the error rate too high.Therefore, decoding circuit needs the frequency reducing lowest weightings position signal as far as possible, reduces power consumption, suppresses the error rate.

For this reason, increase 1bit decoding figure place for cost with decoding value highest order, adopt same frequency code decoded mode, exchange the remarkable increase of low section of TDC low weight bit data frequency for.Eight grades of voltage-controlled ring center of percussion delay cell export formation 16 phase states, after buffer stage, enter decoding circuit, and the data frequency that decoding exports is identical, but decoding carry-out bit is increased to 5bit, wherein comprise with the required 1bit redundant code increased of decoding frequently.With frequency decoding logic as a kind of middle or transition type decoded mode, obtain decoding carry-out bit Y ₀-Y ₄expression formula be:

$Y_0=\stackrel{\‾}{B_8}=B_8\⊕1---\left(1\right)$

$Y_1=B_4\⊕B_8---\left(2\right)$

$Y_2=B_3\⊕B_7---\left(3\right)$

$Y_3=B_2\⊕B_6---\left(4\right)$

$Y_4=B_1\⊕B_5---\left(5\right)$

Wherein, B ₁~ B ₈be respectively the output phase state of the first order to the 8th grade of delay cell.

The decoding of low section of TDC middle transition character solves the matching problem in different path and binary decoding and exports the high bit-error problem that low weight bit data signal frequency multiplication causes above, and its decoding circuit of low five as shown in Figure 4.Article five, decoding path is all made up of an XOR gate, and every grade of phase node all only has one-level fan-in and load is identical, except Y ₀be still outside input clock frequency 62.5MHz as additional arbitration bit frequency, Y ₁-Y ₄the frequency of decoding data signal is identical, for reference clock frequency and the 125MHz of twice, four paths structures are identical, and matching is good, avoid the d type flip flop error code that normal binary decoding circuit causes because frequency is too high, and the edge error code problem caused because of path delay mismatch.

The two-part time-to-digital conversion circuit TDC of single pixel can be extended to two-dimensional array of pixels and detect application above.As shown in Figure 6, a kind of two-dimensional array testing circuit controlled based on delay chain phase-locked loop, comprises the low section of configurable ring differentiated based on clock phases and to shake TDC, delay chain phase-locked loop, decoding circuit and N number of pixel cell.Wherein, low section of configurable ring TDC that shakes comprises the voltage-controlled ring be made up of N level delay cell and to shake unit, and each pixel cell comprises high section attribute TDC, latch.Delay chain phase-locked loop connects external reference clock, voltage-controlled ring shake unit time of delay by delay chain phase-locked loop and voltage-controlled ring shake unit delay cell progression regulation and control.The voltage-controlled ring unit that shakes exports high frequency clock and drives high section attribute TDC in each pixel cell to carry out measurement to the time to be measured to obtain high section count value, and decoding circuit is used for shaking 2N the real-time decoding of leggy node state that N level delay cell in unit forms to voltage-controlled ring.When N number of pixel cell receives the Stop signal of time to be measured corresponding to each pixel respectively, latch in each pixel obtains low section of count value of respective pixel unit after latching for the decoding value exported decoding circuit, high section count value during its low section of count value and arrival of Stop signal is accordingly carried out Serial output by the latch in each pixel.

Wherein, low section of configurable ring TDC intermediate translation that shakes adopts nonredundant Gray code decoded mode, eliminate the transmission of 1bit redundancy arbitration position, reduce elemental area or expand to measure range, its error rate a little more than the redundant digit decoded mode adopted in single dot structure, but still is starkly lower than the error rate adopting binary decoding mode.

When above-mentioned two-dimensional array testing circuit is applied to array type infrared sensing range finding imaging, its course of work is as follows: when gate-control signal EN rising edge arrives, synchronized transmissions laser signal also starts TDC counting, return when there being light signal and by pixel cell transducer receive sense after, produce stable narrow pulse signal Stop signal ended TDC through interface circuit process to count, now two-part time-to-digital conversion circuit completes digital quantity conversion to the flight time TOF that photo emissions and acceptance experience, and by resultant string line output.For each pixel through the tree-like arrangement of H, initial time is identical, but the STOP time receiving signal is different, and the time of count detection is different in allowed limits.

Above can also be shaken by ring as required TDC, LFSR high section TDC and the DLL circuit of two-part time-to-digit converter that two-dimensional array of pixels detects application that be extended to all is placed in outside system pixel array as sharing module, the two-part TDC that in system, all pixels are all shared unique in other words.Compared with the framework that system architecture is shared with low section of TDC system, high section TDC pixel exclusively enjoys that this whole TDC is all external, because high section TDC is also for system is shared, all can reduce by 1 high section of TDC circuit in each pixel, so the super low-power consumption of system can be realized.But because high section TDC is also placed in outside pixel, cause needing the data wire entering pixel to add 7.And the quantity for the d type flip flop storing data in actual pixels is constant, and the area of pixel also can be made to increase.Whole two-part TDC can be considered under the more sufficient condition of elemental area to be configured in pixel outside.

The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (5)

1. A two-stage digital time converter based on delay chain phase-locked loop control, characterized in that: it includes a low-stage configurable ring oscillator TDC based on clock cycle phase resolution, a high-stage counting type TDC, and a delay chain phase-locked loop , a decoding circuit and a latch; the low-stage configurable ring oscillator TDC includes a voltage-controlled ring oscillator unit composed of N-stage delay units, and the high-stage counting TDC includes a multi-bit pseudo-random sequence LFSR counter; the The delay chain phase-locked loop is connected to an external reference clock, and the delay time of the voltage-controlled ring vibration unit is regulated by the delay unit stages of the delay chain phase-locked loop and the voltage-controlled ring vibration unit, and the output of the voltage-controlled ring vibration unit is high The frequency clock drives the multi-bit pseudo-random sequence LFSR counter to measure the time to be measured to obtain the high-level count value; the 2N multi-phase node states formed by the N-level delay unit are subjected to same-frequency redundant decoding through the decoding circuit Processing, when the Stop signal of the time to be measured arrives, the latch is used to latch the output value of the decoder to obtain the low-segment count value, and the latch generates the low-segment count value and the arrival of the Stop signal The high-segment count value at the time is serially output. 2. A kind of two-stage digital-to-time converter based on delay chain phase-locked loop control according to claim 1, characterized in that: in the voltage-controlled ring oscillator unit composed of N-stage delay units, the first stage The delay unit is a 2-1 multiplexing selector, and the second to Nth stage delay units are buffers with the same structure; the delay time of the first stage delay unit and the second to Nth stage delay units are both Similarly, the 2-1 multiplexing selector is an inverting delay, and the second to Nth stage delay units are all in-phase delaying, and the first input of the 2-1 multiplexing selector The channel is connected to the external gate control signal EN and the logic control circuit, and the second input channel is connected to the feedback signal of the Nth stage delay unit; when the external gate control signal EN is at low level, the logic control circuit controls the voltage-controlled ring vibration unit Each multi-phase node is preset to a high level. When the external gating signal EN arrives at a high level, the VCO unit starts to work. When the external gating signal EN has a falling edge transition, the VCO unit Unit stopped working. 3. A two-stage digital-to-time converter based on delay chain phase-locked loop control according to claim 1, wherein the voltage-controlled ring oscillator unit is composed of 8-stage delay units, and the same-frequency redundant By adding a 1-bit decoding bit Y ₀ to the highest bit of the decoding value as a redundant arbitration bit, the expression of the decoding output bits Y ₀ -Y ₄ is obtained as follows: ${\mathrm{<span\; class="notranslate">\; Y</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; =</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; 8</span>}}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; 8</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$ ${\mathrm{<span\; class="notranslate">\; Y</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; 8</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$ ${\mathrm{<span\; class="notranslate">\; Y</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; 7</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$ ${\mathrm{<span\; class="notranslate">\; Y</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; 6</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$ ${\mathrm{<span\; class="notranslate">\; Y</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$ Wherein, B ₁ -B ₈ are the output phase states of the first-stage to eighth-stage delay units respectively. 4. A two-dimensional pixel array detection circuit based on delay chain phase-locked loop control, characterized in that: it includes a low-stage configurable ring oscillator TDC based on clock cycle phase resolution, a delay chain phase-locked loop, a decoding circuit, and N Pixel unit; wherein, the low-stage configurable ring oscillator TDC includes a voltage-controlled ring oscillator unit composed of N-stage delay units, and each pixel unit includes a high-stage counting type TDC and a latch; the delay chain lock The phase loop is connected to an external reference clock, the delay time of the voltage-controlled ring oscillator unit is regulated by the delay chain phase-locked loop and the delay unit stages of the voltage-controlled ring oscillator unit, and the voltage-controlled ring oscillator unit outputs a high-frequency clock drive The high-segment counting TDC in each pixel unit measures the time to be measured to obtain a high-segment count value, and the decoding circuit is used for 2N multi-phase node states formed by N-stage delay units in the voltage-controlled ring oscillation unit Real-time decoding; when the N pixel units respectively receive the Stop signal corresponding to the time to be measured of each pixel, the latch in each pixel is used to latch the decoding value output by the decoding circuit to obtain the corresponding For the low-segment count value of the pixel unit, the latch in each pixel serially outputs the corresponding low-segment count value and the high-segment count value when the Stop signal arrives. 5. A two-dimensional pixel array detection circuit based on delay chain phase-locked loop control according to claim 4, characterized in that: the decoding unit in each pixel is a decoding unit using Gray code decoding.