CN102006056A - Integrated circuit and method for obtaining reference clock in integrated circuit - Google Patents
Integrated circuit and method for obtaining reference clock in integrated circuit Download PDFInfo
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- CN102006056A CN102006056A CN2009101715392A CN200910171539A CN102006056A CN 102006056 A CN102006056 A CN 102006056A CN 2009101715392 A CN2009101715392 A CN 2009101715392A CN 200910171539 A CN200910171539 A CN 200910171539A CN 102006056 A CN102006056 A CN 102006056A
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Abstract
The invention discloses an integrated circuit. The integrated circuit comprises a first frequency dividing unit, a counter, an oscillation frequency generating circuit and a second frequency dividing unit, wherein the first frequency dividing unit is used to divide the frequency of an external clock signal input from the outside of the integrated circuit and obtain a first reference clock; the oscillation frequency generating circuit is used to generate an oscillating signal; the counter is used to count the oscillation signal with the first reference clock and obtain the frequency information of the oscillation signal; and the second frequency dividing unit is used to divide the frequency of the oscillation signal and obtain a second reference clock according to the frequency dividing factor which is obtained according to the frequency information. The invention also discloses a method for obtaining the reference clock in an integrated circuit. By adopting the scheme of the invention, the accurate reference clock can be obtained in the inexistence of a low frequency crystal oscillator, thus the two pins of the low frequency crystal oscillator are not required to be connected on the integrated circuit and the precious pin resource can be saved.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly integrated circuit reaches the method that obtains reference clock in integrated circuit.
Background technology
Existing SOC (system on a chip) (System-On-a-Chip, SOC) in design and the application, generally need to adopt the clock source of two crystal oscillators as SOC, one is that frequency of oscillation is the high frequency crystal oscillator of tens megahertzes, and another one is that frequency of oscillation is the low frequency crystal oscillator of tens KHz.As shown in Figure 1, high frequency crystal oscillator 12 is used as phase-locked loop among the SOC 11 (Phase-Locked Loop, PLL) the clock source of group 111 produces the required high frequency clock of various high-frequency circuits among the SOC.Low frequency crystal oscillator 13 mainly contains two purposes: one is the work clock when being used for producing the SOC11 standby; Another one is that the low frequency frequency divider of giving among the SOC 11 112 produces the required timing reference clock of accurate timing circuit, is generally frequency and is 1 hertz clock.Accurate timing among the SOC is mainly used to realize with the second to be the clocking capability of unit, as perpetual calendar and digital copyright management (Digital Right Management, function such as DRM).
Though also can produce the required reference clock of accurate timing by the high frequency crystal oscillator frequency division, electric current is bigger during owing to the high frequency crystal oscillator vibration, causes the power consumption of SOC accurate timing under holding state to accept.Among the therefore existing SOC, generally adopt the lower low frequency crystal oscillator of power consumption to produce the required reference clock of accurate timing.
The shortcoming of prior art is that SOC not only needs for high frequency crystal oscillator is equipped with two pins, but also will be equipped with two pins for low frequency crystal oscillator is special, and this causes resource the most rare among the SOC---pin is more nervous, rare.And (Bill of Material BOM) needs to increase low frequency crystal oscillator and required resistance of application circuit and electric capacity, thereby increases the BOM cost of SOC application product, the market competitiveness of reduction SOC owing to the BOM of producing the SOC application product.
Summary of the invention
In view of this, the objective of the invention is to, propose a kind of integrated circuit and a kind of method that in integrated circuit, obtains reference clock, can save pin resource valuable in the integrated circuit.
A kind of integrated circuit that the embodiment of the invention proposes comprises: first frequency unit, counter, oscillator signal produce the circuit and second frequency unit;
Described first frequency unit is used for obtaining first reference clock by the external timing signal from the outside input of described integrated circuit is carried out frequency division;
Oscillator signal produces circuit and is used to produce an oscillator signal;
Counter is used for by using described first reference clock described oscillator signal to be counted to get the frequency information of described oscillator signal;
Described second frequency unit is used for according to the Frequency Dividing Factor that obtains according to described frequency information described oscillator signal being carried out frequency division and obtains second reference clock.
Preferably, described first frequency unit comprises first frequency divider and second frequency divider;
Described first frequency divider is used for obtaining a clock signal by using a Frequency Dividing Factor that the external timing signal from the outside input of described integrated circuit is carried out frequency division;
Described second frequency divider is used for carrying out two divided-frequency by the clock signal that described first frequency divider is obtained and obtains first reference clock signal.
Perhaps, described first frequency unit is a frequency divider, is used for obtaining first reference clock by using a Frequency Dividing Factor that the external timing signal from the outside input of described integrated circuit is carried out frequency division.
Described integrated circuit also comprises control unit, be used for after described counter obtains described frequency information, the clock generating unit that is used to produce described external timing signal of controlling described first frequency unit, counter and/or integrated circuit outside enters non operating state.
This integrated circuit can further include: automatic alignment unit is used for controlling described first frequency unit, counter and described clock generating unit and enters operating state behind predetermined interval of calibration.
Described external timing signal is a high frequency clock signal, and described oscillator signal is an oscillating signal.
The embodiment of the invention also proposes a kind of method that obtains reference clock in integrated circuit, and described integrated circuit comprises that first frequency unit, counter, oscillator signal produce the circuit and second frequency unit, and described method comprises:
Described first frequency unit obtains first reference clock by the external timing signal from the outside input of described integrated circuit is carried out frequency division;
Counter counts to get the frequency information of described oscillator signal by an oscillator signal that uses described first reference clock that described oscillator signal is produced;
Described second frequency unit carries out frequency division according to the Frequency Dividing Factor that obtains according to described frequency information to described oscillator signal and obtains second reference clock.
Preferably, described first frequency unit comprises first frequency divider and second frequency divider;
Described first frequency unit is described to be obtained first reference clock and specifically comprises by the external timing signal from the outside input of described integrated circuit being carried out frequency division:
Described first frequency divider obtains a clock signal by using a Frequency Dividing Factor that the external timing signal from the outside input of described integrated circuit is carried out frequency division;
Described first frequency divider carries out two divided-frequency by the clock signal that described first frequency divider is obtained and obtains first reference clock signal.
Described method also comprises after obtaining the frequency information of described oscillator signal: the clock generating unit that is used to produce described external timing signal of controlling described first frequency unit, counter and/or integrated circuit outside enters non operating state.
Described method also comprises after the clock generating unit that is used to produce described external timing signal of control described first frequency unit, counter and/or integrated circuit outside enters non operating state: control described first frequency unit, counter and/or described clock generating unit and enter operating state behind predetermined interval of calibration.
Described external timing signal is a high frequency clock signal, and described oscillator signal is an oscillating signal.
As can be seen from the above technical solutions, the embodiment of the invention can be under the situation that does not need low frequency crystal oscillator, obtain reference clock accurately, thereby need not to connect two pins of low frequency crystal oscillator on the integrated circuit, pin resource that can saves valuable; And behind the frequency information of the oscillator signal that obtains the IC interior generation, the clock generating unit that promptly can control first frequency unit, counter and/or integrated circuit outside as required enters non operating state (quitting work), wait to use required accurate clock and still can continue the accurate timing of output to oscillation signal frequency dividing, satisfied the low-power consumption demand of holding state according to the Frequency Dividing Factor that the foundation frequency information obtains; In addition, can also be as required control first frequency unit, counter and clock generating unit at interval and enter operating state regaining the frequency information of oscillator signal, thereby can realize effect the in good time calibration of accurate clock with the predetermined alignment time.
Description of drawings
Fig. 1 is the schematic block diagram of the clock apparatus of SOC (system on a chip) in the prior art;
Fig. 2 is the block diagram of a kind of SOC (system on a chip) of employing the present invention program;
Fig. 3 is the realization block diagram of a kind of reference clock generation device of embodiment of the invention proposition;
Fig. 4 is the realization block diagram of the another kind of reference clock generation device of embodiment of the invention proposition;
Fig. 5 is the process chart that reference clock generation device shown in Figure 4 generates reference clock;
Fig. 6 is the realization flow figure of the reference clock of embodiment of the invention proposition.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is further elaborated below in conjunction with accompanying drawing.
Fig. 2 shows the block diagram of a kind of SOC (system on a chip) that adopts the embodiment of the invention.As seen from Figure 2, the periphery of SOC 21 no longer needs low frequency crystal oscillator, but produces reference clock signal by the reference clock generation device in the SOC (system on a chip) 212 according to the high frequency clock signal from high frequency crystal oscillator 22.And, satisfy SOC precisely low-power consumption requirement of timing under holding state in case after can the output reference clock signal, reference clock generation device 212 can no longer rely on high frequency clock signal and generate stable reference clock signal voluntarily.
The integrated circuit of the embodiment of the invention one comprises: first frequency unit, counter, oscillator signal produce the circuit and second frequency unit;
Described first frequency unit is used for obtaining first reference clock by the external timing signal from the outside input of described integrated circuit is carried out frequency division;
Oscillator signal produces circuit and is used to produce an oscillator signal;
Counter is used for by using described first reference clock described oscillator signal to be counted to get the frequency information of described oscillator signal; Wherein, described frequency information can be the frequency values of described oscillator signal, or arbitrary frequency division value of oscillation signal frequency value or frequency multiplication value etc.Wherein, use described first reference clock described oscillator signal to be counted to get the frequency information of described oscillator signal, for example can be behind first reference clock that obtains 0.5Hz, with the high level of the one-period of first reference clock/or low level part (duration was 1 second) oscillator signal is counted, thereby obtain the frequency values of oscillator signal; Understandable, when specific implementation, multiple implementation can be arranged, be not limited in this, for example, one-period with first reference clock is counted oscillator signal, thereby obtain 2 overtones band values of oscillator signal etc., first frequency unit also is not limited in first reference clock that obtains 0.5Hz.
Described second frequency unit is used for according to the Frequency Dividing Factor that obtains according to described frequency information described oscillator signal being carried out frequency division and obtains second reference clock; Wherein, the Frequency Dividing Factor that the described frequency information of described foundation obtains can be this frequency information itself, or arbitrary frequency division value of this frequency information or frequency multiplication value etc.
Preferably, described first frequency unit comprises first frequency divider and second frequency divider;
Described first frequency divider is used for obtaining a clock signal by using a Frequency Dividing Factor that first clock from the outside input of described integrated circuit is carried out frequency division; Described second frequency divider is used for carrying out two divided-frequency by the clock signal that described first frequency divider is obtained and obtains first reference clock signal.
Perhaps, described first frequency unit is a frequency divider, is used for obtaining first reference clock by using a Frequency Dividing Factor that first clock from the outside input of described integrated circuit is carried out frequency division.
Described integrated circuit also comprises control unit, is used for after described counter obtains described count results, and the device that is used to produce described first clock of controlling described first frequency unit, counter and/or integrated circuit outside enters non operating state.Can play the effect of saving power consumption like this; And after this, second frequency unit still can carry out frequency division to oscillator signal according to count results and obtains second reference clock.
Preferably, this integrated circuit further comprises: automatic alignment unit is used for controlling described first frequency unit, counter and the described device that is used to produce described first clock enters operating state according to predetermined interval of calibration.
Described first clock is a high frequency clock, and described oscillator signal is an oscillating signal.
The described Frequency Dividing Factor that first clock is carried out frequency division is the nominal frequency of described first clock or the crossover frequency or the frequency multiplication frequency of this nominal frequency.
Fig. 3 has provided the realization block diagram of the reference clock generation device 212 in a kind of SOC (system on a chip) of the embodiment of the invention two, comprises first frequency divider 31, second frequency divider 32, counter 33, low frequency RC oscillator 34 and tri-frequency divider 35.
The input of second frequency divider 32 comprises 1 hertz clock that the enabling signal and first frequency divider 31 produce, and output duty cycle is 1, frequency is 0.5 hertz first reference clock signal.The Frequency Dividing Factor of second frequency divider 32 is called second Frequency Dividing Factor, and its numerical value is 2, can realize by a frequency-halving circuit in a kind of embodiment, for example realizes with the T-shape edge triggered flip flop.
Understandable, in more embodiment of the present invention, also can produce first reference clock signal by a frequency divider, this frequency divider carries out frequency division as Frequency Dividing Factor to the high frequency clock from the outside input of integrated circuit with the nominal frequency of 2 times high frequency crystal oscillator, equally also can output duty cycle is 1 0.5 hertz first reference clock.
The input of counter 33 comprises 0.5 hertz clock signal of enabling signal, 32 generations of second frequency divider and the low-frequency oscillation clock that low frequency RC oscillator 34 produces, and is output as count completion signal that feeds back to SOC and the frequency information of giving tri-frequency divider 35.Counter 33 is counted the frequency information that obtains low-frequency oscillation by using described first reference clock to described oscillator signal, and the frequency information of low-frequency oscillation clock is imported tri-frequency divider 35.Wherein a kind of working method of counter 33 is following after receiving enabling signal, high level part at the one-period of first reference clock is counted the low-frequency oscillation clock that low frequency RC oscillator 34 produces, produce after counting finishes and count the signal that finishes, and count results is preserved.
Be a kind of circuit implementation that adopts the counter 33 of Verilog hardware description language design below, wherein rst_n is an enabling signal, clk_i is the low-frequency clock that low frequency RC oscillator 34 produces, and enable is the 0.5 hertz frequency clock that second frequency divider 32 produces.
module?counter(rst_n，clk_i，enable，finish，result)；
parameter?WIDTH＝10；
parameter?UDLY＝1；
input?rst_n；
input?clk_i；
input?enable；
output finish；
output[WIDTH-1:0]result；
reg[1:0]enable_p；
always@(posedge?clk_i?or?negedge?rst_n)
begin
if(rst_n＝＝1′b0)
enable_p＜＝#UDLY?2′b00；
else
enable_p＜＝#UDLY{enable_p[0]，enable}；
end
reg?finish；
always@(posedge?clk_i?or?negedge?rst_n)
begin
if(rst_n＝＝1′b0)
finish＜＝#UDLY?1′b0；
else?if(enable_p＝＝2′b?10)
finish＜＝#UDLY?1′b1；
end
reg[WIDTH:0]pointer；
always@(posedge?clk_i?or?negedge?rst_n)
begin
if(rst_n＝＝1′b0)
pointer＜＝#UDLY?′h0；
else?if(enable_p[0]＝＝1′b1)
pointer＜＝#UDLY?pointer+1′b1；
else
pointer＜＝#UDLY?′h0；
end
reg[WIDTH-1:0]result；
always@(posedge?clk_i?or?negedge?rst_n)
begin
if(rst_n＝＝1′b0)
result＜＝#UDLY′h02；
else?if(enable_p＝＝2′b10)
result＜＝#UDLY?pointer；
end
endmodule//counter
More than shown in the circuit implementation only be a kind of possible implementation of counter 33 among the present invention program, not in order to the restriction the present invention.
Low frequency RC oscillator 34 produces the low-frequency oscillation clock, and wherein R represents resistance, and C represents electric capacity.Work clock when this low-frequency oscillation clock can be used as the SOC standby on the one hand can be used as the clock source that produces accurate clock in addition on the one hand.Low frequency RC oscillator is a kind of very ripe basic circuit, and the low frequency RC oscillator 34 of present embodiment can be a kind of low frequency RC oscillator in the known technology.The required precision of timing reference clock is depended in the selection of its frequency of oscillation.For example, if the required precision of timing reference clock is lower than 40/1000000ths, its frequency will be higher than 40/1000000ths inverse so, i.e. 25 KHz, consider that again low frequency RC oscillator is subjected to the influence (general frequency drift can not surpass ± 50%) of semiconducter process drift, therefore can be chosen as 50 KHz with the frequency of low frequency RC oscillator.
The function of tri-frequency divider 35 is exactly after startup, and the low-frequency clock that low frequency RC oscillator 34 is produced carries out frequency division with the three frequency division factor, produces the second required 1 hertz reference clock of accurate timing.The three frequency division factor wherein can be the frequency information of counter 33 itself.Tri-frequency divider 35 can adopt and first frequency divider, 31 identical circuit design.First frequency divider, second frequency divider, the Frequency Dividing Factor of tri-frequency divider and output clock can adopt other to meet the design form that the present invention program requires, and are not limited in the numerical value of mentioning in the foregoing description.
Understandable, in the more embodiment of the present invention, the three frequency division factor also can be arbitrary frequency division value of the resulting frequency information of counter or frequency multiplication value etc.When specific implementation, for example can between counter and tri-frequency divider, dispose a frequency divider, frequency information is carried out frequency division obtain the three frequency division factor, perhaps obtain directly offering the tri-frequency divider use after the three frequency division factor by the data of the processing unit with disposal ability according to counter output.
Further, the SOC of present embodiment can also comprise control unit, be used for after described counter obtains described count results, the high frequency crystal oscillator of controlling described first frequency divider, second frequency divider, counter and/or SOC periphery enters non operating state (quitting work).Can play the effect of saving power consumption like this; And meanwhile, tri-frequency divider still can use three frequency division factor pair oscillator signal to carry out frequency division and obtain second reference clock.
Because the low-frequency oscillation clock that SOC running medium and low frequency RC oscillator produces is to drift about with SOC internal temperature and voltage drift, therefore can calibrate to guarantee accurate clock stable the three frequency division factor of tri-frequency divider 35 in good time.The specific implementation block diagram of the SOC that the embodiment of the invention three proposes as shown in Figure 4, on the basis of embodiment two, further increased automatic alignment unit, be used for realizing the in good time three frequency division of the calibration automatically factor, this automatic alignment unit comprises four-divider 36 and calibrates start-up control device 37 automatically:
Four-divider 36 can adopt with first and realize to the identical structure of tri-frequency divider, its Frequency Dividing Factor (hereinafter referred to as the 4th Frequency Dividing Factor) can be the constant that preestablishes or receive from the outside, its numerical value can be by the alignment time interval determination of maximum, if be spaced apart 64 seconds such as the maximum alignment time, then the 4th Frequency Dividing Factor is chosen as 128.It is exactly the 4th Frequency Dividing Factor that receives from the outside that alignment time shown in Fig. 4 is selected signal (select) at interval.Four-divider 36 effects are exactly a timer, behind the enable signal enable (counting that is counter 33 is finished index signal finish) that receives from counter 33, reception is from 1 hertz of reference clock signal of tri-frequency divider 35, with the 4th Frequency Dividing Factor 1 hertz of reference clock signal is carried out frequency division, the frequency division result (pointer) who obtains exports automatic calibration start-up control device 37 to as time interval signal (timer).
Automatically the input signal of calibration start-up control device 37 comprises rst_n, enable, timer, clk_i and clk_o, connects the count completion signal of enabling signal, counter 33, time interval signal, high-frequency crystal oscillating clock signal and 1 hertz of reference clock signal of four-divider 36 outputs respectively.Output signal is enable_osc and enable_div12, is used as the hardware-initiated signal of high frequency crystal oscillator and the work enable signal of first and second frequency divider respectively.Its operation principle is as follows: will be from the count completion signal of counter 33 as enable signal, automatically calibration start-up control device 37 is after receiving enable signal, when the time interval signal that receives from four-divider 36, the hardware-initiated signal of using 1 hertz of reference clock signal from tri-frequency divider 35 to produce high frequency crystal oscillator is sent to high frequency crystal oscillator; The work enable signal of using high-frequency crystal oscillating clock signal from high frequency crystal oscillator to produce first and second frequency divider exports first frequency divider 31 and second frequency divider 32 to, makes win frequency divider 31 and second frequency divider 32 change operating state into.
Conclusion is got up, and the implement device of reference clock shown in Figure 4 is exactly on the basis of Fig. 3, further comprises four-divider and automatic start-up control device;
Described four-divider will be from the count completion signal of counter as enable signal, four-divider is after receiving enable signal, reception is 1 hertz of reference clock signal from the frequency of tri-frequency divider, with the 4th Frequency Dividing Factor that preestablishes or receive from the outside 1 hertz of reference clock signal is carried out frequency division, the generation time blank signal exports automatic calibration start-up control device to;
Described automatic calibration start-up control device will be from the count completion signal of counter as enable signal, automatically calibration start-up control device is after receiving enable signal, when the time interval signal that receives from four-divider, the hardware-initiated signal of using 1 hertz of reference clock signal from tri-frequency divider to produce high frequency crystal oscillator is sent to high frequency crystal oscillator; The work enable signal of using high-frequency crystal oscillating clock signal from high frequency crystal oscillator to produce first and second frequency divider exports first frequency divider and second frequency divider to, makes win frequency divider and second frequency divider change operating state into.
For the convenience that designs, first to fourth frequency divider adopts identical structure in design.Be a kind of circuit that adopts first to fourth frequency divider of Verilog hardware description language design below, wherein rst_n is an enabling signal, enable is an enable signal, divisor is a Frequency Dividing Factor, clk_i is an input clock, clk_o is the output clock behind the frequency elimination, and pointer is the counting pointer in frequency division or the counting process.
module?divider(rst_n，enable，divisor，clk_i，clk_o，pointer)；
parameter?WIDTH＝10；
parameter?UDLY＝1；
input?rst_n；
input?enable；
input?clk_i；
output?clk_o；
input[WIDTH-1:0]divisor；
output[WIDTH-1:0]pointer；
wire [WIDTH-1:0]divisor；
reg[WIDTH-1:0]pointer；
always@(posedge?clk_i?or?negedge?rst_n)
begin
if(rst_n＝＝1′b0)
pointer＜＝#UDLY?′h0；
else?if((enable＝＝1′b1)&&(pointer＜divisor-1))
pointer＜＝#UDLY?pointer+1′b1；
else
pointer＜＝#UDLY′h0；
end
reg?clk_o；
always@(posedge?clk_i?or?negedge?rst_n)
begin
if(rst_n＝＝1′b0)
clk_o＜＝#UDLY?1′b0；
else?if(enable＝＝1′b1)
clk_o＜＝#UDLY?pointer＜divisor＞＞1；
else
clk_o＜＝#UDLY?1′b0；
end
endmodule//divider
More than shown in the circuit implementation only be among the present invention program first frequency divider 31 to a kind of possible implementation of four-divider 36, not in order to the restriction the present invention.
The handling process of reference clock generation device 212 generation reference clocks shown in Figure 4 comprises the steps: as shown in Figure 5
Step 501: power on to SOC.
Step 502: start low frequency RC oscillator 34.
Step 503: start high frequency crystal oscillator.
Step 504: by software startup first frequency divider 31, second frequency divider, 32 sum counters 33, they are started working, and calculate the required Frequency Dividing Factor of second frequency divider, and signal feedback are finished in calculating given SOC.
Step 505:SOC starts tri-frequency divider 35 after receiving the count completion signal that counter 33 feeds back, and the Frequency Dividing Factor that counter 33 is brought is preserved, and produce 1 hertz of required reference clock of accurate timing.
After this, in order to reduce power consumption, SOC can place non operating state with first frequency divider 31, frequency-halving circuit 32 sum counters 33 and high frequency crystal oscillator, avoids their work to produce unnecessary power consumption.Like this, even if forbid falling high frequency crystal oscillator, the low-frequency oscillation clock that low frequency RC oscillator 34 produces exports tri-frequency divider 35 to, the Frequency Dividing Factor that tri-frequency divider 35 has been preserved according to counter 33 carries out frequency division to the low-frequency oscillation clock and obtains reference clock, reference clock generation device 212 still can carry out accurate timing like this, thereby need not the high frequency crystal oscillator oscillatory work when reaching the SOC holding state, the little purpose of power consumption when realizing the SOC stand-by operation.
In order to realize the function of calibration in good time, can further include after the step 505:
Step 506: four-divider enables the back and carries out timing according to the Frequency Dividing Factor of determining at interval according to the maximum alignment time, automatically calibration start-up control device is selected signal to remove to open high frequency crystal oscillator at interval according to the alignment time and is enabled first and second frequency divider, and go to step 503, repeated execution of steps 503 to 505, the realization certain interval of time is calibrated Frequency Dividing Factor automatically.
212 of reference clock generation devices shown in Figure 3 can realize that step 501 except that step 506 is to 505.
Can sum up the realization flow of the reference clock that the embodiment of the invention three proposes according to above description, specifically comprise the steps: as shown in Figure 6
Step 601: be re-used as Frequency Dividing Factor after the nominal frequency of the high frequency clock that high frequency crystal oscillator is produced multiply by 2, to described high frequency clock frequency division, output duty cycle is that 1 frequency is 0.5 hertz a clock signal;
Step 602: in described duty ratio is that 1 frequency is the high level part of one-period of 0.5 hertz clock signal, the low-frequency oscillation clock that low frequency RC oscillator produces is counted, described high level partly finishes then to count to be finished, and count results is preserved as the three frequency division factor;
Step 603: the low-frequency oscillation clock that produces according to described three frequency division factor pair low frequency RC oscillator carries out frequency division, produces and export 1 hertz reference clock.
Preferably, described step 601 can be divided into:
Step 601a: receive the high frequency clock of high frequency crystal oscillator generation and the nominal frequency of described high frequency clock, with described nominal frequency described high frequency clock is carried out frequency division, output frequency is 1 hertz a clock signal;
Step 601b: described 1 hertz clock signal is carried out two divided-frequency, and output duty cycle is 1, frequency is 0.5 hertz clock signal.
Alternatively, after the described step 603, further comprise:
Step 604: with the 4th Frequency Dividing Factor 1 hertz of reference clock signal is carried out frequency division, the generation time blank signal;
Step 605: the hardware-initiated signal that produces high frequency crystal oscillator with 1 hertz of reference clock signal when receiving time interval signal is sent to high frequency crystal oscillator, and goes to described step 601.
The high frequency clock that technical scheme of the present invention utilizes high frequency crystal oscillator to produce, obtain the Frequency Dividing Factor of the reference clock of 1 hertz frequency by SOC internal hardware circuit, thereby under the situation that does not need low frequency crystal oscillator, obtain 1 hertz frequency reference clock accurately, can realize the effect of calibration in good time simultaneously as required.
The effect that the present invention is the most useful is exactly to save two low frequency crystal oscillator pins that are equipped with for low frequency crystal oscillator among the SOC, realize that for SOC still less the pin package product provides possibility on the one hand, can make SOC under same number of pins, realize more function in addition on the one hand.Simultaneously, in multimedia processor SOC uses, can save an external low frequency crystal oscillator and the required components and parts of application circuit thereof, can effectively reduce the BOM cost of multimedia processor SOC application product, improve the SOC competitiveness of product in market.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. an integrated circuit is characterized in that, comprising: first frequency unit, counter, oscillator signal produce the circuit and second frequency unit;
Described first frequency unit is used for obtaining first reference clock by the external timing signal from the outside input of described integrated circuit is carried out frequency division;
Oscillator signal produces circuit and is used to produce an oscillator signal;
Counter is used for by using described first reference clock described oscillator signal to be counted to get the frequency information of described oscillator signal;
Described second frequency unit is used for according to the Frequency Dividing Factor that obtains according to described frequency information described oscillator signal being carried out frequency division and obtains second reference clock.
2. integrated circuit according to claim 1 is characterized in that, described first frequency unit comprises first frequency divider and second frequency divider;
Described first frequency divider is used for obtaining a clock signal by using a Frequency Dividing Factor that the external timing signal from the outside input of described integrated circuit is carried out frequency division;
Described second frequency divider is used for carrying out two divided-frequency by the clock signal that described first frequency divider is obtained and obtains first reference clock signal.
3. integrated circuit according to claim 1 is characterized in that, described first frequency unit is a frequency divider, is used for obtaining first reference clock by using a Frequency Dividing Factor that the external timing signal from the outside input of described integrated circuit is carried out frequency division.
4. integrated circuit according to claim 1, it is characterized in that, described integrated circuit also comprises control unit, be used for after described counter obtains described frequency information, the clock generating unit that is used to produce described external timing signal of controlling described first frequency unit, counter and/or integrated circuit outside enters non operating state.
5. integrated circuit according to claim 4, it is characterized in that, this integrated circuit further comprises: automatic alignment unit is used for controlling described first frequency unit, counter and described clock generating unit and enters operating state behind predetermined interval of calibration.
6. according to each described integrated circuit of claim 1 to 5, it is characterized in that described external timing signal is a high frequency clock signal, described oscillator signal is an oscillating signal.
7. a method that obtains reference clock in integrated circuit is characterized in that, described integrated circuit comprises that first frequency unit, counter, oscillator signal produce the circuit and second frequency unit, and described method comprises:
Described first frequency unit obtains first reference clock by the external timing signal from the outside input of described integrated circuit is carried out frequency division;
Counter counts to get the frequency information of described oscillator signal by an oscillator signal that uses described first reference clock that described oscillator signal is produced;
Described second frequency unit carries out frequency division according to the Frequency Dividing Factor that obtains according to described frequency information to described oscillator signal and obtains second reference clock.
8. method according to claim 7 is characterized in that, described first frequency unit comprises first frequency divider and second frequency divider;
Described first frequency unit is described to be obtained first reference clock and specifically comprises by the external timing signal from the outside input of described integrated circuit being carried out frequency division:
Described first frequency divider obtains a clock signal by using a Frequency Dividing Factor that the external timing signal from the outside input of described integrated circuit is carried out frequency division;
Described first frequency divider carries out two divided-frequency by the clock signal that described first frequency divider is obtained and obtains first reference clock signal.
9. method according to claim 7, it is characterized in that described method also comprises after obtaining the frequency information of described oscillator signal: the clock generating unit that is used to produce described external timing signal of controlling described first frequency unit, counter and/or integrated circuit outside enters non operating state.
10. method according to claim 9, it is characterized in that described method also comprises: control described first frequency unit, counter and/or described clock generating unit and enter operating state behind predetermined interval of calibration after the clock generating unit that is used to produce described external timing signal of control described first frequency unit, counter and/or integrated circuit outside enters non operating state.
11., it is characterized in that described external timing signal is a high frequency clock signal according to each described method of claim 7 to 10, described oscillator signal is an oscillating signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101715392A CN102006056A (en) | 2009-08-28 | 2009-08-28 | Integrated circuit and method for obtaining reference clock in integrated circuit |
| PCT/CN2010/074530 WO2011023030A1 (en) | 2009-08-28 | 2010-06-25 | Integrated circuit and method for acquiring reference clock in integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101715392A CN102006056A (en) | 2009-08-28 | 2009-08-28 | Integrated circuit and method for obtaining reference clock in integrated circuit |
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| Publication Number | Publication Date |
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| CN102006056A true CN102006056A (en) | 2011-04-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101715392A Pending CN102006056A (en) | 2009-08-28 | 2009-08-28 | Integrated circuit and method for obtaining reference clock in integrated circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102006056A (en) |
| WO (1) | WO2011023030A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104247269A (en) * | 2012-08-01 | 2014-12-24 | 英特尔公司 | Integrated non-volatile monotonic counters |
| CN109061265A (en) * | 2018-08-31 | 2018-12-21 | 无锡华润矽科微电子有限公司 | Unused time controllable multimeter control circuit |
| CN113746477A (en) * | 2021-08-13 | 2021-12-03 | 武汉精测电子集团股份有限公司 | Precise timing method and device and signal vacancy reservation method and device |
| CN114785342A (en) * | 2022-04-25 | 2022-07-22 | 厦门码灵半导体技术有限公司 | Low-frequency high-precision oscillator for system-on-chip SOC and system-on-chip SOC |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105117200B (en) * | 2015-06-30 | 2018-01-05 | 广西科技大学 | A kind of counter IP kernel being connected with microprocessor of 16 bit application system and its method for realizing rolling counters forward control |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2329795B (en) * | 1997-09-27 | 2002-09-25 | Nec Technologies | High resolution clock reconstruction for use in a mobile telecommunication device |
| DE10029421C2 (en) * | 2000-06-15 | 2002-07-11 | Infineon Technologies Ag | Calibration device and method for clock generation on an integrated circuit |
| JP2006215618A (en) * | 2005-02-01 | 2006-08-17 | Seiko Epson Corp | Clock generation circuit |
| CN100444641C (en) * | 2005-11-11 | 2008-12-17 | 北京中星微电子有限公司 | Clock Recovery System for Multimedia System |
-
2009
- 2009-08-28 CN CN2009101715392A patent/CN102006056A/en active Pending
-
2010
- 2010-06-25 WO PCT/CN2010/074530 patent/WO2011023030A1/en not_active Ceased
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104247269A (en) * | 2012-08-01 | 2014-12-24 | 英特尔公司 | Integrated non-volatile monotonic counters |
| CN104247269B (en) * | 2012-08-01 | 2017-05-24 | 英特尔公司 | Integrated non-volatile monotonic counters |
| CN109061265A (en) * | 2018-08-31 | 2018-12-21 | 无锡华润矽科微电子有限公司 | Unused time controllable multimeter control circuit |
| CN109061265B (en) * | 2018-08-31 | 2024-03-26 | 华润微集成电路(无锡)有限公司 | Universal meter control circuit with controllable shutdown time |
| CN113746477A (en) * | 2021-08-13 | 2021-12-03 | 武汉精测电子集团股份有限公司 | Precise timing method and device and signal vacancy reservation method and device |
| CN113746477B (en) * | 2021-08-13 | 2025-02-11 | 武汉精测电子集团股份有限公司 | Precise timing method, device and signal slot reservation method and device |
| CN114785342A (en) * | 2022-04-25 | 2022-07-22 | 厦门码灵半导体技术有限公司 | Low-frequency high-precision oscillator for system-on-chip SOC and system-on-chip SOC |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2011023030A1 (en) | 2011-03-03 |
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