CN101908200A - Drawing processing system and method with power gate control function - Google Patents

Abstract

The invention provides a drawing processing system with a power gating function and a power gating method. The power gating method is suitable for a graphics processing unit, wherein the graphics processing unit is provided with a unified shader unit, and the unified shader unit comprises a plurality of shaders. The power supply gating method comprises the following steps: drawing a plurality of front pictures; calculating the number of first operation shaders for drawing each front picture and a corresponding picture speed; determining a second number of operating shaders for drawing a next frame after the front frames according to the first number of operating shaders of each front frame and the corresponding frame speed; and starting the corresponding shaders through one or more power gating elements according to the number of the second operation shaders. A graphics processing unit with improved power gating functions can achieve the purpose of saving power consumption according to the requirements of various graphics applications.

Description

Drawing processing system and method with power gating function

technical field

The present invention relates to drawing processing, in particular to a drawing processing system with power gate control function and a power gate control method, which dynamically predicts the number of shaders to be operated according to the change of picture speed.

Background technique

In general, drawing applications include complex and high-detail graphics drawing, such as: three-dimensional (3D) drawing, and in order to meet the current increasing demand in this regard, the graphics processing unit ( graphics processing unit (GPU) is used to process a large number of calculations to display various objects, and therefore consumes a lot of power. Furthermore, for battery-powered portable devices, such as mobile phones, since power consumption is a particularly important issue, it is necessary to reduce the power consumption generated by the graphics processing unit in the mobile phone.

In electronic components, the sources of general power consumption mainly include: dynamic power consumption caused by power supply voltage and operating frequency, and static power consumption caused by leakage loss. With the development of semiconductor process technology, static power consumption caused by leakage loss has become a major problem. Taking the process below 65 nanometers (65nm) as an example, more than 40% of the power consumption is caused by leakage loss.

Known, such as clock gating (clock-gating) technology or dynamic voltage frequency modulation (dynamic voltage and frequency scaling, DVFS) technology, is a commonly used power saving method, both of which can effectively reduce dynamic power consumption, But it does not help to reduce leakage loss, or the help is limited. In addition, other known methods, such as power-gating technology, configure the power-gating element on the entire graphics processing unit, and control the power supply of the entire graphics processing unit through the power-gating element, but lack elasticity. Alternatively, a power gating element is configured in each of the internal elements. When a component is idle, the power supply to the component is turned off through the corresponding power gate control component, thereby simultaneously reducing dynamic and static power consumption. However, this power gating mechanism requires an additional control circuit for turning on or off the power supplied to each device, so there is still power consumption. In addition, when performing the power gating function, additional time (overhead) is required to restore power to each component, making the known power gating mechanism time-consuming and inefficient.

Therefore, there is a need for a graphics processing unit with an improved power gating function to achieve the purpose of saving power consumption according to the requirements of various graphics applications.

Contents of the invention

An embodiment of the present invention provides a graphics processing system with a power gating function, including a graphics processing unit and a driver. The graphics processing unit includes an integrated shader unit and one or more power gating elements. The integrated shader unit includes a plurality of shaders. These shaders are used to draw multiple front frames. The one or more power gating elements are coupled to the shaders for activating corresponding shaders according to the second number of operating shaders. The driver is coupled to the graphics processing unit, calculates a first number of operating shaders for drawing each previous frame and a corresponding frame speed, and according to the number of first operating shaders of each previous frame and the corresponding The frame speed is used to determine a second number of operating shaders for drawing the next frame after the previous frames.

On the other hand, an embodiment of the present invention provides a graphics processing system with a power gating function, including a graphics processing unit and a driver. The graphics processing unit includes an integrated shader unit and one or more power gating elements. The integrated shader unit includes a plurality of shaders. These shaders are used to draw multiple front frames. The one or more power gating elements are coupled to the shaders for activating corresponding shaders according to the second number of operating shaders. The driver is coupled to the graphics processing unit, calculates a first number of operating shaders for drawing each previous frame and a corresponding frame speed, and according to the number of first operating shaders of each previous frame and the corresponding The frame speed is used to determine a second number of operating shaders for drawing the next frame after the previous frames.

The above method of the present invention dynamically predicts the number of shaders to be operated according to the change of the frame speed, and also achieves the purpose of saving power consumption according to the requirements of various drawing applications.

Description of drawings

FIG. 1 is a schematic diagram showing a power gating method of a graphics processing system according to the present invention.

FIG. 2 is a block diagram showing a graphics processing unit according to an embodiment of the invention.

FIG. 3 shows a graphics processing system with a power gating function according to an embodiment of the present invention.

FIG. 4 is a flowchart showing a power gating method according to an embodiment of the invention.

FIG. 5 is a block diagram showing a graphics processing unit according to another embodiment of the present invention.

FIG. 6 is a block diagram showing a graphics processing unit according to another embodiment of the present invention.

Figure number:

302～graphic processing unit;

304～driver;

308～arbiter;

310～command processor;

312～application programming interface;

314, 316 ~ application program;

318～memory corresponding input/output;

320～integrated shader unit;

320A, 320B, 320C, 320D～shaders;

328A, 328B, 328C, 328D～power gating components;

Vdd ~ voltage source; and

Ck ~ clock.

Detailed ways

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1 is a schematic diagram showing a power gating method of a graphics processing system according to the present invention.

In the embodiment of FIG. 1 , a power gating control circuit is added to a graphics processing unit 102 , so that the graphics processing unit 102 has a power gating function. Further, before the graphics processing unit 102 draws a frame, a driver 104 is used to determine a frame rate (frame rate per second, FPS) required by the frame in advance to represent the drawing work of the frame quantity. Therefore, the driver 104 controls the power on and off of the relevant functional elements in the graphics processing unit 102 according to the drawing workload of the picture, so as not to affect the user and the drawing performance (for example: the fluency of the picture presented) ) under the premise of improving the overall power consumption of the graphics processing unit 102 .

Specifically, in one embodiment, when the graphics processing unit 102 completes the drawing operation of a frame, the driver 104 calculates the frame speed corresponding to the frame to determine the frame required for the next frame. Velocity (shown by arrow 106). Then, before the graphics processing unit 102 performs the drawing operation of the next frame, the driver 104 controls the graphics processing unit 102 according to the frame speed of the next frame, for example: setting the power supply of relevant functional elements On and off (as shown by arrow 108).

In other embodiments, a plurality of frame speeds corresponding to previous frames can be used to determine the required frame speed of the next frame.

FIG. 2 is a block diagram showing a graphics processing unit 202 according to an embodiment of the present invention.

Referring to FIG. 2 , the graphics processing unit 202 has a unified shader unit 220 (unified shader unit), and the unified shader unit 220 is a multi-processor capable of processing multiple instructions within a single clock. The integrated shader unit 220 includes multiple shader processors (shader processors or shader cores), such as 220A, 220B, 220C and so on. Each shader can be a vector (vector) and scalar (scalar) architecture, or a multi-value (multiple scalar) very long instruction set (very long instruction word, VLIW) architecture, and has a corresponding temporary memory files and instruction cache memory. Furthermore, each shader executes various shader programs and is responsible for performing vertex shader and pixel shader operations to draw each frame. In addition, the graphics processing unit 202 further includes: a fixed-function geometry stage (fixed-function geometry stages) 204, a fixed-function fragment stage (fixed-function fragment stages) 206, an arbiter 208 and a command processor 210 .

Specifically, the fixed-function geometry stage 204 includes a clipper 212 , a primitive assembly 214 and a streamer 216 . In this pipeline stage, the stream receiver 216 receives vertex data of a 3D object and sends it to the shader. Afterwards, the shaders 220A, 220B, and 220C execute related shading programs to determine the properties of the vertex data of the 3D object, so as to convert the 3D object into a picture displayed on the screen. Next, the primitive grouping unit 214 performs geometric grouping to group vertices into polygons, such as triangles. The clipper 212 eliminates triangles outside the viewable area.

Further, the fixed function segment stage 206 includes a triangle building unit 222, a segment generation unit 224, a hierarchical depth processing unit 226, a depth/template (Z/stencil) testing unit 228, an interpolation unit 230 and a Rendering unit 232 . In this pipeline stage, the triangle building unit 222 performs face-culling to remove undisplayable triangles, and calculates edge equations of the triangles. The fragment generation unit 224 provides a triangle fragment generation function for calculating pixels to be displayed. The hierarchical depth processing unit 226 is optionally configured in the fixed-function fragment stage 206 to discard triangles or out-of-view fragments, and may discard entire fragment blocks at once. The depth/stencil test unit 228 uses the depth buffer and the stencil buffer to determine and discard hidden segments. The interpolation unit 230 interpolates the perspective-corrected triangle attributes to generate segment attributes. Subsequently, the pixel rendering operation is performed by the rendering unit 232 . In an embodiment, the depth/stencil testing unit 228 may also be configured after the rendering unit 232 .

In operation, the command processor 210 is used for receiving various drawing commands, and monitoring and setting the power states of the shaders. The arbiter 208 performs thread scheduling according to various drawing commands, and distributes the drawing commands to each shader for 3D drawing operations. Since the integrated shader unit 220 is responsible for a large number of graphics operations, it becomes the bottleneck of the power consumption of the entire graphics processing unit 202 . Further, because the drawing workload required for each frame is different, each shader can be controlled by power gating, for example, the power gating elements of the shaders 220A, 220B, and 220C can be controlled separately. The action of turning on or off. In this way, the dynamic power consumption or leakage loss of the graphics processing unit 202 can be effectively reduced, so that the overall power consumption of the graphics processing unit can be significantly reduced without affecting the execution performance of application programs.

FIG. 3 is a block diagram showing a graphics processing system with a power gating function according to an embodiment of the present invention.

Referring to FIG. 3 , the graphics processing system includes a graphics processing unit 302 and a driver 304 . In the embodiment shown in FIG. 3 , the graphics processing unit 302 includes an integrated shader unit 320 having four shaders 320A, 320B, 320C and 320D for rendering multiple frames. Similar to the unified shader unit 220 shown in FIG. 2 , the unified shader unit 320 is a multiprocessor capable of processing multiple instructions in a single clock Ck. Further, the graphics processing unit 302 includes four power gating elements 328A, 328B, 328C and 328D, respectively coupled to each shader. The power gating elements are used to enable or disable corresponding shaders according to corresponding control signals 330A, 330B, 330C and 330D. The driver 304 is coupled to the graphics processing unit 302, receives and executes various application programs from an application programming interface (application programming interface, API) 312, for example: a first application program 314, a second application program 316 etc., to correspondingly drive the graphics processing unit 302 to perform graphics. The power gating method of the graphics processing system will be described in detail in conjunction with FIGS. 3 and 4 as follows.

FIG. 4 is a flowchart showing a power gating method 40 according to an embodiment of the present invention.

As mentioned above, before the graphics processing unit 302 draws a predetermined frame Frame _n+1 , the driver 304 can use a history-based calculation method to use the previously drawn frames Frame _n , Frame _{n -1} ,..., Frame _n-m+1 frame speed FPS _n , FPS _n-1 ,..., FPS _n-m+1 and the number of shaders S _n , S _n-1 ,..., S _n- Based on _m+1 , it is used to predict the number S _n+1 of shaders that need to be activated when the graphics processing unit 302 draws the predetermined frame Frame _n+1 . Wherein, m represents the number of previous frames used for prediction. Then, the power gating elements are used to turn on or turn off the power of the corresponding shaders, so that the graphics processing unit 302 can operate more efficiently and improve the overall power consumption of the graphics processing system.

Further, the driver 304 drives the graphics processing unit 302 to perform various graphics operations according to the request of each application program. Therefore, the driver 304 can also determine the start and end of drawing the screen through the request of the application program, so as to perform the operation of power gating. For example, the first application program 314 may include a command SwapBuffer to indicate the end of frame drawing, and the application program 316 may include a command ClearBuffer to indicate the end of frame drawing. If the power gating operation is performed during the execution of the above commands, the drawing performance will not be affected.

Referring to Figures 3 and 4, when the driver 304 receives the first application program 314 from the application program interface 312, the driver 304 generates a corresponding command packet, and the memory-mapped I/O (memory-mapped I/O) /O) 318 is sent to a command processor 310 of the graphics processing unit 302 (step S402).

In response to the execution of the command SwapBuffer, which means that the previous frame Frame _n of the predetermined frame Frame _n+1 has been drawn, the driver 304 then calculates the previous frames Frame _n , Frame _n-1 , . . . , the number of shaders S _n , S _n-1 , ..., S _{n-m+1 operated} by Frame n-m+1 and the corresponding frame speed FPS _n , FPS _n-1 , ..., FPS _n-m+1 (step S404).

For example, when m=5, it means that the driver 304 calculates the coloring performed by the first five drawn frames Frame _n , Frame _n-1 , . . . , Frame _n-4 of the predetermined frame Frame n ₊ 1 Number of monitors S _n , S _n-1 , . . . , S _n-4 and corresponding frame speeds FPS _n , FPS _n-1 , . . . , FPS _n-4 .

In addition, the driver 304 operates the number of shaders _{S n} , S _{n-1 ,} ..., S _{n-m +1} and the corresponding _The frame speeds FPS _n , FPS _{n -1 ,} .

More specifically, the driver 304 may determine the number of shaders S _n+ 1 required to draw the predetermined frame Framen ₊₁ according to the following formula:

Wherein, m is the number of these front pictures, S _n , S _n-1 , ..., S _n-m+1 is to draw these front pictures Frame _n , Frame _n-1 , ..., Frame _{n-m+ 1} The number of shaders operated, FPS _n , FPS _n-1 ,..., FPS _n-m+1 are the frames corresponding to the previous frames Frame _m , Frame _n-1 ,..., Frame _n-m+1 Speed, Target_FPS is a target frame speed adjusted according to display requirements, α is a control variable, and n≧m.

Afterwards, when the driver 304 receives the second application program 316 from the application program interface 312 (step S408), in response to the execution of the command ClearBuffer, it means that the predetermined frame Frame _n+1 is started. drawing operation, the driver 304 generates a corresponding command packet according to the number of shaders S _n+1 required to operate for the predetermined frame Frame _n+1 and the current power state of each shader 320A, 320B, 320C, and 320D , for configuring the power on and off of the shaders 320A, 320B, 320C and 320D, and sending the corresponding command packet to the command processor 310 (step S410). In an embodiment, assuming that the number S _n of shaders used by a frame Frame _n before the predetermined frame Frame _n+1 is greater than the number S _n+1 of shaders required to draw the predetermined frame Frame _n+1 , Correspondingly, the power supply of the inactive shader is turned off. Otherwise, the power supply of the active shader is correspondingly turned on.

Next, in response to the command packet, the command processor 310 generates control signals 330A, 330B, 330C, and 330D for turning on or off each power gating element 328A, 328B, 328C, and 328D, thereby setting The shaders 320A, 320B, 320C, and 320D are powered on or off, and an arbiter 308 is notified (step S412 ).

Afterwards, the arbiter 308 can allocate drawing commands according to the activated shaders, and execute the drawing operation of the predetermined frame Frame _n+1 (step S414), for example, tile-based rendering can be performed. way to draw the given frame Frame _n+1 .

In one embodiment, each power gating element includes a transistor. As shown in FIG. 3 , each power gating element includes an NMOS transistor coupled between a voltage source Vdd and each shader, and its gate receives a control signal from the command processor 310 . Therefore, each transistor is turned on or off according to a corresponding control signal to determine whether to provide the voltage source Vdd to each shader.

Furthermore, in operation, each shader 320A, 320B, 320C, and 320D can be individually configured with a texture unit, or share one or more texture units. Thus, each shader 320A, 320B, 320C, and 320D may receive texture data from a texture unit through a respective texture access path 332 , 334 , 336 , and 338 . In this case, the distribution of the power gating components can also be flexibly adjusted according to the configuration of the texture units. In this way, the efficiency of power management can be greatly improved. The above power gating mechanism will be described in detail in conjunction with FIG. 5 and FIG. 6 as follows.

FIG. 5 is a block diagram showing a graphics processing unit 502 according to another embodiment of the present invention.

Referring to FIG. 5 , the graphics processing unit 502 includes an integrated shader unit 520 , local shared memories 512 and 514 , texture units 508 and 510 , global shared memory 516 and a thread processing unit 518 .

In this embodiment, the integrated shader unit 520 has multiple shaders. The shaders include two shader clusters 504 and 506, each using the local shared memory 502 and 514 for drawing. In addition, the shader clusters 504 and 506 are respectively coupled to two texture units 508 and 510 , and the global shared memory 516 is shared by the texture units 508 and 510 . Specifically, each shader cluster includes 8 shaders. The thread processing unit 518 includes two thread sequencers 522 and 524 for thread allocation.

In this case, each shader cluster 504 and 506 may be configured with a power gating element. In this way, turning on or off of each power gating element will enable or disable the corresponding shader cluster. In addition, it is also possible to control the power supply of the regional shared memory and the texture unit to which each shader cluster belongs. Not only the cost of the power gating control circuit is reduced, but also the power consumption caused by the related components around the shader can be saved.

FIG. 6 is a block diagram showing a graphics processing unit 602 according to another embodiment of the present invention.

Referring to FIG. 6 , the graphics processing unit 602 includes an integrated shader unit 620 , a geometry control unit 604 , a shader control unit 606 and a texture unit 608 .

In this embodiment, the unified shader unit 620 has multiple shaders. These shaders include two multi-shader processing units (shader multi-processor) 610 and 612, and the two multi-shader processing units 610 and 612 form a shader cluster, and use the texture unit 608 together for drawing . The geometry control unit 604 and the shader control unit 606 are used for receiving data and assigning drawing tasks. In FIG. 6, each multi-shading processing unit includes 8 shader SPs, I and C caches (cache), multi-thread issue unit MT (multi-thread issue), 2 special function units SFU (Special Function Unit) Function Unit) and the shared memory MEM for drawing operations. Under this architecture, the multi-shading processing units 610 and 612 share the texture unit 608, therefore, these two multi-shading processing units 610 and 612 can be regarded as a power management unit, and the power supply control is performed by the same power gating element . When the power gating element is turned off, the entire shader cluster, ie, MPUs 610 and 612, and the texture unit 608 will be turned off together. Further reduce unnecessary power gating components and power consumption.

Therefore, through the graphics processing system and the power gate control method of the present invention, when performing graphics, the number of shaders to be operated can be dynamically controlled according to the frame speed variation relationship of each frame, thereby reducing unnecessary power consumption.

The method of the present invention, or specific forms or parts thereof, may exist in the form of program codes. The program code may be contained in a physical medium, such as a floppy disk, a CD, a hard disk, or any other machine-readable (such as a computer-readable) storage medium, or a computer program product not limited to an external form, where, when the program code When loaded and executed by a machine, such as a computer, the machine becomes a device for participating in the present invention. The program code may also be transmitted through some transmission medium, such as wire or cable, optical fiber, or any transmission type in which when the program code is received, loaded and executed by a machine, such as a computer, the machine becomes used to participate in the Device of the present invention. When implemented on a general-purpose processing unit, the program code combines with the processing unit to provide a unique device that operates similarly to application-specific logic circuits.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (18)

1. A power gating method, suitable for a graphics processing unit, characterized in that the graphics processing unit has an integrated shader unit, and the integrated shader unit includes a plurality of shaders, and the power gate Control methods include: Draw multiple front screens; calculating the number of a first operating shader for drawing each previous frame and a corresponding frame speed; According to the number of the first operating shaders of each previous frame and the corresponding frame speed, it is used to determine the number of a second operating shader for drawing the next frame after the previous frames; and According to the second number of operating shaders, the corresponding shaders are enabled through one or more power gating elements. 2. The power gating method according to claim 1, wherein said method further comprises: Utilize the activated shader to draw the next frame. 3. The power gating method according to claim 1, wherein said method further comprises: execute a first application; and calculating the first number of active shaders and the corresponding frame speed for each previous frame in response to execution of the first application, wherein the first application corresponds to an end of each previous frame . 4. The power gating method according to claim 1, wherein the step of determining the number of second operating shaders comprises: Before determining the second number of active shaders, a power state of each shader is obtained. 5. The power gating method according to claim 4, wherein the step of starting the shaders comprises: execute a second application; and in response to execution of the second application, generating a command packet for controlling the one or more power gating elements based on the second number of active shaders and the power state of each shader, Wherein, the second application program corresponds to a start of the next screen. 6. The power gating method according to claim 5, wherein the method further comprises: generating one or more control signals in response to the command packet, Wherein, each power gating element is turned on or off by a corresponding control signal. 7. The power gating method according to claim 6, wherein each power gating element comprises a transistor coupled between a voltage source and at least one shader for controlling according to the corresponding The signal determines whether to provide the voltage source to the at least one shader. 8. The power gating method according to claim 1, wherein said shaders comprise a plurality of shader clusters coupled to a plurality of texture units, and wherein each texture unit is coupled to At least one shader cluster is used to enable each power gating element to simultaneously activate a texture unit and the at least one shader cluster coupled thereto. 9. The power gating method according to claim 1, wherein the second number of operating shaders is generated according to the following formula: Wherein, S _n+1 is the number of the second operating shader for drawing the next frame, m is the number of the previous frames, S _n , S _n-1 ,..., S _n-m+1 is The number of first operating shaders for drawing each previous frame, FPS _n , FPS _n-1 , ..., FPS _n-m+1 is the frame speed corresponding to each previous frame, Target_FPS is a target frame speed , α is a control variable and n≥m. 10. A graphics processing system with a power gating function, characterized in that the system comprises: A graphics processing unit including an integrated shader unit and one or more power gating elements, wherein the integrated shader unit includes a plurality of shaders for drawing a plurality of front frames, the one or more a power gating element coupled to the shaders for enabling corresponding shaders according to the second number of operating shaders; and A driver, coupled to the graphics processing unit, calculates a first number of operating shaders for drawing each previous frame and a corresponding frame speed, and according to the number of first operating shaders of each previous frame and the corresponding The frame speed is used to determine a second number of operating shaders for drawing the next frame after the previous frames. 11. The graphics processing system according to claim 10, wherein the graphics processing unit utilizes the activated shader to draw the next frame. 12. The image processing system according to claim 10, wherein when a first application program is executed, in response to the execution of the first application program, the driver calculates the first The number of operating shaders and the corresponding frame speed, and wherein the first application corresponds to an end of each previous frame. 13. The graphics processing system of claim 10, wherein the driver obtains a power state of each shader before determining the second number of active shaders. 14. The graphics processing system according to claim 13, wherein when a second application program is executed, in response to the execution of the second application program, the driver operates according to the number of second operating shaders and The power state of each shader generates a command packet for controlling the one or more power gating elements, and wherein the second application corresponds to a start of the next frame. 15. The graphics processing system according to claim 14, wherein the graphics processing unit comprises: a command processor, coupled to the driver, generating one or more control signals in response to the command packet, Wherein, each power gating element is turned on or off by a corresponding control signal. 16. The graphics processing system as claimed in claim 15, wherein each power gating element comprises a transistor coupled between a voltage source and at least one shader for controlling the corresponding control signal according to the It is determined whether to provide the voltage source to the at least one shader. 17. The graphics processing system of claim 10, wherein the shaders comprise a plurality of shader clusters coupled to a plurality of texture units, and wherein each texture unit is coupled to at least A shader cluster for enabling each power gating element to simultaneously activate a texture unit and the at least one shader cluster coupled thereto. 18. The graphics processing system of claim 10, wherein the second number of operating shaders is generated according to the following formula:

Wherein, S _n+1 is the number of the second operating shader for drawing the next frame, m is the number of the previous frames, S _n , S _n-1 ,..., S _n-m+1 is The number of first operating shaders for drawing each previous frame, FPS _n , FPS _n-1 , ..., FPS _n-m+1 is the frame speed corresponding to each previous frame, Target_FPS is a target frame speed , α is a control variable and n≥m.

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