CN101626009A - Substrate panel - Google Patents

Abstract

The invention relates to a substrate panel, which mainly comprises two or more substrate strips arrayed on the substrate panel, two or more electroplating buses, two or more electroplating serial connecting lines connected between the substrate strips and connecting two adjacent substrate strips, and a current input gate buffer area; the electroplating bus connects the side edge of the substrate panel to the adjacent substrate strip; the current input gate buffer area is arranged on the non-substrate strip part of the substrate panel and is provided with a current buffer frame and two or more than two network cables, the current buffer frame is in cross connection with the electroplating bus, and the network cables are in cross connection with the electroplating serial connection lines and both ends of the network cables are connected to the current buffer frame. Therefore, the current is evenly dispersed to each substrate strip in the electroplating process, the problem of inconsistent thickness of an electroplated layer caused by uneven current density is solved, and instantaneous large current can be buffered and unstable voltage can be relieved to protect the internal circuit of the substrate strip.

Description

Substrate panel

technical field

The invention relates to a printed circuit board, especially a substrate panel.

Background technique

At present, the printed circuit board can be used as a micro-substrate (or referred to as a substrate unit) for carrying chips, and a plurality of micro-substrates arranged in an array are formed in a substrate strip (Substrate Strip). Semiconductor packaging/assembly operations are carried out by substrate strip transfer. In addition, a plurality of substrate strips arranged in an array form a substrate panel (Substrate Panel), so as to facilitate mass production using a printed circuit board process. Usually, before these substrate strips are singulated and separated, the substrate panel will be subjected to an electroplating step in order to plate nickel/gold or other electroplating layers on these substrate strips to prevent oxidation of exposed metal pads and facilitate metal bonding in subsequent processes , such as putting gold wires or bonding solder balls, etc.

Please refer to FIG. 1, a known substrate panel 100 includes two or more substrate strips 110, two or more electroplating bus lines 121 and 122, and two or more electroplating serial lines 130, wherein these The electroplating buses 121 and 122 and the electroplating serial lines 130 are copper circuits on the same circuit layer. The substrate strips 110 are arranged in a matrix in the substrate panel 100 in an integrally connected and uncut manner. The substrate strip adjacent to the current input side edge 101 of the substrate panel 100 is further denoted as 110A. Part of the plating bus 121 connects the current input side edge 101 of the substrate panel 100 to the adjacent substrate strip 110A; part of the plating bus 122 connects the current output side edge 102 of the substrate panel 100 to the adjacent substrate strip 110 . These plating strings 130 connect two adjacent substrate strips 110 . During the electroplating process, the current is conducted to the substrate strips 110A adjacent to the current input side edge 101 through the electroplating bus lines 121, and then the current is conducted in series to the adjacent substrate strips 110 through the electroplating serial lines 130, and finally the current The electroplating bus 122 of the output side edge 102 is led out (as shown by the arrows on the left and right sides of FIG. 1 ) for electroplating. Since the current must be conducted to these substrate strips 110A first, and then to other substrate strips 110 in series, the current density in these substrate strips 110A will be the highest and gradually decrease towards the current output edge 102 . And because the conduction direction of the current is from the current input side edge 101 to the current output side edge 102, so that the current density passing through the substrate strips 110 will gradually decrease as the distance from the current input side edge 101, so the same substrate panel is formed. Depending on the position of the substrate strip 110 within 100 , there may be problems of different plating thickness and plating roughness, thus resulting in poor plating quality. Even in semiconductor packaging/assembly operations, wire bonding failures or poor soldering problems may occur. In addition, during electroplating, large instantaneous current or unstable voltage may cause damage to the internal circuits of the connected substrate strips 110A via the electroplating buses 121 .

Contents of the invention

In view of this, the main purpose of the present invention is to provide a substrate panel that can make the thickness of the electroplating layer consistent and protect the internal circuit of the substrate strip.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. According to a substrate panel disclosed in the present invention, it mainly includes two or more substrate strips, two or more electroplating buses, two or more electroplating serial lines, and a current input gate buffer; the substrate Strip arrays are arranged on the substrate panel, and each substrate strip contains two or more substrate units arranged in an array; the electroplating bus connects the side edge of the substrate panel to adjacent substrate strips; the electroplating serial line is set between the substrate strips and connect two adjacent substrate strips; the current input gate buffer is set on the non-substrate strip part of the substrate panel and has a current buffer frame and two or more network cables, the current buffer A frame is formed on the surface periphery of the substrate panel and cross-connects the electroplating bus, the mesh wire is formed in the current buffer frame and is located between the substrate strips, and the mesh wire cross-connects the electroplating string and connects both ends to the current buffer box.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned substrate panel, the current buffer frame and the electroplating bus may be in a cross-shaped pattern.

In the foregoing substrate panel, the current buffer frame may equally divide the electroplating bus.

In the foregoing substrate panel, the network cable and the electroplating serial line may be in a cross-staggered manner.

In the aforementioned substrate panel, the mesh wires may equally divide the electroplating serial wires.

In the aforementioned substrate panel, the current input gate buffer zone may additionally have two or more electroplating dispersion lines, and the electroplating dispersion lines connect the current buffer frame and adjacent substrate strips.

In the foregoing substrate panel, the electroplating dispersion lines may be arranged in parallel with the electroplating bus lines at equal intervals on the same side of the adjacent substrate strips.

In the aforementioned substrate panel, the side edge of the substrate panel has a current input side edge, and the substrate panel may additionally have a current output side edge arranged parallel to the current input side edge, and the electroplating dispersion lines are only adjacently arranged on the current input side edge and the current output side edge.

In the aforementioned substrate panel, the width of the current buffer frame may be greater than the width of the mesh line.

In the aforementioned substrate panel, the substrate panel may further include an electroplating layer, and the electroplating is formed on the current buffer frame.

In the aforementioned substrate panel, the electroplating layer can be further electroplated and formed on the mesh cable.

In the aforementioned substrate panel, the substrate panel may further include a solder resist layer formed on the surface of the substrate panel and covering the current buffer frame and the network cable.

It can be seen from the above technical solutions that the substrate panel of the present invention has the following advantages and effects:

1. Use the current input gate buffer to cross-connect the electroplating bus and the electroplating series connection, which can evenly disperse the current to each substrate strip during the electroplating process, avoiding the uneven thickness of the electroplating layer caused by uneven current density, and also has the ability to buffer instantaneous large current and Moderate unstable voltage to protect the efficacy of the internal circuit of the substrate strip.

2. Multiple electroplating dispersion lines and electroplating buses are equidistantly connected between the current buffer frame and the substrate strip, which has the effect of increasing the average dispersion of the current and contributes to the uniform distribution of the current density of the substrate strip.

Description of drawings

FIG. 1 is a schematic top view of a known substrate panel;

2 is a schematic top view of a substrate panel according to a specific embodiment of the present invention;

3 is a schematic top view of a substrate strip in a substrate panel according to a specific embodiment of the present invention;

4A is a schematic partial cross-sectional view of a substrate panel according to a specific embodiment of the present invention;

FIG. 4B is a schematic partial cross-sectional view of another variation of the substrate panel according to an embodiment of the present invention.

Explanation of reference signs

100 substrate panel 101 current input side edge

102 current output side edge 110 substrate strip

110A substrate strip 121 plating bus

122 electroplating bus 130 electroplating series connection

200 substrate panel 201 current input side edge

202 current output side edge 203 surface

210 substrate strips 210A substrate strips

211 Substrate unit 212 Metal pad

221 electroplating bus               222 electroplating bus

230 electroplating series connection line 240 current input gate buffer

241 current buffer frame 242 network cable

243 electroplating dispersion line 250 electroplating layer

260 solder mask

Detailed ways

According to a specific embodiment of the present invention, a substrate panel is illustrated in the schematic top view of FIG. 2 and the partial cross-sectional schematic diagram of FIG. 4A .

The substrate panel 200 mainly includes two or more substrate strips 210 , two or more electroplating buses 221 and 222 , two or more electroplating serial lines 230 and a current input gate buffer 240 . Usually, the substrate panel 200 can be a large-sized printed circuit board, and the ratio of the long side to the wide side is approximately equal or not more than twice, such as 1:1, 4:3 or 16:10, etc., and is in the form of a panel form.

The substrate strips 210 are arranged in an array on the substrate panel 200 . As shown in Figure 3, each substrate bar 210 contains two or more substrate units 211 arranged in an array, and each substrate unit 211 can be used as a chip carrier of a semiconductor package/combined structure, and its surface is provided with two or two substrate units. More than one metal pad 212 to be electroplated (as shown in FIG. 4A ). Each substrate strip 210 can be used for semiconductor packaging/assembly operations after singulation. After the finished product is manufactured, the substrate units 211 are further separated into individual units, and each substrate unit 211 can become a semiconductor package/assembled structure. In addition, the substrate panel 200 has a current input side edge 201 and a current output side edge 202 . Usually, the current input side edge 201 and the current output side edge 202 are arranged parallel to each other. Among the substrate strips 210, the substrate strip adjacent to the current input side edge 201 is particularly designated 210A.

Some of the plating buses 221 connect the current input side edge 201 to the adjacent substrate strip 210A, while the rest of the plating buses 222 connect the current output side edge 202 to the adjacent substrate strip 210 . The electroplating strings 230 are disposed between the substrate strips 210 and connect two adjacent substrate strips 210 for conducting current between the connected substrate strips 210 during the electroplating process. More specifically, the electroplating serial lines 230 and the electroplating bus lines 221 and 222 are disposed on the surface 203 of the substrate panel 200 and are made of highly conductive metal, such as copper.

The current input gate buffer area 240 is disposed on a non-substrate strip portion of the substrate panel 200 . “Non-substrate strip portion” means that the substrate panel 200 does not include the peripheral portion of the substrate strips 210 and the gap between the substrate strips 210 . The current input gate buffer 240 has a current buffer frame 241 and two or more network cables 242 . In this embodiment, please refer to FIG. 2 , the width of the current buffer frame 241 may be greater than the width of the network wires 242 . The mesh wires 242 are formed in the current buffer frame 241 to form two or more meshes. Each grid can correspond to each substrate strip 210 , and the grid size can be slightly larger than the size of the corresponding substrate strip 210 , forming a structure similar to a mesh conductive grommet.

The current buffer frame 241 is formed on the periphery of the surface 203 of the substrate panel 200 and cross-connects the plating buses 221 and 222, the network lines 242 are formed in the current buffer frame 241 and are located between the substrate strips 210, and the network lines 242 cross-connects the electroplating serial lines 230 and connects both ends to the current buffering frame 241 . Please refer to FIG. 4A, since the electroplating buses 221 and 222, the electroplating serial lines 230, the current buffer frame 241 and the network wires 242 are located on the same surface 203 of the substrate panel 200, they can be formed on the same circuit layer, so as to Reduce manufacturing costs. In this embodiment, the current buffer frame 241 can be a square-shaped conductive strip, such as a thickened metal frame strip, and its material can be copper. Wherein the width of the current buffer frame 241 can be properly adjusted according to requirements. In this embodiment, the material of the network wires 242 may be the same as that of the current buffer frame 241 . The connection between the two ends of the network cables 242 and the current buffer frame 241 may be T-shaped.

In addition, in this embodiment, please refer to FIG. 2 , the current buffer frame 241 and the electroplating buses 221 and 222 may be in a cross-shaped pattern. Please refer to FIG. 2 , the current buffering frame 241 can equally divide the electroplating buses 221 and 222 . That is to say, the length of these electroplating buses 221 from the current buffer frame 241 to the substrate bar 210A is equal to the length of the current input side edge 201 from the current buffer frame 241 to the substrate panel 200; The length from the buffer frame 241 to the substrate strip 210 is equal to the length of the plating buses 222 from the current buffer frame 241 to the current output edge 202 of the substrate panel 200 . In this embodiment, please refer to FIG. 2 , the mesh wires 242 and the electroplating serial wires 230 may also be in a criss-cross pattern. In this embodiment, please refer to FIG. 2 , the mesh wires 242 can equally divide the electroplating serial wires 230 . That is to say, the lengths of the electroplating series connection lines 230 on both sides of the network lines 242 are the same, so as to achieve the effect of current sharing. Preferably, please refer to FIG. 2 again, the current input gate buffer zone 240 also has two or more electroplating dispersion lines 243, which can connect the current buffer frame 241 and the adjacent substrate strips 210 to increase the current Uniformity of distribution. The plating dispersion lines 243 may not be connected to the current input side edge 201 of the substrate panel 200 . The electroplating dispersion lines 243 and the electroplating bus lines 221 can be arranged in parallel at equal intervals on the same side of the substrate strip 210A, so as to achieve a better input/output current dispersion effect. More preferably, these electroplating dispersion lines 243 are only adjacently arranged at the current input side edge 201 and the current output side edge 202, so the substrate panel 200 has no electroplating dispersion lines 243 at the non-current input/output side edges to connect the The current buffer frame 241 and the substrate strip 210, so that the current dispersed in the current buffer frame 241 will not be conducted to these substrate strips 210A that are prone to generate high current density, but will be conducted to these network lines 242 and then shunted to different substrate strips 210. Therefore, the current buffering frame 241 can exert better high current buffering effect and reduce edge effects.

Preferably, please refer to FIG. 4A, the substrate panel 200 may further include an electroplating layer 250, such as nickel gold (Ni/Au), electroplating is formed on the current buffer frame 241, in other words, the current buffer frame 241 is not covered by a solder mask layer 260. In this embodiment, the electroplating layer 250 can also be formed on the mesh wires 242 . During the electroplating process, the electroplating layer 250 is not only formed on the metal pads 212 in the substrate strips 210A, but also formed on the current buffer frame 241 at the same time. Therefore, the exposed current buffer frame 241 can reduce the influence of the plating edge effect (Edge Effect), so that these substrate strips 210 have better plating quality.

Please refer to FIG. 4B , in another variant embodiment of the substrate panel, it further includes a solder resist layer 260, which is formed on the surface 203 of the substrate panel and covers the current buffer frame 241 and the network lines 242, so in During the electroplating process, the electroplating layer 250 can be economically formed on the metal pads 212 in the substrate strips 210A and 210, thereby reducing the waste of electroplating materials.

When current is conducted to these substrate strips 210A via these electroplating buses 221, the current will first be dispersed in the current buffer frame 241, so that the current will not concentrate on these substrate strips 210A, and the current dispersed in the current buffer frame 241 It will be further conducted to these network wires 242, and the current will be conducted to these electroplating serial lines 230 through these network wires 242, so that the current is evenly distributed to each substrate strip 210, so the current can be transferred by the current buffer frame 241 and these network wires 242 Evenly distributed to avoid excessive current density in the substrate strips 210A adjacent to the current input side edge 201 of the substrate panel 200 . Therefore, the thickness of the plating layer of these substrate strips 210A may be substantially the same as that of the remaining substrate strips 210 . The current buffer frame 241 of the current input gate buffer zone 240 and the network cables 242 can evenly distribute the current to each substrate strip 210 , so as to avoid the problem of inconsistent thickness of the electroplating layer caused by uneven current density.

In addition, once a momentary large current is introduced by these electroplating buses 221 during electroplating, the current can still be dispersed by the current buffer frame 241 and these network cables 242, so the present invention also has the functions of buffering a momentary large current and easing unstable voltage to protect The effect of these substrate strips 210 internal wiring.

The present invention also has the effect of improving the average distribution of current. Since these electroplating dispersion lines 243 and these electroplating bus lines 221 are equidistantly connected to the same side of these substrate strips 210A, so the current can be evenly dispersed to The electroplating dispersion lines 243 and the electroplating bus lines 221 are then input to the substrate strip 210A, so as to improve the effect of uniform current dispersion and contribute to the uniform distribution of the current density of the substrate strip.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention in any form. The scope of the technical solutions of the present invention should be based on the appended claims. Any skilled person familiar with this profession can use the technical content disclosed above to make some changes or modify equivalent embodiments of equivalent changes, but all the content that does not deviate from the technical solution of the present invention, the above implementation can be implemented according to the technical essence of the present invention. Any simple modifications, equivalent changes and modifications made in the examples still belong to the scope of the technical solutions of the present invention.

Claims (12)

1. A substrate panel, characterized in that it comprises: Two or more substrate strips are arranged in an array on the substrate panel, and each substrate strip contains two or more substrate units arranged in an array; two or more plating buses connecting the side edges of the substrate panel to adjacent substrate strips; Two or more electroplating serial lines are arranged between the substrate strips and connect two adjacent substrate strips; and The current input gate buffer is set on the non-substrate strip part of the substrate panel and has a current buffer frame and two or more network cables. The current buffer frame is formed on the surface periphery of the substrate panel and cross-connects the electroplating bus. A mesh wire is formed in the current buffer frame and located between the substrate strips, and the mesh wire cross-connects the electroplating serial wires and connects both ends to the current buffer frame. 2 . The substrate panel according to claim 1 , wherein the current buffer frame and the electroplating bus are in a criss-cross pattern. 3. The substrate panel according to claim 1 or 2, wherein the current buffer frame equally divides the electroplating bus. 4 . The substrate panel according to claim 1 , wherein the network cable and the electroplating serial line are in a criss-cross pattern. 5. The substrate panel according to claim 1 or 4, characterized in that, the network cable equally divides the electroplating series connection. 6. The substrate panel according to claim 1, characterized in that, the current input gate buffer also has two or more electroplating dispersion lines, and the electroplating dispersion lines connect the current buffer frame and adjacent substrate strips . 7. The substrate panel according to claim 6, wherein the electroplating dispersion lines and the electroplating bus lines are arranged in parallel at equal intervals on the same side of adjacent substrate strips. 8. The substrate panel according to claim 6, wherein the side edge of the substrate panel has a current input side edge, and the substrate panel further has a current output side edge arranged in parallel with the current input side edge , and the electroplating dispersion lines are arranged adjacent to the current input side edge and the current output side edge. 9. The substrate panel according to claim 1, wherein the width of the current buffer frame is greater than the width of the network cable. 10. The substrate panel according to claim 1, wherein the substrate panel further comprises an electroplating layer, and the electroplating is formed on the current buffer frame. 11. The substrate panel according to claim 10, wherein the electroplating layer is also formed on the network cable by electroplating. 12. The substrate panel according to claim 1, wherein the substrate panel further comprises a solder resist layer, the solder resist layer is formed on the surface of the substrate panel and covers the current buffer frame and the cable.

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