CN101454979B - Switching circuit - Google Patents
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- CN101454979B CN101454979B CN200780019978.0A CN200780019978A CN101454979B CN 101454979 B CN101454979 B CN 101454979B CN 200780019978 A CN200780019978 A CN 200780019978A CN 101454979 B CN101454979 B CN 101454979B
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Abstract
A switching circuit arrangement (100) comprises a field effect transistor (40) and a circuit (50, 52, 54, 60, 62) for biasing a gate voltage of the field effect transistor (40), in particular for bringing the gate voltage of the field effect transistor (40) below a certain threshold, in particular below a certain positive threshold level. In an embodiment, reverse recovery and gate bounce are mitigated simultaneously. In one embodiment, the biasing circuit includes a biasing diode (52) connected in series to the gate (G) of the field effect transistor (40) to bias the gate voltage of the field effect transistor (40), and a clamping field effect transistor unit (62) connected between the gate (G) of the field effect transistor (40) and the source (S) of the field effect transistor (40) to bring the gate voltage of the field effect transistor (40) below a certain threshold, in particular below a certain positive threshold level.
Description
Technical field
The present invention relates to switching circuit.
Background technology
For lifting high FEEDBACK CONTROL dynamics (dynamics) with for the demand that reduces printed circuit board (PCB) (PCB) space during low voltage and high currents such as voltage regulator module (VRM) or POL (PoL) is used, the high-frequency power transfer is the most seductive solution in essence.
Yet high switching frequency operation is unfavorable for need to keeping high transducer effciency in these are used especially.Therefore, high efficiency is the major obstacle that increases the switching frequency operation.This affects the design guideline of converter conversely significantly, particularly has to keep the switchgear of low conduction resistance and high switch performance.
During VRM and PoL use the most widely converter topology be synchronous buck.In this converter, two power switch loss mechanism are importantly interrelated: the reverse recovery of synchronous rectifier mos field effect transistor (sync MOSFET or sync FET) and grid rebound.Consult Thomas Duerbaum, Tobias Tolle, the article of Reinhold Elferich and Toni Lopez " Quantification of Switching Loss Contributions in Synchronous Rectifier Applications ", the 10th European power electronics and use meeting EPE, in September, 2003, the Toulousc, France, the 786th page.These two power switch loss mechanism are all producing heat among MOSFET and the control MOSFET synchronously, thereby reduce the efficient of converter.
Existence reduces the known solution of reverse recovery by the intelligent driver with self adaptation time lag (dead time) control program.Verified this solution is only effectively worked in integration module.Consult http://www.semiconductors.philips.com/pip/PIP212-12M.html, and Philip Rutter, at the prior art paper " Challenges of Integrated Power Trains " of Intel Symposium 2004 discussion.The solution that another is more recent is consulted WO 2004/114509A1, and the what is called " bulk effect " of having utilized MOSFET to present is although be intended to particularly reduce electromagnetic interference (EMI).Also consult G.M.Dolny, S.Sapp, A.Elbanhaway, the paper of C.F.Wheatley " The influence of body effect and threshold voltage reduction on trench MOSFET body diode characteristics ", ISPSD 2004, the 217th page to 220 pages, or Thomas Duerbaum, Toni Lopez, Reinhold Elferich, the paper of Nick Koper and Tobias Tolle " Third Quadrant Output Characteristics in High Density Trench MOSFETs ", the 11st International Power electronics and motion control meeting EPE-PEMC, in September, 2004, in add, Latvia, the A14370 page or leaf is effectively to eliminate reverse recovery by the series diode that appends to grid circuit.
Based on this intention, the new FET equipment of integrated series diode and MOSFET will become the product of automation industry in single package, be characterised in that low electromagnetic interference switching characteristic.
Above-mentioned solution although alleviated reverse recovery, may worsen the grid rebound.In the situation of this FET equipment, the grid rebound may badly be arrived so that overall power dissipation is more taller than the traditional solution under the high switching frequency application scenarios.
Minimize the appropriate technology of grid rebound, be intended to produce the device structure of a kind of Crss (=Miller feedback capacity) and the low ratio of Ciss (input capacitance of=lump input capacitance or explanation), namely comprise the equipment to the low neurological susceptibility of grid rebound.The Low ESR gate path further helps to minimize this loss effect.
US 5 929 690 has proposed a kind of equipment, it by revise semiconductor process parameter (diode thickness, doping profile ...) utilize " bulk effect " to obtain to optimize, this may trade off such as electric capacity and on-state drain-source resistance R
DS(on) Other related equipment parameter.In this case, US 5 929 690 proposes to reduce the nominal threshold voltage to effectively utilize " bulk effect ".In addition, US 5 929 690 fully ignores in the power MOSFET field can significantly produce switch power loss, specifically the grid rebound effect when reducing threshold voltage with utilization " bulk effect ".So like this, the benefit of " bulk effect " possibly can't compensate the increase of the loss relevant with the grid rebound of power MOSFET in the prior art.
About technical background of the present invention, finally reference:
A kind of US 6,421 262 B1 of the active switch from controlling have been proposed;
Adopt timing controlled with US 6,819 149 B2 of the voltage ring of the node voltage that minimizes half-bridge, this timing controlled (spurious) straight-through (shoot-through) that cause looking genuine, thus excess loss in being switched circuit, produced to cause reducing the voltage ring;
Exclusively be applicable to the US 2005/00471777A1, particularly forward converter of the AC (interchange)/DC (direct current) converter for power main.
Summary of the invention
Especially, the purpose of this invention is to provide a kind of improved switching circuit.This invention is limited by independent claims.Favourable execution mode is limited by dependent claims.
Special execution mode causes oppositely recovering and the grid rebound alleviates simultaneously, avoids above-mentioned situation when ideal.
Embodiments of the present invention are mainly based at least one the low side grid circuit for the loss of suppressing the loss relevant with reverse recovery and being correlated with the grid rebound.For reaching this purpose, drive at least one grid voltage biasing circuit that synchronous rectifier (SR) mos field effect transistor (MOSFET) enters time threshold areas and avoids thus oppositely recovering, prevent that with at least one power apparatus does not expect that the clamp switch circuit that switches combines when node voltage increases.
Different from traditional scheme, special execution mode of the present invention provides the mode of avoiding simultaneously oppositely recovery and grid rebound.As a result, can reduce energy loss and electromagnetic interference (EMI).In addition, no longer need to minimize the low ohm gate drivers of reverse recovery, also do not need to have the severe time-controlled drive scheme of eliminating reverse recovery.The solution that proposes causes the good switching mode performance that limits, and wherein can determine simply the maximum voltage peak value of line balance converter, and this helps to optimize the avalanche breakdown level of switch.
The very soft switch circuit of synchronous rectification that proposes can be integrated in the single package, does not need the pin that adds.Multi-chip module also can benefit from the present invention.
In more detail, at least one clamp switch at the grid circuit place of synchronous rectification (low side) MOSFET, provide low impedance path between gate terminal and source terminal, risen in the dv/dt transition to prevent grid voltage, dv/dt is the first derivative of voltage about the time.
According to special improvement of the present invention, the grid of this clamp switch is connected to the drain electrode of mainly (rectification) switch, to prevent the grid rebound.
In preferred implementation of the present invention, at least two diodes are added to grid and drive, one of them diode is used for the grid driving is biased on the zero volt spy, and the current path that another diode is provided for opening is to eliminate the loss that is caused by the body diode reverse recovery.
Therefore, embodiments of the present invention can be based on the connection of at least one series diode in the grid of MOSFET, is similar in file WO 2004/114509A1 certifiedly, is used for minimizing reverse recovery and electromagnetic interference (EMI).Yet different from WO 2004/114509A1, embodiments of the present invention do not aggravate but to alleviate the grid rebound.
Alternatively, if bias diode is embodied in the driver, do not need this opening (turn-on) path diode.
Solution according to certain execution mode of the present invention can be integrated in the encapsulation of metal oxide semiconductor transistor (MOSFET), keeps the pin of equal number, i.e. drain pin, grid pin and source electrode pin.This has been avoided the demand to external circuit or complicated drive scheme.And because gate terminal and the electric capacity between the drain terminal of synchronous rectifier (SR) become more inessential, and can limit the avalanche breakdown level well, so this allows more flexibly device structure design.Therefore, can further improve other parameter of MOSFET, for example the drain terminal of on-state synchronous rectifier (SR) and the resistance between the source terminal.
The benefit of the preferred embodiment for the present invention can be summarized as follows:
Significantly reduce the switching loss of forward position transformation place;
Reduce electromagnetic interference (EMI);
In the prior art power MOSFET, the maximum voltage peak value of the leap synchronizing field effect transistor (sync FET) of determining, the approximate input voltage that is less than or equal to 2.5 times buck converter; Therefore, this equipment can be designed as the level that prevents the avalanche breakdown loss; Oppositely recover just can not guarantee as long as occur;
Do not need vital grid driving timing;
Can use low current, traditional gate drivers of high impedance;
Miller feedback capacity Crss is no longer so most important; Therefore, reduced compromise about parameter optimization;
The concrete solution of three-prong, namely drain pin, grid pin, source electrode pin.
Embodiments of the present invention can be used in the application such as voltage regulator module (VRM) or POL (PoL) especially, for example in the power of notebook-sized personal computer (PC) provides, in the graphics card neutralization semiconductor Related product such as integrated power transmission module, as the power transmission module of optimizing fully or high power frequency synchronous buck DC (direct current) power output stage to DC (direct current) converter applications.
Embodiments of the present invention can be with the solution of integrated solution or separation as purpose, and different synchronous rectifier converters, as synchronous buck and pressurized shift device.
Embodiments of the present invention have alleviated be presented in synchronous step-down converter and the pressurized shift device two related switch loss mechanism, namely oppositely recover and grid knock-ons.The reduction of switching loss causes better transducer effciency, and this uses of great advantage for the high electric current of high-frequency such as voltage regulator module (VRM) or POL (PoL).
With reference to the execution mode that the following describes, these or those aspect of the present invention obtains to describe, and is obvious.
Description of drawings
Figure 1A schematically shows the basic circuit diagram of synchronous step-down converter;
Figure 1B schematically shows the operate figure of the synchronous step-down converter of Figure 1A, and wherein waveform relates to specific application example;
Fig. 1 C schematically shows the synchronous step-down converter of Figure 1A about the operate figure of forward position transformation, wherein the title in the legend utilizes letter C and alphabetical S in the legend to come with reference to Figure 1A, Figure 1B, wherein letter C relates to the trace of controlling FET unit 30, and alphabetical S relates to the trace of synchronous FET unit 40;
That Fig. 2 A schematically shows is operated according to method of the present invention, be used for the basic circuit diagram of execution mode of the synchronous rectifier switch of high efficiency converter according to the present invention;
Fig. 2 B schematically shows the more detailed basic circuit diagram that is used for the synchronous rectifier switch of high efficiency converter among Fig. 2 A;
Fig. 2 C schematically shows the basic circuit diagram of the grid bias diode that is integrated in the gate drivers, does not wherein need the diode for open path;
Fig. 3 A, Fig. 3 B, Fig. 3 C and Fig. 3 D have schematically shown respectively the operate figure of synchronous step-down converter about the execution mode of forward position transformation; And
Fig. 4 A, Fig. 4 B, Fig. 4 C and Fig. 4 D have schematically shown respectively the operate figure according to the execution mode of synchronous step-down converter of the present invention.
Embodiment
Figure 1A partly adopts identical reference number accordingly in Fig. 4 D.
In order to understand better the solution that proposes according to the present invention, by example, in Figure 1A, Figure 1B and Fig. 1 C, presented understanding in depth of synchronous step-down converter operation.Figure 1A shows synchronous step-down converter, and Figure 1B and Fig. 1 C show the application drawing of this synchronous step-down converter 10 that comprises mos field effect transistor (MOSFET reference number 20) model.
The power waveform of Figure 1B shows the loss pattern LS of synchronous step-down converter 10.When switching transient, produce high loss, especially in controlling filed effect transistor 30.
To node voltage V among Fig. 1 C
xThe forward position change the more detailed observation of LE, disclose the existence of the overcurrent peak value of the raceway groove that passes controlling filed effect transistor 30 (＜--〉trace icnC among Fig. 1 C), it is responsible for substantial losses LC and LS in two switches, and is namely responsible to the substantial losses LC in the control FET unit 30 and responsible to the substantial losses LS of synchronous FET unit 40.
Current peak among Fig. 1 C results from 3 effects substantially:
The reverse-conducting of the body diode of synchronizing field effect transistor 40 (＜--trace idioS among Fig. 1 C);
Synchronizing field effect transistor 40 is because the raceway groove conducting of grid rebound (＜--〉trace icnS among Fig. 1 C); With
Capacity current.
According to the embodiment of the present invention, propose to drive 42 by the grid of revising synchronizing field effect transistor 40 and alleviate at first two current components.The solution that proposes can be integrated in the identical equipment packages, shown in Fig. 2 A and Fig. 2 B, wherein shows maximally related parasitic component.
Owing to being intended to switch with zero loss, so new synchronizing field effect transistor 40 may be embodied as very soft switch synchronous rectifier (very soft switch S R), that is:
The loss relevant with reverse recovery is zero;
The loss relevant with the grid rebound is zero, and
The loss relevant with avalanche breakdown is zero.
Basically, used the slight zero volt spy's of surpassing inferior thresholding grid voltage (being to be 0.5 volt in 1.5 volts the equipment at the typical gate voltage limit for example).In this case, the characteristic of body diode, especially dynamic characteristic substantially are improved to and can no longer observe reverse recovery current from the transistor external terminal.
Thisly eliminate body diode reverse and recover to be implemented as the first execution mode by in gate path 70, increasing diode 52, the diode 52 that wherein increases by forward bias for closing synchronizing field effect transistor 40 (referring to Fig. 2 B, very soft switch synchronous rectifier being shown).
In this process, use suitable external gate resistance R
GX, the input capacitance of power MOSFET discharges into the forward conduction voltage of the gated diode that is included, thereby is provided at the bias voltage circuit 50 of expectation time threshold level.Also use the anti-paralleled diode 54 of diode 52, to allow in grid, to open current path.
When the drain source voltage of synchronous FET unit (=reference number is 40 sync FET) rose, the loss relevant with the grid rebound began, shown in Fig. 1 C.Large dv/dt (=voltage V is to the derivative of time t) causes passing grid-drain capacitance C
GDThe electric current of (reverse transfer capacitance between=grid G and the drain D), described electric current impel grid voltage to increase until raceway groove is opened and loss occured.
In order to be reduced in the rising of grid voltage in the dv/dt transformation, include and be parallel to grid-source capacitor C
GSThe optional low impedance path 70 of (electric capacity between=grid G and the source S) (referring to the very soft switch synchronous rectifier shown in Fig. 2 A).
As long as drain source voltage begins to rise, this low impedance path 70 just works so.As the first execution mode, shown in Fig. 2 B, switch mosfet 62 is used for implementing this low impedance path 70.Switch 62 is as the clamp circuit 60 (seeing Fig. 2 A) of the grid voltage of power switch 40.The grid of clamp switch 62 is connected to the drain D of power switch 40.
As long as the drain source voltage of power switch 40 rises to the thresholding above clamp switch 62, then clamp switch 62 is opened, thus when grid rebound process begins automatic short-circuit gate path 70.The present invention depends on the resistance R of power switch 40 significantly about reducing the effect of grid rebound
GX
Unlike among the US 6421262B1 if power switch in drain source voltage be that the timing clamp switch is just closed power switch, in present embodiment of the present invention, use clamp switch circuit 60 to provide low ohm gate path 70 avoiding the grid rebound, and therefore keep this equipment to be in off state.In other words, clamp switch circuit 60 is not closed power apparatus, but makes power apparatus keep off state.This means two main distinctions about US 6421262B1, the checkout gear of the drain source voltage of the namely control strategy of clamp switch circuit 60, and power switch.
Low drain-source resistance R under the channel status
DS(on), be lower than at least the resistance of polycrystalline silicon grid of power MOSFET (equipment 40); By being characterized as low resistance R
GThe power MOSFET of (referring to Figure 1A, Fig. 2 A, Fig. 2 B) has obtained maximum benefit of the present invention.
Low threshold voltage is preferably between 0.5 volt and 1 volt;
Maximum gate voltage equals the puncture voltage of power MOSFET;
The N-raceway groove.
Can not realize easily that maximum gate voltage equals can select the following option so in the situation of puncture voltage of power MOSFET:
Use the series capacitance in the clamp field-effect transistor 62, to reduce the grid voltage of clamp switch;
The grid of clamp field-effect transistor 62 is to the connection of synchronizing field effect transistor driver, i.e. synchronizing field effect transistor driver control clamp field-effect transistor 62; In this case, if having the separation solution of the 4th pin (first grid, second grid, drain electrode, source electrode), then provide the intelligent driver of monitoring switch node voltage.
If the grid of clamp field-effect transistor 62 is connected to the drain D (referring to Fig. 2 A, Fig. 2 B) of power MOSFET, the output capacitance of synchronizing field effect transistor 40 increases so, and this is of value to the switching node trailing edge and changes.
In the exemplary embodiment according to Fig. 2 A, Fig. 2 B, as long as the drain source voltage of power MOSFET is higher than the threshold voltage of clamp field-effect transistor 62, just be sure of that this synchronizing field effect transistor is in off state.On the contrary, have short gate to drive 42 possibility, specifically in the situation that clamp field-effect transistor 62 is unexpectedly opened, gate drivers is with 62 outputs of clamp field-effect transistor.Although can prevent this unexpected unlatching of clamp field-effect transistor 62 by normal running, standard short-circuit protection and monitoring switch node voltage by in the gate drivers 42 can avoid short circuit by grill-protected driver 42.
By diode 52,54, implement bias voltage by grid voltage biasing circuit 50 at grid.Therefore, provide anti-paralleled diode 54 to allow electric current to flow through rightabout.Diode 52,54 can be arranged in the MOSFET encapsulation or the outside.In MOSFET encapsulation, have diode 52,54 benefit is, with the threshold voltage temperature dependency of diode 52,54 forward voltage temperature dependency compensation power MOSFET.
On the other hand, if diode 52,54 in the outside of MOSFET encapsulation, heat is assigned with better so, this may be very important for high switching frequency.Shown in Fig. 2 C, if bias diode 52 is arranged in the gate drivers 42, can avoid the diode 54 for open path.The diode 54 that is used for open path can be by voltage source V
DRVSubstitute, recover to allow power.
The stray inductance of gate drivers 42 causes grid voltage to depart from bias voltage level, so these stray inductances, particularly source inductance, should be lowered, perhaps otherwise the resistance of gate path 70 should increase to minimize their effect.By non-essential resistance R
GX, shown in Fig. 2 C, perhaps connect so that passage path does not present this high resistance with bias diode 52, can realize this increase of the resistance of gate path 70.
Turn-off the path for fear of high impedance, clamp switch 60,62 is arranged in parallel with grid and the source electrode of power switch, for example by clamp switch 60 is integrated in the silicon wafer of power switch, so that the minimum resistance in shutoff path.Inductance L among Fig. 2 A, Fig. 2 B
GAnd L
SThe stray inductance of expression encapsulation.
In addition, the difference between the impedance path 70 of Fig. 2 A, Fig. 2 B and the impedance path 70 of Fig. 2 C is compared with the impedance path 70 of Fig. 2 A, Fig. 2 B so far, and the impedance path 70 of Fig. 2 C should be higher.In this situation, internal node N
G, N
SCan be limited in the silicon wafer of Fig. 2 A, Fig. 2 B, and clamp switch 60,62 is connected to internal gate silicon wafer node N
GWith internal source silicon wafer node N
SBetween, thereby avoid the stray inductance that encapsulates.
Generally speaking, can find from Fig. 2 B, in conventional MOS FET 40, increase by 3 New Parents, namely
The first diode 52 is used for offset gate voltage and surpasses the zero volt spy;
The second diode 54 is used for the current path that is provided for opening; With
Clamp field-effect transistor 62.
Come very soft switch synchronous rectifier equipment among comparison diagram 2A, Fig. 2 B, Fig. 2 C and the performance of conventional synchronization field-effect transistor with accurate simulation.Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D show the application drawing that the switching node forward position changes synchronous step-down converter in the LE process.
The below lists the relevant parameter that drives path 70 about the grid of synchronizing field effect transistor 40:
Resistance R
G: 0.5 ohm;
Source inductance L
S: 600pH (p=pico=10
-12H is prosperous);
Total grid inductance (does not comprise source inductance L
S): 2.4nH (n=nano=10
-9).
Gate drivers is made as traditional, all has predetermined time lag 40ns on two edges.
Referring to the analog waveform of Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D, can find out in the first voltage of vdsdS raises main power loss occurs.In this time interval, 3 main loss mechanism in the synchronizing field effect transistor have caused power loss:
Oppositely recover;
The grid rebound; And
Puncture.
In the described time interval, controlling filed effect transistor 30 and synchronizing field effect transistor 40 power loss among both approximately all is 3.9 little joules (=the switching frequency place of 1MHz 3.9 watts).
Fig. 4 A, Fig. 4 B, Fig. 4 C, Fig. 4 D show according to embodiment of the present invention, use the simulation result of the synchronous step-down converter of very soft switch synchronous rectifier MOSFET 100.Except helping to suppress the non-essential resistance R of inductive effect in the gate path 70 that is used in synchronous MOSFET 40
GX(referring to Fig. 2 C) equals outside 2.5 ohm, and the parameter of synchronous step-down converter (comprising control MOSFET 30 and synchronous MOSFET 40) is adjusted to the value in the emulation that is applied to Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D.The clamp FET 62 that uses is less than 10 times (that is, about 60 milliohm switches) of power fet 40; Its threshold voltage is adjusted to 1 volt.Diode pair is usual in common use, has low parasitic capacitance.
As can being found by Fig. 4 A, Fig. 4 B, Fig. 4 C and Fig. 4 D, simulation result represents that present embodiment eliminates diode reverse recovery effectively, and eliminates especially and the grid relevant loss of knock-oning.As a result, comprise the overall losses power of the loss of bias diode 52 and clamp field-effect transistor 62 in the interval of forward position LE, be reduced to significantly 1.5mJ from 3.9mJ.
In addition, drain source voltage and drain current peak value are minimized, thereby improve the neurological susceptibility of avalanche breakdown, and reduce electromagnetic interference (EMI).
In order to ensure the complete operability according to embodiment of the present invention:
The resistance R of power switch 40
GWith clamp switch circuit 60 should be low as much as possible, and/or
The maximum gate voltage of clamp switch circuit 60 should be the same with the avalanche breakdown voltage of power switch high, and/or
When integrated clamp switch circuit 60, the drain electrode of clamp switch circuit 60 should be connected to the grid of power switch, and/or
In gate path 70, should provide particular gate resistance to alleviate inductive effect.
Generally speaking, according to the embodiment of the present invention, proposed to be used for the grid circuit of power apparatus, wherein power apparatus is with the drain-source resistance R in the channel status of optimizing
DS(on) and such as ratio C
GD/ (C
GS+ C
GD) other optimize relevant parameter, and corresponding method of operation, (C
GDReverse transfer or grid-drain capacitance; C
GSGrid-source electric capacity).
Effectively, in embodiments of the present invention, utilized " bulk effect " in the power MOSFET field, do not reduced nominal threshold voltage (typical case is about 2 volts).In addition, by the invention solves grid rebound problem, the circuit 100 that wherein proposes reduces described grid rebound, simultaneously, utilizes " bulk effect " to eliminate reverse recovery and to improve conducting.
In this situation, the combination of 3 aspects is crucial:
The order of operation.
Utilizing " bulk effect " to reduce among the US 5929690 of power loss, do not list the either side in this 3 aspect.
Yet, in the field of power MOSFET because even aggravated the loss relevant with grid rebound, so independent this reduction power loss is also insufficient.Applicable technical measures have in a preferred embodiment of this invention illustrated and can in the switching node ring independently, reduce significantly even minimum power consumption, that is:
Eliminate oppositely and recover;
Improve conducting; With
Avoid the grid rebound
In a word, a kind of switching circuit (100) comprises field-effect transistor (40) and is used for the grid voltage of bias-field effect transistor (40), make particularly the grid voltage of field-effect transistor (40) below certain threshold, particularly, circuit (50,52,54 under specific positive threshold level, 60,62).In execution mode, alleviated simultaneously the rebound of reverse recovery and grid.In one embodiment, biasing circuit comprises that the grid (G) that is connected to field-effect transistor (40) is with the bias diode (52) of the grid voltage of bias-field effect transistor (40), and be connected between the source electrode (S) of the grid (G) of field-effect transistor (40) and field-effect transistor (40) so that the grid voltage of field-effect transistor (40) below certain threshold, the clamp FET unit (62) below specific positive threshold level specifically.
In the claims, particularly, field-effect transistor (40) can be at least one synchronizing field effect transistor.Particularly, be used for grid voltage that the circuit (50,52,54,60,62) of the grid voltage of bias-field effect transistor (40) makes field-effect transistor (40) below certain threshold, specifically below specific positive threshold level.Particularly, biasing circuit (50,52,54) can be the bias diode (52) of at least one grid that is connected in series to field-effect transistor (40) (G), is used for the grid voltage of bias-field effect transistor (40).Particularly, clamp switch circuit (60,62), it can be at least one the clamp FET unit (62) between the source electrode (S) of the grid (G) that is connected to field-effect transistor (40) and field-effect transistor (40), the grid voltage that is used for making field-effect transistor (40) is below certain threshold, specifically below specific positive threshold level.Particularly, the second diode (54) can be anti-paralleled diode and/or open path diode, to allow to flow through the electric current with the current opposite in direction of passing bias diode (52).Particularly, actuator unit (42) can be that at least one grid drives, and wherein biasing circuit can be arranged in this actuator unit (42).Particularly, gate path (70) can be low impedance path, with the electric capacity (C from the grid (G) of field-effect transistor (40) to the source electrode (S) of field-effect transistor (40)
GS) parallel connection, be used for the rising that alleviates grid voltage in the dv/dt transition.As long as the voltage from the drain electrode (D) of field-effect transistor (40) to field-effect transistor (40) source electrode (S) begins to rise, during specifically above certain threshold, gate path (70) becomes and works.Grid resistor unit (R
GX) can connect with the first bias diode (52), particularly externally, so that the path of the path of anti-paralleled diode and/or open path diode (54) does not comprise described grid resistor unit (R
GX).
Can recognize, above-mentioned execution mode is exemplary, and does not limit the present invention, and the scope that those skilled in the art can not break away from claims designs many optional execution modes.In the claims, any reference number in the bracket does not consist of the restriction of claim.Word " comprises " does not get rid of the element do not listed in the claim or the existence of step.The existence of a plurality of this elements do not got rid of in word " " before the element.Can be by comprising hardware implementation the present invention of obvious element, and/or the processor by suitable programmed.In the equipment claim, enumerated several devices, can be by and specific several these devices of identical items of hardware.Some measure of narration does not show the combination that can not further use these measures in different mutually dependent claims.
List of reference characters
100 very soft switch synchronous rectificating devices, specifically very soft switch synchronous rectifier MOSFET
10 synchronous buck converter unit or synchronous step-down converters
20 mos field effect transistor (MOSFET)
30 control FET units
32 actuator units, the grid of specifically controlling FET unit 30 drives
40 synchronous FET units
42 actuator units, specifically the grid of FET unit 40 drives synchronously
50 voltage offset electric circuits, specifically grid voltage biasing circuit
52 first diodes, the specifically bias diode of voltage offset electric circuit 50
54 second diodes, specifically the open path diode of voltage offset electric circuit 50
60 clamp switch circuit, specifically switch mosfets
62 clamp FET units
70 gate path, specifically low impedance path
The drain electrode of D synchronizing field effect transistor 40
The grid of G synchronizing field effect transistor 40
Loss or the loss pattern of LC control FET unit 30
LE node voltage V
XForward position or forward position change
The loss of the synchronous FET unit 40 of LS or loss pattern
N
GInternal gate silicon wafer node
N
SInternal source silicon wafer node
R
GXResistance, specifically external gate resistor unit
The source electrode of the synchronous FET unit 40 of S
V
XNode voltage
Claims (4)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP06114606.4 | 2006-05-29 | ||
| EP06114606 | 2006-05-29 | ||
| EP06120034.1 | 2006-09-04 | ||
| EP06120034 | 2006-09-04 | ||
| PCT/IB2007/051806 WO2007138509A2 (en) | 2006-05-29 | 2007-05-14 | Switching circuit arrangement |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101454979A CN101454979A (en) | 2009-06-10 |
| CN101454979B true CN101454979B (en) | 2013-03-27 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200780019978.0A Expired - Fee Related CN101454979B (en) | 2006-05-29 | 2007-05-14 | Switching circuit |
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| Country | Link |
|---|---|
| CN (1) | CN101454979B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103229415B (en) * | 2010-10-21 | 2016-10-05 | 爱特梅尔公司 | Switches and Programmable Gain Amplifiers for Programmable Gain Amplifiers |
| US8981748B2 (en) * | 2011-08-08 | 2015-03-17 | Semiconductor Components Industries, Llc | Method of forming a semiconductor power switching device, structure therefor, and power converter |
| JP5582123B2 (en) * | 2011-10-05 | 2014-09-03 | 三菱電機株式会社 | Semiconductor device |
| JP5800986B2 (en) * | 2012-03-27 | 2015-10-28 | シャープ株式会社 | Cascode circuit |
| CN105634261B (en) * | 2016-03-01 | 2018-05-18 | 南京航空航天大学 | A kind of normal open type SiC JFET driving circuits with straight-through protection |
| US10224918B2 (en) * | 2016-12-07 | 2019-03-05 | Infineon Technologies Americas Corp. | Active gate bias driver |
| US9813009B1 (en) * | 2017-02-07 | 2017-11-07 | Ford Global Technologies, Llc | Active gate clamping for inverter switching devices using grounded gate terminals |
| TWI659599B (en) * | 2017-03-15 | 2019-05-11 | 德商伍爾特電子ｅｉＳｏｓ有限公司 | Power switching device and method to operate said power switching device |
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|---|---|---|---|---|
| GB2351860A (en) * | 1996-10-21 | 2001-01-10 | Int Rectifier Corp | Sensing rate of change of current with a calibrated bondwire |
| CN1734904A (en) * | 2005-08-08 | 2006-02-15 | 南京航空航天大学 | Single Switch Dual Output Boost Converter |
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2007
- 2007-05-14 CN CN200780019978.0A patent/CN101454979B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2351860A (en) * | 1996-10-21 | 2001-01-10 | Int Rectifier Corp | Sensing rate of change of current with a calibrated bondwire |
| CN1734904A (en) * | 2005-08-08 | 2006-02-15 | 南京航空航天大学 | Single Switch Dual Output Boost Converter |
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| CN101454979A (en) | 2009-06-10 |
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