CN101111900A - Semiconductor device, address assignment method, and verification method - Google Patents

Abstract

A semiconductor device includes: a CAM cell array (4) for storing operation setting information of the semiconductor device (1); a controller (8) for controlling the reading and writing of the CAM cell array; a row decoder (5); and a column decoder (6), and has a configuration for assigning different row addresses to various functional blocks of different operation setting information. Because of the function of assigning different row addresses to various operation setting information, during programming, no stress is generated on the CAM cell array (4) that is not selected.

Description

Semiconductor device, address assignment method, and verification method

technical field

The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a nonvolatile memory. More specifically, the present invention relates to a technique for controlling the operation of a semiconductor device using CAM (Content Addressable Memory) data.

Background technique

In the past, there has been known a semiconductor device that has: data stored in a nonvolatile memory body during programming or erasing of the nonvolatile memory body; Check whether the data is consistent with the expected value, and automatically perform data verification (that is, the so-called CAM unit (cell), used to control the general non-volatile storage unit and the operation of the semiconductor device used by customers). In recent years, in order to reduce the device size, a structure having a CAM cell formed in a general nonvolatile memory cell has been proposed. When the CAM cell has the same structure as the general memory cell, it is preferable that the word line and the bit line connected to the CAM cell also have the same structure as the general memory cell.

When starting up or resetting the hardware, the CAM data written in the CAM unit with the same configuration as the general storage unit is preferably transferred to a volatile storage such as SRAM (Static Random Access Memory; Static Random Access Memory) part (latch circuit). In this way, the CAM data reading will not reduce the read-access speed of general non-volatile memory cells.

In the case where the CAM cell has the same configuration as a general memory cell, it is preferable to perform a verify operation in the semiconductor device when rewriting CAM data as in the verification operation of the general memory cell. Patent Document 1 discloses a verification circuit for programming general memory cells.

When programming a common memory cell, the user inputs information "1" and "0" through I/O. "0" indicates a memory cell set to be programmed, and "1" indicates a memory cell set to be erased. In addition, the information of each I/O is used as an expected value at the time of verifying the operation.

In a semiconductor device, before actual programming, data of a plurality of memory bank cells connected to a word line to be programmed is read out at once. This processing is called pre-reading. Compare the pre-read data with the data input through I/O, only for the memory that is set to be in the erased state (stored with information "1") and programmed through I/O (input with "0") Units are programmed.

For programmed memory cells (stored with information "0"), programming is not performed because additional programming will generate stress. When the information input to the programmed memory bank unit (stored with information "0") through the I/O is "1", an error signal is sent back to the controller. This is because the memory bank unit is a non-volatile memory bank that actually performs the write operation, and the erase operation and the program operation are separated because of reversibility, for example, each sector (sector) is commonly erased. When the information input from the I/O to the erased bank unit (stored information "1") is "1", no operation is performed.

The programming of the CAM unit is the same as that of the general memory cell. However, when programming a CAM cell, two interface methods different from the programming interface of a general memory bank cell are used. The programming interface of the CAM unit for making the CAM unit that is programmed and the CAM unit that is not programmed correspond to the information "1" and "0" from the I/O to input and set is called interface 1 (refer to Patent Document 2 ). In the case of interface 1, the user inputs information "1" and information "0" through respective I/Os. Information "1" indicates a memory cell set to be programmed, and information "0" indicates a memory cell set not to perform an operation (not to be programmed).

In addition, when programming CAM cells, instead of using the method of interface 1, a method of specifying only the CAM cells to be programmed by command input is used. This method is called interface2. In the case of using the interface 2, since the address of the CAM cell is specified, the specified CAM cell means a bank cell set to be programmed.

Patent Document 1: Japanese Patent Application Laid-Open No. 6-76586

Patent Document 2: Japanese Patent Application Laid-Open No. 10-106275

Contents of the invention

(Problem to be solved by the invention)

Preferably, a user block (user block) for users to rewrite information and a factory block (factory block) for factory manufacturers to pre-write information are provided in the CAM unit. In this configuration, when rewriting the CAM data of the user block, it must be ensured that the memory cells of the factory block are not affected by the disturbance of the cell information. The so-called disturbance is a phenomenon in which memory cells connected to the same word line and bit line are electrically affected during programming of a designated memory cell, resulting in charge loss or charge increase in the memory cell.

The first problem of the conventional technology is that when rewriting the CAM data of the user block, it is necessary to ensure that the memory cells of the factory block will not be disturbed by the cell information.

The second problem with the conventional technology is that it cannot be verified correctly after programming the CAM cells. This problem point is detailed below.

The second problem arises when it is configured as an array with multiple CAM cells connected on the same word line, and the verification operation is performed on the multiple CAM cells on the same word line at the same time.

Figure 1 (A) shows that multiple CAM cells arranged on the same word line are in a programmed state. The CAM cells shown as "1" in Figure 1 (A) are erased cells and have not been programmed yet. The CAM cells that are "0" are programming cells, and are cells that have already been programmed.

The CAM cell on the word line shown in FIG. 1 (A) performs I/O input of the interface 1 shown in FIG. 1 (B). In addition, "1" shown in Fig. 1 (B) is set to execute programming, and "0" is set to not execute programming and is in the current state.

In the semiconductor device, data is read from each CAM cell on the word line through the pre-reading, and the pre-reading data is compared with the data input from the I/O, and only the data in the erased state (stored information "1") and the memory bank cells set to be programmed (input with information "1") through the I/O are programmed. Here, as shown in FIG. 1 (C), programming is performed on the rightmost CAM cell on the word line.

Verify after programming. The data read from the CAM cell after programming is compared with the I/O input data as an expected value (see FIG. 1 (D)). At this time, as shown in Figure 1 (D), when the expected value of the I/O input is not programmed for the programmed CAM cell, the comparison result is "failure", and the verification operation ends in failure.

In addition, in the case of using the designation method of the interface 2, since it is a method of designating only the CAM cells to be programmed by command input, it is impossible to generate the expected value corresponding to the unprogrammed CAM cells on the same word line. , and the verification operation cannot be implemented.

The present invention was developed in view of the above-mentioned problems, and its object is to provide a semiconductor device that can normally perform data rewriting and verification in a semiconductor device with a CAM unit, an address allocation method, and a Authentication method.

(means to solve the problem)

In order to achieve the object, the semiconductor device of the present invention has: a cell array for storing operation setting information of the semiconductor device; and a control unit for controlling reading and writing of the cell array, and the control unit It has a structure for assigning various row addresses to the operation setting information. Since different row addresses are allocated to each function of the operation setting information, no stress (gate disturbance) will be generated to the cell array of the unselected function during programming.

In the semiconductor device described above, the control unit may assign different column addresses to the respective functions of the operation setting information. Since different column addresses are assigned to the respective functions of the operation setting information, no stress (drain disturb) is generated to the cell array of the unselected functions.

In the semiconductor device described above, the control unit may assign consecutive column addresses to a plurality of different functions of the operation setting information. Since consecutive column addresses are allocated to a plurality of different functions, data can be continuously read, thereby shortening the read time.

In the semiconductor device described above, the control unit may distribute the operation setting information to a plurality of columns selected by the row address. In addition, the control unit may distribute the operation setting information to all I/Os of an arbitrary column selected by the row address. The number of read cycles can be minimized, thereby reducing the read time.

In the semiconductor device described above, a wiring pattern of a local bit line (local bit line) is cut off between memory bank cells of different row addresses. Since the wiring patterns of the local bit lines are cut between bank cells with different row addresses, data can be read by switching column addresses while simultaneously selecting word lines between bank cells with different functions.

In the above semiconductor device, the memory cells with addresses in different rows may respectively have switches for switching the connection with the bit lines provided in the corresponding columns. Data can be read out by switching column addresses while word lines are simultaneously selected between memory bank cells with different functions.

In the semiconductor device, the cell array has a plurality of memory cells in each column, and the plurality of memory cells in which the operation setting information is not stored can also be switched from a bit line arranged in a corresponding column. Leave. Therefore, when programming, there is no stress to the cell array of unselected functions.

In the above-mentioned semiconductor device, the control unit may select all the word lines on the cell array, and continuously switch the column address to read data. Data can be read only by switching the column address without switching the word line, and the reading time can be shortened.

In the above semiconductor device, the control unit may have a conversion table for converting the number of the designated memory unit into the address of the corresponding memory unit. Since the address of the specified cell can be converted, a desired cell can be programmed.

The present invention is an address allocation method for allocating addresses to a cell array storing operation setting information of a semiconductor device, in which different row addresses are allocated to each function of the operation setting information. Since different row addresses are assigned to each function of the operation setting information, no stress is generated on the cell array of the function not selected during programming. In addition, each function can be erased.

In the address allocation method, different column addresses may also be allocated to the respective functions of the operation setting information. Data can be read with different column addresses for each function of the operation setting information.

In the address assignment method, consecutive column addresses may also be assigned to a plurality of different functions of the operation setting information. It becomes easy to read out the operation setting information of multiple different functions.

In the address allocation method, all the word lines on the cell array may also be selected, and the column addresses may be switched continuously to read data. Therefore, the operation setting information can be read only by switching the column address without switching the word line.

The composition of the present invention has: a cell array for storing operation setting information of a semiconductor device; a writing circuit for simultaneously programming a plurality of cells of the cell array; and a verifying circuit for verifying only actually programmed cells. The programming result of the unit. In this way, the present invention can verify the programming results of only the cells that were actually programmed.

In the semiconductor device, the verification circuit may also include: a comparison circuit for comparing the expected value data obtained by normal programming with the data read by the cell or sense amplifier (Sense Amplifier) after the programming. data; and a control unit for controlling to make a pseudo-pass for the result of the comparison circuit assigned to the unprogrammed cell. Since the control is performed so that the result of the comparison circuit assigned to the unprogrammed cell is given a dummy pass, the programming result of the programmed cell can be reflected in the verification.

In the above-mentioned semiconductor device, the control unit is a unit designated to be programmed by an external input, and may include an expected value holding circuit, which is a unit for determining an erase bit before the programming, and according to the The expected value data obtained when programming the unit is generated according to the instruction of the control unit, and output to the comparison circuit assigned to the unit. In this way, since the actually programmed cell is determined and the expected value data is output to the comparison circuit assigned to the cell, the programming result of the programmed cell can be correctly determined.

The above-mentioned semiconductor device may also include: a cell array for storing operation setting information of the semiconductor device; a write circuit for simultaneously writing a plurality of cells of the cell array; a volatile memory circuit for storing the storage data of the plurality of cells before the programming; and a verification circuit, among the plurality of cells, directly using the storage data to verify the cells that have not been programmed, and verifying the actual The programmed cells verify programming results using expected value data obtained after performing normal programming. In this way, since the present invention directly uses the stored data to verify the unprogrammed cells, and uses the expected value data obtained during normal programming to verify the programming results for the actually programmed cells, it can correctly verify the programmed The programming result of the unit.

In the semiconductor device, the verification circuit may also include a plurality of comparison circuits for comparing expected value data obtained by normal programming with those read by the cells or sense amplifiers after the programming. the data; and the control unit is used to determine the cell that has actually been programmed, and the comparison circuit assigned to the cell uses the expected value data obtained after normal programming to verify the programming result. The actually programmed cells can be determined, and the programming results of the programmed cells can be verified correctly.

In the semiconductor device, the control unit is a cell designated to be programmed by an external input, and stores an expected value in the volatile memory circuit corresponding to a cell whose bit is erased before the programming. The data is changed into programmed expected value data and output to the comparison circuit. The actually programmed cells can be determined, and the programming results of the programmed cells can be verified correctly.

In the semiconductor device, the control unit may externally input an indication signal indicating whether to set as a programming target to the plurality of cells to determine whether the cell set as the programming target is an eraser or not. Divide the bit cell and determine the cell that is actually programmed. The unit to be programmed can be set by an external command signal, and the designated unit can be programmed.

In the semiconductor device, the control unit may decode address information input from the outside, determine the cell set as the programming target, and determine whether the cell set as the programming target is at the erase bit. cell, and determine the cell that is actually being programmed. A cell to be programmed can be set by address information input from the outside, and the designated cell can be programmed.

In the semiconductor device, the control unit may switch an interface for specifying the programming target unit by a mode switching signal input from the outside. Designation of cells to be programmed may be accepted corresponding to a plurality of interfaces.

In the semiconductor device, the verification circuit may be shared between the verification after programming of the cell array storing the operation setting information and the verification after programming of a general cell array storing general data. Since the verification circuit can be shared, the circuit can be miniaturized.

In the semiconductor device, the comparison circuit may also input a mode signal for switching the cell array storing the operation setting information to programming mode, and compare the expected value data with that from the cell or sense amplifier. read data. The comparison circuit can be operated only at the time of verification.

In the semiconductor device, when programming the cell array for storing the operation setting information, the output of the volatile storage circuit may be used, and a comparison operation may be performed in the comparison circuit, and in When programming a general cell array for storing general data, it is also possible to use the output of the expected value holding circuit storing the expected value data obtained when the cells are programmed, and perform the comparison operation of the comparison circuit. Different verification control can be performed when programming a cell array for storing operation setting information and when programming a general cell array.

The present invention also provides a verification method for verifying a cell array storing operation setting information of a semiconductor device, wherein among a plurality of cells in the cell array, only a programming result of a cell actually programmed is verified. In this way, the present invention can only verify the programming results of the cells that were actually programmed.

The present invention also provides a verification method for verifying a cell array storing operation setting information of a semiconductor device. The verification method is to directly use the data of the cell before the programming for the cell that has not been programmed. Verification, and for the cells that are actually programmed, use the expected value data obtained when programming is performed normally to verify the programming results. In this way, since the present invention directly uses the storage data to verify the unprogrammed cells, and uses the expected value data obtained during normal programming to verify the programming results for the actually programmed cells, it can be correctly verified. The programming result of the programmed cell.

(effect of invention)

The present invention can normally perform data rewriting and verification in a semiconductor device with a cell array for storing operation setting information.

Description of drawings

FIG. 1 (A) to FIG. 1 (D) are used to illustrate the problems of the prior art.

Fig. 2 shows the structure of the semiconductor device of the present invention.

FIG. 3 shows an example of a bitmap of a CAM cell array.

FIG. 4 shows an example of a bitmap of a CAM cell array.

Figure 5 shows the correspondence between the WP bit number and the address.

Figure 6 shows the conversion of the CAM cell array address towards the WP bit address.

FIG. 7 (A) and FIG. 7 (B) show the structure of memory cells of a CAM cell array and a general cell array.

FIG. 8 (A) and FIG. 8 (B) show the structure of the memory cell of the CAM cell array and the general cell array.

Fig. 9 shows the configuration of the logic circuit for converting the WP address into the CAM column address.

Figure 10 shows the configuration of the logic circuit that converts the WP address into DQ.

Fig. 11 shows the structure of cell array and verification circuit.

Figure 12 shows the configuration of the WP bit selection circuit.

Fig. 13 is a flowchart showing the sequence of operations when the verification circuit is in I/O mode.

FIG. 14 (A) to FIG. 14 (D) are used to illustrate the sequence when the verification circuit is in the I/O mode.

FIG. 15 is a flowchart showing the operation sequence when the verification circuit is in address mode.

FIG. 16 is used to illustrate the sequence of verifying circuit in address mode.

Fig. 17 shows the detailed configuration of the verification circuit.

The eighteenth is the configuration of the display cell array and verification circuit.

Fig. 19 shows the configuration of the WP bit selection circuit.

Fig. 20 is a flow chart showing the sequence of operations when the verification circuit is in I/O mode.

FIG. 21 is used to illustrate the sequence when the verification circuit is in I/O mode.

Fig. 22 is a flow chart showing the operation sequence when the verification circuit is in the address mode.

Fig. 23 is used to illustrate the sequence when the verification circuit is in the address mode.

Fig. 24 shows the detailed configuration of the verification circuit.

Detailed ways

Preferred specific embodiments of the present invention are described below with reference to the accompanying drawings.

first embodiment

Preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First, referring to Fig. 2, the overall configuration of this embodiment will be described. The semiconductor device 1 of this embodiment includes: a general cell array 3 for storing general data; and a CAM cell array 4 for storing CAM data. The CAM cell array 4 is the same as the general cell array 3, and has a structure in which bank cells are arranged in a plurality of rows and columns. The CAM cell array 4 stores operation setting information (so-called CAM data) of the semiconductor device 1 . For example, write protection information of the general cell array 3 , internal voltage adjustment information, internal timing adjustment information, operation mode switching information, and bank unit backup bit information of the semiconductor device 1 are stored. Peripheral circuits for implementing data writing, reading, and erasing of these cell arrays are provided. As shown in Figure 1, the peripheral circuit is provided with a row (row) decoder 5, a column decoder 6, a command buffer 7, a controller 8, a programming voltage generating circuit 9, a sense amplifier 10, a volatile memory Body unit 11 , determination circuit 12 , verification circuit 13 , and data input/output circuit 14 .

The row decoder 5 is used to selectively drive a plurality of word lines WL based on respective addresses during data writing, erasing, and reading, and to apply a required voltage from the programming voltage generating circuit 9 to the word lines WL. word line driver (not shown). The column decoder 6 selects a column of the cell array (ie, selects a global bit line or a local bit line) based on an externally input address.

The command buffer 7 decodes external commands into internal control signals. The controller (control unit) 8 controls the internal operation of the corresponding command corresponding to the internal control signal decoded by the command register 7 . The controller 8 is, for example, constituted by a microprocessor, and controls the programming voltage generation circuit 9 , the determination circuit 12 , and the verification circuit 13 according to the internal control signal.

The CAM data stored in the CAM cell array 4 is transferred to and stored in the volatile memory bank unit 11 when the power of the semiconductor device 1 is turned on or when the hardware is reset. Since the CAM data is read in advance in the volatile memory bank unit 11 , there will be no delay in the read operation due to the readout of the CAM data when the general cell array 3 is read in advance. Since the read operation time becomes longer as the activation time increases, it is better to transfer CAM data in a short time.

The data input/output circuit 14 is provided with I/O terminals for inputting programming commands from the outside and outputting read data. The data input/output circuit 14 performs writing (programming) and reading (reading) of data in the general cell array 3 and the CAM cell array 4 .

Next, the configuration of the CAM cell array 4 will be described. FIG. 3 is a bitmap showing the allocation of CAM data to the CAM cell array 4 . The CAM cell array 4 is divided into functional blocks of a user block and a factory block. Data erasure is performed in units of functional blocks.

The so-called user block refers to an area for writing a user-rewritable write-protect (write-protect) bit (hereinafter also referred to as a WP bit). The write protect bit is a bit for controlling programming or erasing of a memory bank unit, and is set in units of an arbitrary number of sectors (hereinafter, the unit is referred to as a sector group). In the example shown in Figure 3, it is preferable to assign the WP bit to all I/Os from DQ0 to DQ15, one word line (one row address), and one local bit line (LBL) for each I/O Four are allocated (ie, 4 column address shares (LBL0 to LBL3)), and the global bit line (GBL) is allocated one share (GBL0) for each I/O. Here, allocating the WP bit to all the I/Os of DQ0 to DQ15 refers to allocating data to all memory bank units in any column selected by the row address. When the number of WP bits is not divisible by the number of I/Os, you can focus on I/O allocation to allocate columns, or focus on column allocation to allocate I/O. For example, when the number of WP bits is 60 and the number of I/Os is 16, in the method of allocating columns with emphasis on I/O allocation, WP bits 60, I/O (DQ) corresponding to 61, 62, 63, or shift (shift) the I/O (DQ) corresponding to WP bits 1, 2, 3, 4 of the front column address (000000) and to assign. In the method of allocating I/O with emphasis on column allocation, the I/O (DQ) corresponding to WP bits 15, 31, 47, 63 is skipped for allocation.

The user block is composed of 64 bits of WP bits 0 to 63, and bit allocation is performed according to the correspondence relationship (conversion table) shown in FIG. 5 and the conversion (conversion table) shown in FIG. 6 . That is, as shown in FIG. 5 and FIG. 6, WP bits 0 to 63 correspond to addresses A17 to A20 as I/O DQ terminals and addresses A21 and A22 as column addresses.

The factory block is a functional block that is rewritten by the manufacturer but cannot be rewritten by the user. In this functional block, backup data, internal voltage trimming data, internal timing trimming data, etc. are written.

In the factory block shown in Figure 3, 16 bits from TR0 to TR15 are used for trimming, and 32 bits from REDSECA to REDSECD are used to store a sector backup of a defect release address using 8 bits. Bit share, and 128 bit shares of REDCOL (0 to 0) to REDCOL (7 to 1) used to record a defect release address using 8 bits.

As shown in Figure 3, the factory block is also allocated to each of DQ0 to DQ15, one word line is allocated, and 11 local bit lines (LBL) are allocated for each I/O (that is, 11 column addresses ( LBL4 to LBL14)), the global bit line (GBL) of the factory block allocates three copies (GBL1 to GBL3) for each I/O. As shown in FIG. 4 , the factory block can also be configured with 64 bits the same as the user block, and allocated to each of DQ0 to DQ15.

FIG. 7(A) shows the detailed structure of the CAM cell array 4 , and FIG. 7(B) shows the detailed structure of the general cell array 3 . The CAM cell array 4 shown in Fig. 7 (A) has word lines independent of each other in the factory block and the user block, so that the factory block will not be affected by the bank information due to the rewriting of the user block grid interference. That is, different row addresses are assigned to the factory block and the user block. The row decoder 5 shown in FIG. 2 distributes the CAM data of each functional block to different row addresses according to the addresses input from the outside. FIG. 7(A) shows the word line WL0 allocated to the WP bits included in the user block and the word line WL1 allocated to the factory bits included in the factory block. Also, in the same functional block (user block or factory block), the number of word lines to be allocated is set to the minimum. This is because this structure is designed so that data in units of functional blocks can be erased as a whole. Here, the so-called gate disturbance refers to the phenomenon that the bit line connected to the same bit line as the memory cell to be programmed applies a high voltage during programming to the gate of the unselected memory cell, causing charge to increase. . Because of this phenomenon, the data of the unselected memory cells will change from "1" (low threshold) to "0" (high threshold) due to charge increase.

Similarly, the column decoder 6 allocates the CAM data of each functional block to different column addresses according to the addresses input from the outside. In addition, between the factory block and the user block, addresses are allocated in such a manner that column addresses are continuous.

In order to prevent the factory block from being disturbed by the drain of the memory bank information due to the rewriting of the user block, etc., the bit line is connected between the factory block and the user block as shown in Figure 7 (A). be separated. That is to say, the column decoder 6 assigns column addresses independent of each other to data in the user block and the factory block. In addition, the column decoder 6 is set to consecutive column addresses between different functional blocks. Here, the separation of the bit lines refers to the physical separation and electrical separation of the local bit lines and the global bit lines. The so-called drain disturbance refers to the phenomenon that the bit line is connected to the same bit line as the memory cell to be programmed, and the bit line applies a high voltage during programming to the drain of the non-selected memory cell, causing charge leakage. Because of this phenomenon, the data of the non-selected memory cells will change from "0" (high threshold) to "1" (low threshold) due to charge leakage.

In addition, since all the CAM data are read out only by switching the column address in the state where all the word lines (for example, word lines WL1 and WL2) are selected, there will not be the same column address between functional blocks, and the Column addresses are continuous within a functional block. Therefore, the time for word line switching can be saved, and the CAM data can be transferred from the CAM cell array 4 to the volatile memory bank unit 11 in a short time. In this case, when a plurality of word lines are simultaneously selected, bit lines connecting unnecessary cell data are separated so that necessary cell data and unnecessary cell data are not repeatedly selected through the same bit line.

And, taking advantage of the fact that the user block and the factory block do not share the same column address, the allocation of the local bit line (LBL) between the user block and the factory block is shown in Figure 8 (A). The line pattern is physically disconnected, and the disconnected local bit line (LBL) is not connected to the global bit line (eg, no contact vias are provided). Alternatively, the user block and the factory block are separated from each other with the concept of a sector, and each of the user block and the factory block has a column switch (column) connected to the global bit line as shown in FIG. switch) to electrically separate the user block from the factory block.

Thereby, when data is read from the CAM cell array 4 to the volatile memory cells 11 during power supply or the like, the word line of the user block and the word line of the factory block can be simultaneously selected. , CAM data is read out only by selecting and switching the column address. Since there is no need to select and switch word lines, the total readout time of all bits of CAM data can be shortened.

FIG. 9 shows the configuration of a conversion circuit for converting address signals for program/erase operations into column address signals for individual banks. Since this conversion circuit is arranged in the column decoder 6, and switches the CAM programming mode signal (CAMPGM) into an active state and an inactive state, it can be switched to the column address of the general cell array 3 and the column address of the CAM cell array 4 .

The composition of the conversion circuit is provided with: OR gate 121 for inputting address signal WA (0) or WA (1) and CAMPGM signal for programming/erasing operation; OR gate 123 for inputting CAMPGM signal respectively The inverting output of and address signal WA (21) or WA (22); NAND (reverse AND) grid 124, in order to input the output of OR grid 121 and 123; And inverter 125, in order to make the output of NAND grid 124 invert. The output of the inverter 125 becomes the column addresses AA(0) and AA(1). When the CAMPGM signal is inactive, the address signals WA(1) and WA(0) will directly become column addresses AA(1) and AA(0).

In addition, and possess: OR grid 131, in order to input GAMPGM signal, each address signal WA (2), WA (3), WA (4), and WA (5); OR grid 133, in order to input CAMPGM signal Inverted output and power supply voltage VCC; NAND gate 134 for inputting the outputs of OR gates 131 and 133 ; and inverter 135 for determining the output of NAND gate 134 . The output of the inverter 135 is output as column addresses AA(2), AA(3), AA(4), and AA(5).

Fig. 10 is a diagram showing a conversion circuit for converting address signals for program/erase operations into DQ. This conversion circuit is provided in the data input/output circuit 14 as a switch. The conversion circuit used to generate DQ0 is composed of the following: NOR grid 142 for inputting address signals WA (20), WA (19), WA (18), WA (17); NAND grid 143 for The CAMPGM signal and the output of the NOR gate 142 are input; and the inverter 144 is used to invert the output of the NAND gate 143 . A conversion circuit for generating DQ1 to DQ15 is configured with the same circuit configuration.

When the CAMPGM signal is active, address signals WA(0) to WA(17) are assigned to CAM_DQ15 to CAM_DQ0. When the general cell array 3 is in the selected state (that is, the CAMPGM signal is inactive), CAM_DQ15 to CAM_DQ0 become inactive.

When programming the write protection bit, only the DQ to be programmed is activated by the conversion circuit shown in FIG. 10 , and the applied stress, expected value, and judgment signal are controlled, thereby ignoring the DQ not to be programmed.

Although the above-described embodiments are preferred embodiments, the present invention is not limited thereto. For example, the factory block may also include a one-time programmable read-only memory (One Time Programmable Rom; OTP ROM). OTP ROM is a functional memory bank that can only be programmed once by the user. From the point of view of the function that allows users, although it is different from the factory block, but from the point of view of the function that does not allow reprogramming after one programming, it is separated from the user block that can be repeatedly programmed and erased by the user. . That is, it is required to avoid gate disturbance and drain disturbance.

In addition, the read bit block can also be used to form the user block instead of the write bit block, and the read control can be performed in any sector unit.

In the described embodiment, although it is disclosed that the local bit lines between the factory block and the user block are physically separated and the global bit lines are electrically separated, the present invention is not limited thereto, and the The global bit lines between the factory block and the user block are physically or electrically separated.

Ordinary cell arrays and CAM cell arrays can also be connected to share the data bus, or connected to share the global bit lines of the user block and factory block.

In addition, the wells between the user block and the factory block can be separated or shared. If shared, the size of the die can be reduced. In this case, when the erase operation is performed in the user block, floating control is performed on the word line of the factory block.

second embodiment

Referring to Fig. 11, the configuration of this embodiment will be described. Figure 11 shows the cell array part 2 (common cell array 3 and CAM cell array 4) used to store the data of the semiconductor device 1, and is used to confirm the writing state of the data in the cell array part 2 or the erasing state of the data. Configuration of the verification circuit 13 and the expected value holding circuit 32 in the data input/output circuit 14 . In this embodiment, there is also a 16-bit simultaneous write mode, whereby 16 memory bank cells of the general cell array 3 or the CAM cell array 4 can be accessed and programmed simultaneously.

As shown in FIG. 11 , the verification circuit 13 includes a WP bit selection circuit 33 and a data comparison circuit 34 . Sixteen expected value holding circuits 32 and data comparison circuits 34 in the data input/output circuit 14 are respectively provided corresponding to the 16 I/Os.

As shown in Figure 11, the interface mode setting signal, the signal input from each I/O, and the address signal (WP-CAM address designation signal) designating the write-protect CAM (hereinafter referred to as WP-CAM) are input to the The WP bit selects the circuit 33 .

There are two specified methods for programming CAM cells. A method of specifying by inputting information "1" to an I/O corresponding to a CAM cell to be programmed, and inputting information "0" to an I/O corresponding to a CAM cell not to be programmed ( Hereinafter referred to as I/O mode). Another method is to input the corresponding address to the CAM cell to be programmed (hereinafter referred to as address mode). The interface mode setting signal is a signal used to switch the designated method of the CAM cell to be programmed between the two methods.

FIG. 12 shows the detailed configuration of the WP bit selection circuit 33. As shown in FIG. As shown in FIG. 12 , the WP bit selection circuit 33 mainly includes a decoder 51 , an AND gate 53 , and a switch 54 . Sixteen AND gates 53 and switches 54 are provided corresponding to the sixteen I/Os. With this configuration, the data comparison circuit 34 for dummy verification is selected.

When the address mode is set with the interface mode setting signal, the switches 54-(0) to 54-(15) are turned off (OFF), and the input WP-CAM address designation signal is translated by the decoder 51 code to generate a verification control signal. In addition, when the I/O mode is set with the interface mode setting signal, the decoder 51 is turned off (OFF) by the interface mode setting signal input to the decoder 51 via the inverter 52, and The switches 54-(0) to 54-(15) are turned ON.

Input the signal (I/O-(0) to I/O(15)) input by each I/O and the pre-read data (DAV) read in advance by the CAM unit to the AND gate 53-(0) to 53 -(15), and the logical product of these signals is obtained. That is, when the data before programming of the CAM unit and the data input by the I/O are both "1", a high level signal is output as a verification control signal. In other cases, a low-level signal is output as a verification control signal.

As shown in FIG. 11, the expected value holding circuits 32-(0) to 32-(15) are provided corresponding to the respective I/Os, and hold the information input by the I/Os. After the general cell array 3 is programmed, the retained information is output to the data comparison circuit 34 as expected value data. The expected value holding circuits 32-(0) to 32-(15) hold the information of the I/O input when the I/O mode is set and the programming of the CAM cell array 4 is performed. After the CAM cell array 4 is programmed, the held information is output to the data comparison circuit 34 as expected value data. In addition, when the address mode is set and the programming of the CAM cell array 4 is performed, when the switch 35 is turned on by the interface mode setting signal, the expected value holding circuit 32 will input the verification control output by the WP bit selection circuit 33. signal and generate the expected value. After the CAM cell array 4 is programmed, this data is output to the data comparison circuit 34 as expected value data.

The data comparison circuits 34-(0) to 34-(15) are also respectively provided corresponding to the I/Os, and hold the data read by the general cell array 3 or the CAM cell array 4 in the expected value holding circuits 32-(0) to The data (expected value) in 32-(15) are compared. During programming of the CAM cell array 4 , the data comparison circuit 34 dummy-verifies all the cells not to be programmed by the verification control signal from the WP bit selection circuit 33 .

Next, referring to the flowchart of FIG. 13 and FIG. 14(A) to FIG. 14(D), the operation of setting the I/O mode of this embodiment and programming the CAM cell array 4 will be described. In this embodiment, a write protection setting for protecting writing can be performed on a sector group composed of a plurality of sectors, and I/O can be allocated to each sector group. When a sector group set as write protection for protecting writing is selected, programming of protection data is performed in WP-CAM cells of the sector group.

First, the CAM programming setting signals (I/O-0 to 15) of the WP-CAM cells to be programmed are input from the respective I/Os (step S10). Input the information "1" to indicate that programming is performed to the I/O corresponding to the WP-CAM unit to be programmed, and input the information "0" to indicate that programming is not performed to other I/Os (see 14 (Figure (B)).

Next, the data stored in the WP-CAM unit is read (pre-read) (step S11). The pre-read data is judged, and the data writing status of each WP-CAM cell is judged. When data has been written and is in a programmed state, information "0" is stored, and when data is not written and is in an erased state, information "1" is stored (see FIG. 14(A)).

Next, write is set by an I/O input signal, and a WP-CAM cell whose current state is in an erased state is detected (step S12). A WP-CAM cell whose data of the pre-read WP-CAM cell is "1" in an erased state and whose I/O input is "1" is detected. For this judgment, the expected value holding circuit 32 and the data comparison circuit 34 shown in FIG. 11 can also be used.

Then, the detected WP-CAM cells are programmed (step S13) (for example, refer to FIG. 14(C)). When programming is performed, the verification circuit 13 judges whether data has been definitely written into the WP-CAM cell. At this time, the switches 35-(0) to 35-(15) provided for the respective I/Os are turned off by the interface mode setting signal set to the I/O mode. In addition, an interface mode setting signal is also input to the WP bit selection circuit 33, and sets the switches 54-(0) to 54-(15) to be turned on.

WP bit selection circuit 33 draws the data read by each WP-CAM unit during pre-reading and the signal of I/O input (I/O-0 to 53-(15) by AND gate 53-(0) 15) to generate a verification control signal. When the I/O input is designated as “1” for programming, and the pre-read data is also designated as “1” for erasing cells, a high-level verification control signal is output to the data comparison circuit 34 . In other cases, a low-level verify control signal is output to the data comparison circuit 34 .

Expected value holding circuits 32-(0) to 32-(15) directly latch the input I/O-(0), (1) to (15) signals, and use the latched data as DIN0 at a predetermined timing to DIN15 to output to data comparison circuits 34-(0) to 34-(15). These data are referred to as expected value data. The verification control signal from the WP bit selection circuit 33 is also input to the respective data comparison circuits 34-(0) to 34-(15).

The data comparison circuit 34-(0) to 34-(15) is to compare the data (that is, the data after programming) read from the WP-CAM unit with the expected value holding circuit 32-(0) to 32-(15) The expected value of the readout is compared. At this time, in the data comparison circuit 34 to which the low-level verification control signal is input from the WP bit selection circuit 33, a high-level matching signal is output without a comparison operation, whereby the verification is virtually passed (refer to FIG. 14 (D) ). In the data comparison circuit 34 inputted with a high-level verification control signal by the WP bit selection circuit 33, the expected value data input by the corresponding expected value holding circuit 32 is compared with the programmed data of the WP-CAM cell. When the I/O input is set to "to be programmed" with "1", and the data read by the WP-CAM unit after programming is in the erased state set with "1", it will indicate the low bit of Fail The quasi-signal is output to the decision circuit 12. As shown in Figure 14 (D), when the I/O input is "1" and the data read by the WP-CAM unit after programming is in the programming state set with "0", it will indicate the high level of verification passed The signal is output to the decision circuit 12 .

When the matching signals output by the data comparison circuits 34-(0) to 34-(15) are all at the "H" level, the determination circuit 12 outputs a verification signal indicating that the data writing is successful to the controller.

In this embodiment, since the comparison result of the data comparison circuit assigned to the unprogrammed CAM cell is dummy passed, the programming result of the programmed CAM cell can be reflected in the verification.

Next, referring to the flowchart of FIG. 15 and FIG. 16, the operation in the case of specifying the sector group address (SGA) from the outside will be described. As shown in FIG. 16 , the sequence for executing the programming command of WP-CAM is to carry out the program of command recognition in 5 cycles (cycle), and rewrite the information in the 6th cycle. That is, an SGA to be programmed is specified, and one SGA is programmed in a total of six cycles.

First, a WP-CAM address designation signal designating a WP-CAM cell to be programmed is input. Analyze the WP-CAM address specifying signal with a decoder (step S20 ), thereby generating an address corresponding to the actual WP-CAM unit to be programmed. In the verification circuit 13, the WP-CAM address specifying signal is decoded by the decoder 51 as well. Then, a high-level verification control signal is output to the expected value holding circuit 32 and the data comparison circuit 34 corresponding to the WP-CAM unit to be programmed. A low-level verification control signal is output to other expected value holding circuits 32 and data comparison circuits 34 .

Next, read ahead the data stored in the WP-CAM unit specified by the decoding result (step S21). Determine the pre-read data to determine the data writing status of the WP-CAM unit.

When it is determined that the WP-CAM cell is in the erasing state (YES in step S22), write data into the cell and set it in the programming state (step S23). When it is judged that the WP-CAM unit is in the programming state (step S22 is negative (NO)), it is considered that the programming is completed and the process ends.

When the programming of the WP-CAM cell is completed, the verification circuit 13 is used to perform verification to determine whether data has been correctly written in the WP-CAM cell.

The WP bit selection circuit 33 is connected with the data comparison circuits 34-(0) to 34-(15) set corresponding to the I/O by wires, and the verification control signal is output from the WP bit selection circuit 33. When in the address mode, the switches 35-(0) to 35-(15) are turned on by the interface mode setting signal. Therefore, the verify control signal is input only to the expected value holding circuit 32 connected to the wire that outputs the verify control signal at the "H" level. The expected value holding circuit 32 input with the verification control signal of the "H" level generates an expected value "0" indicating that the WP-CAM cell has been programmed, and outputs it to the data comparison circuit 34 (step S24) (refer to FIG. 16 ) . The expected value holding circuit 32 to which the verification control signal of the "L" level is input does not generate an expected value (step S24). Therefore, the expected value is not output to the data comparison circuit 34 .

The data comparison circuit 34 inputted with the expected value "0" from the expected value holding circuit 32 reads out the data stored in the WP-CAM unit, and compares the data DAVi with the expected value "0" (shown by /DINi in FIG. 16 ). )Compare. The other data comparison circuit 34 forcibly outputs a matching signal of "H" level because the verification control signal is at the low level. That is, the verification is virtually passed (see FIG. 16).

When the matching signals output by each data comparison circuit 34 are at the "H" level, the determination circuit 12 outputs a verification signal indicating that the data writing is successful to the controller (step S25). That is, a data comparison result of actually programmed WP-CAM cells may be output as a verification result.

FIG. 17 shows detailed configurations of the expected value holding circuit 32, the data comparison circuit 34, and the determination circuit 12 shown in FIG. 11. As described above, the output of the data comparison circuit 34 is controlled by the verification control signal from the WP bit selection circuit 33 and output to the determination circuit 12 . Furthermore, control of the data comparison circuit 34 is performed by a CAM mode signal to rewrite the mode signal of the CAM cell. In addition, the control of the expected value holding circuit 32 is performed by an interface mode setting signal.

third embodiment

Next, a third embodiment of the present invention will be described with reference to FIG. 18 . The CAM data written into the CAM cell array 4 is read when the switch 61 is turned on when the power is turned on or when the hardware is reset, and is transferred to a volatile storage body 11 such as an SRAM shown in FIG. 18 . Since the CAM data is read from the volatile memory bank 11, the read access speed of the general cell array 3 is not delayed. In this embodiment, when programming to the CAM, the data stored in the volatile memory bank 11 is used as expected value data, and is compared with the data read from the CAM cell by the data comparison circuit 34 .

Except when verifying the programmed data of the CAM cell array 4 , the switch 62 is switched by the CAM mode signal, thereby connecting the expected value holding circuit 32 and the data comparing circuit 34 . Thereby, verification using the expected value holding circuit 32 can be performed when verifying the general cell array 3 .

FIG. 19 shows the configuration of the WP bit selection circuit 33. As shown in FIG. In this embodiment, when the AND gate 53 of the second embodiment is not provided and the I/O mode is set by the interface mode setting signal, the I/O input signal I/O (0) to (15) It is directly output as a verification control signal. When in the address mode, the switches 54-(0) to 54-(15) are turned off by the interface mode setting signal, and the decoding signal from the decoder 51 is output. When the address mode is set, a WP-CAM address designation signal is input to the decoder 51 and the signal is analyzed to determine the WP-CAM cell designated for programming. Then, a high-level verify control signal indicating that the WP-CAM cell has been designated for programming is output to the volatile memory bank 11 . Verify control signals corresponding to other WP-CAM cells not designated for programming are output at a low level.

In the volatile memory bank 11, there are two storage areas for holding data read by the CAM cells. The first storage area is an area for storing data whose data is verified to be stored in the CAM unit through verification. That is, information of the same nature as the nonvolatile memory bank information in the CAM cell array after CAM cell programming (including verification) is retained. Therefore, in normal operation of the general cell array 3, when a circuit required for operation requires data of a CAM cell, data of the first memory area is output. In addition, the second storage area is used as a temporary storage area, and is an area for storing data of CAM cells that have been pre-read during programming or the like.

When the verification control signal is input from the WP bit selection circuit 33, the volatile memory bank 11 will output "0" as the expected value of the WP-CAM unit specified according to the verification control signal as shown in FIG. the data read. In addition, during pre-reading, the data stored in the second storage area is directly output (initially passed) as the data of the WP-CAM unit corresponding to other low-level verification control signals.

Referring to the flowchart of FIG. 20 and FIG. 21, the operation sequence when setting the I/O mode of this embodiment and programming the CAM cell array 4 will be described. First, the CAM programming setting signals (I/O-0 to I/O-15) of the WP-CAM units to be programmed are input from the respective I/Os (step S30). Information "1" for indicating program execution is input to the I/O corresponding to the WP-CAM cell to be programmed, and information "0" is input to other I/Os.

Then, the data is pre-read by the WP-CAM unit, and the data writing status of each WP-CAM unit is judged (step S31). When it is in a state where data has been written and programmed, information “0” is stored, and when it is an erased state where no data has been written, information “1” is stored.

Next, write is set by the I/O input signal, and the current state of the WP-CAM cell in the erased state is detected (step S32). The WP-CAM cells whose data of the pre-read WP-CAM cells are "1" in the erased state and whose I/O input is "1" are detected. Also, when the WP-CAM cell designated to be written has finished programming, this process is ended, and an error signal is output. In addition, the processing described so far is performed by the controller 8 .

Next, the detected WP-CAM cells are programmed (step S33). When programming is performed, verification is performed in the verification circuit 13 to determine whether or not data has been reliably written in the WP-CAM cell. At this time, the switches 54-(0) to 54-(15) provided in the respective I/Os are set to be on by the interface mode setting signal. In addition, the decoder 51 stops operating according to the interface mode setting signal input through the inverter 52 .

The WP bit selection circuit 33 directly outputs the input signals of I/O-(0) to I/O-(15) to the volatile memory bank 11 as verify control signals. That is, since the I/O input is "1" in the WP-CAM cell designated for programming, a high-level signal is output as a verification control signal. The verification control signals corresponding to other WP-CAM units become low level.

The volatile memory bank 11 outputs the expected value "0" as the data of the WP-CAM cell designated by the high-level verification signal to the data comparison circuit 34 (see FIG. 21). The data stored in the pre-reading of the second storage area is output as the expected value data of other WP-CAM units (refer to FIG. 21).

Each data comparison circuit 34-(0) to 34-(15) compares the data read from each WP-CAM cell after programming with the expected value read from the volatile memory bank 11 (step S34). Since the data read from the unprogrammed WP-CAM unit must be the same as the expected value, the detection result that the data of the programmed WP-CAM unit is consistent with the expected value will directly become the determination result of the verification. When the data read by the WP-CAM unit does not agree with the expected value (NO at step S35), the operation returns to the programming step (step S33). When the data read by the WP-CAM unit coincides with the expected value (YES in step S35 ), the data comparison circuit 34 outputs a match signal indicating the coincidence to the decision circuit 12 . When all the matching signals of the data comparison circuits 34 indicate matching, a signal indicating that the verification is passed is output to the controller 8 (step S36). When the verification is successful, read data from the WP-CAM unit or the sense amplifier, and store the data in the first storage area of the volatile memory bank 11 as the data of the formal WP-CAM unit (step S37 ).

In this embodiment, since the comparison result of the data comparison circuit allocated to the unprogrammed CAM cell is controlled by dummy pass, the verification can reflect the programming result of the programmed CAM cell.

Next, referring to the flowchart of FIG. 22 and FIG. 23, the operation procedure in the address mode will be described. First, a WP-CAM address specifying signal of a WP-CAM cell to be programmed is input. Analyze the WP-CAM address specifying signal with a decoder (step S40), thereby generating an address corresponding to the actual WP-CAM unit to be programmed. In the verification circuit 13, the WP-CAM address designation signal is also decoded by the decoder 51. Then, a verify control signal for designating a WP-CAM cell to be programmed is output to the volatile memory bank 11 .

Next, the data stored in the WP-CAM cell selected by the decoding result is read out by pre-reading (step S41). The pre-read data is judged, and the data writing status of the WP-CAM unit is judged.

When it is determined that the WP-CAM cell is in the erased state (Yes in step S42), write data into the cell to make it into the programmed state (step S43). When it is determined that the WP-CAM unit is in the programming state (step S42: No), it is considered that the programming is completed and the process ends.

Thereafter, the detected WP-CAM cells are programmed and verified in the same manner as the flow chart shown in FIG. 20 . At the time of verification, the volatile memory bank 11 outputs an expected value "0" to the data comparing circuit 34 (see FIG. 23 ) as the data of the WP-CAM cell designated by the high-level verify control signal. The pre-reading data stored in the second storage area is directly output as expected value data of other WP-CAM units (see FIG. 23). Each data comparison circuit 34 - ( 0 ) to 34 - ( 15 ) compares the data read by each WP-CAM cell after programming with the expected value read by the volatile memory bank 11 . When the data read by the WP-CAM unit after programming is consistent with the expected value, a signal indicating that the verification is passed is output to the controller 8 . When the verification is successful, the data is read from the WP-CAM unit or the sense amplifier and stored in the first storage area of the volatile memory bank 11 as the data of the official WP-CAM unit.

Fig. 24 shows the detailed structure. In the semiconductor device shown in FIG. 24, the input of the data comparison circuit 34 is switched by a CAM mode signal. That is, in the CAM mode, the output of the volatile memory bank 11 is input to the data comparison circuit 34, and in the normal operation, the output of the expected value holding circuit 32 is input to the data comparison circuit 34.

The described embodiments are preferred embodiments of the present invention. However, the present invention is not limited to these examples, and various modifications can be made without departing from the spirit of the present invention.

For example, the volatile memory body 11 may be formed with only one storage area (first storage area). The CAM data written in the CAM cell array 4 is read by turning on the switch 61 at the time of power supply or hardware reset, and transferred to the volatile memory bank 11 (first storage area). At the time of pre-reading, by reading the information of the volatile memory bank 11, WP-CAM cells whose data is "1" in the erased state and whose I/O input is "1" are detected. Then, program the detected WP-CAM cells. When programming, the verification circuit 13 will verify to determine whether the data has been written into the WP-CAM cell. The WP bit selection circuit 33 will output a high-level signal to the volatile memory bank 11 as a verification control signal to the WP-CAM unit specified by programming, and output a low-level signal as a verification corresponding to other WP-CAM units control signal. Regardless of the information stored as the WP-CAM cell data designated by the high-level verification control signal in the readout portion (not shown) of the first storage area, the volatile memory bank 11 outputs the expected value "0" to the data comparison circuit 34. More simply, a clamp circuit using a verify control signal is connected to the readout portion of the first storage area in order to clamp the outputs to "0". The information stored in the first storage area is output as expected value data of other WP-CAM cells without operating the clamping circuit. Each data comparison circuit compares the data read from each WP-CAM cell after programming with the expected value read from the volatile memory bank 11 . When the verification results are consistent, the switch 61 is turned on to read data from the WP-CAM unit or sense amplifier, and store it in the first storage area of the volatile memory bank 11 as the data of the formal WP-CAM unit .

In addition, the component configuration of the volatile memory bank 11 may be a so-called static memory bank unit, or may be a latch circuit formed of logic components suitable for peripheral circuits.

Claims (28)

1. semiconductor device, possessing has:

Cell array is in order to the operating and setting information of storing semiconductor device; And

Control part is in order to control reading and writing of described cell array; And,

Described control part is to distribute different row addresses each function to described operating and setting information.

2. semiconductor device as claimed in claim 1, wherein, described control part is to distribute different column addresss each function to described operating and setting information.

3. semiconductor device as claimed in claim 1, wherein, described control part is to distribute a plurality of difference in functionalitys of continuous column address to described operating and setting information.

4. semiconductor device as claimed in claim 1, wherein, described control part is to distribute described operating and setting information extremely with the selected a plurality of row of described row address.

5. semiconductor device as claimed in claim 1, wherein, described control part is to distribute described operating and setting information to all I/O with the selected any row of described row address.

6. semiconductor device as claimed in claim 1, wherein, the wiring graph with local bitline between the storage unit of described different row is cut off.

7. semiconductor device as claimed in claim 1, wherein, the storage unit of described different row is to have the switch that is connected with the bit line that is disposed at respective column in order to switch respectively.

8. semiconductor device as claimed in claim 1, wherein, described cell array has a plurality of storage unit at each row, and the described a plurality of storage unit that do not store described operating and setting information are to separate from the bit line that is disposed at respective column.

9. semiconductor device as claimed in claim 3, wherein, described control part is all word lines of selecting on the described cell array, and switches described column address and reading of data continuously.

10. as each described semiconductor device in the claim 1 to 9, wherein, described control part has the number translated of the appointed storage unit map table for the address of corresponding storage unit.

11. an address distribution method is the address distribution method to the cell array of the operating and setting information that stores semiconductor device, wherein, distributes different row addresses each function to described operating and setting information.

12. address distribution method as claimed in claim 11 wherein, distributes different column addresss each function to described operating and setting information.

13. address distribution method as claimed in claim 11 wherein, distributes a plurality of different function of continuous column address to described operating and setting information.

14. address distribution method as claimed in claim 13 wherein, is selected all word lines on the described cell array, and is switched described column address and reading of data continuously.

15. a semiconductor device, possessing has:

Cell array is in order to the operating and setting information of storing semiconductor device;

Write circuit is programmed to a plurality of unit of described cell array simultaneously; And

Proof scheme in described a plurality of unit, is verified only actual programmed result of carrying out programmed cells.

16. semiconductor device as claimed in claim 15, wherein, described proof scheme possesses and has:

Comparator circuit, expectation value data that obtained when normally programming and described programming back compare from the data that described unit or sensing amplifier read; And

Control part is in order to the virtual control of passing through of the comparative result that makes the described comparator circuit that described unit distributed that does not carry out described programming.

17. semiconductor device as claimed in claim 16, wherein, described control part is to be designated as programmed cells by the outside input, and judgement is in the unit of wiping the position before described programming, and has:

The expectation value holding circuit, according to indication from described control part, the expectation value data that obtained when being created in the described unit of programming, and export the described comparator circuit that described unit distributes to.

18. a semiconductor device has:

Cell array is in order to the operating and setting information of storing semiconductor device;

Write circuit is programmed to a plurality of unit of described cell array simultaneously;

Volatile memory circuit is in order to store the storage data of the described a plurality of unit before the described programming; And

Proof scheme in described a plurality of unit, directly uses described storage data to verify to carrying out programmed cells, and carries out described programmed cells and use the expectation value data that obtained when normally programming to come the verification of programming result actual.

19. semiconductor device as claimed in claim 18, wherein, described proof scheme possesses and has:

A plurality of comparator circuits, expectation value data that will be obtained when normally programming and described programming back compare from the data that described unit or sensing amplifier read; And

Control part is judged the actual programmed cells of carrying out, and uses the described expectation value data that obtained when normally programming to come the verification of programming result to the described comparator circuit that this unit distributed.

20. semiconductor device as claimed in claim 19, wherein:

Described control part is for being designated as programmed cells by the outside input, and the expectation value data that the described expectation value data change of will be before described programming storing for the described volatile memory circuit of the unit correspondence of wiping the position is obtained during for programming, and export described comparator circuit to.

21. as claim 16 or 19 described semiconductor devices, wherein, described control part from the outside respectively to the input of described a plurality of unit in order to representing whether described a plurality of unit sets the command signal of programming object for, and whether be that the actual programmed cells of carrying out is judged in the unit of wiping the position by the unit that described programming object is set in judgement for.

22. as claim 16 or 19 described semiconductor devices, wherein, described control part is deciphered the unit of setting programming object with judgement for the address information of outside input, and judge whether the unit of setting described programming object for is the unit of wiping the position, and judge the actual programmed cells of carrying out.

23. as the semiconductor device of claim 16 or 19, wherein, the mode switching signal that described control part is imported by the outside switches the interface in order to the unit of specifying described programming object.

24., wherein, be to share described proof scheme to the checking after weaving in order to the cell array of storing described operating and setting information and to the checking after programming in order to the general cell array of storage general data as the semiconductor device of claim 15 or 18.

25. semiconductor device as claim 16 or 19, wherein, the input of described comparator circuit is in order to switching to the mode signal of programming to the cell array of storing described operating and setting information, and with described expectation value data with from described unit or the sensing amplifier data of reading compare.

26. semiconductor device as claim 19, when the cell array of storing described operating and setting information is programmed, use the output of described volatile memory circuit and compare at described comparator circuit, and to the general cell array of storage general data when programming, use the output of the expectation value holding circuit of the expectation value data that obtained when keeping described unit to be programmed to carry out the compare operation of described comparator circuit.

27. a verification method is the verification method of cell array that stores the operating and setting information of semiconductor device, in a plurality of unit of described cell array, only verifies actual programmed result of carrying out programmed cells.

28. a verification method is the verification method of cell array that stores the operating and setting information of semiconductor device, in described a plurality of unit, the data of not carrying out before the described programming that described programmed cells directly uses this unit is verified; And carry out described programmed cells and use the expectation value data that obtained when normally programming to come the verification of programming result actual.

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