CN100476675C - On-Chip Power - Google Patents

Abstract

One technique for extracting power from external signal circuits to power on-chip components of an integrated circuit diode (ICD) utilizes integrated diodes and capacitors. During the time the ICD blocks the flow of external current, the capacitor is charged by an externally applied voltage. The charged capacitor then acts as a battery to power the on-chip circuitry, providing active control for ICD operation. The ICD can be provided as a two-terminal discrete diode, or integrated into a larger IC. The foregoing technique can be used in a "self-powered" MOSFET IC (ICM) by using a low power logic signal to trigger an internal circuit that will provide a much larger gate drive than the logic signal can provide. The circuit can also be provided as a discrete three-terminal component, or integrated into a larger IC.

Description

On-Chip Power

This application claims the benefit of U.S. Provisional Patent Application No. 60/451,060, filed February 26,2003.

technical field

This invention relates to integrated circuit semiconductor diodes and transistors.

Background technique

Semiconductor devices tend to be divided into discrete components and integrated circuits. Discrete devices include: single function components such as bipolar transistors, junction field effect transistors, surface field effect transistors, silicon controlled rectifiers, etc.; and certain integrated components such as insulated gate bipolar transistors. One characteristic common to all discrete components is that no external power supply is required.

Recently, a new form of discrete circuit has entered the market, which is a high-efficiency diode made of surface field-effect transistors, the integrated circuit diode (ICD). The current form of this circuit (the passive form) does not utilize any on-chip drive circuitry; however, when an external or internal power supply is added, these circuits can significantly improve its performance.

Utilizing an external power supply for this purpose tends to be less attractive due to the added circuit board complexity. However, it has the advantage that external signals are not altered when drawing the charge required for the on-board supply voltage. In most applications, the convenience of a self-powered circuit is advantageous.

In commonly used semiconductor diodes, forward conduction is limited to the value of the leakage current until the forward voltage bias reaches a value characteristic of the particular type of semiconductor device. As an example, silicon pn junction diodes do not conduct significantly until the forward bias voltage is about 0.6-0.7 volts. Due to the nature of the Schottky barrier, many silicon Schottky diodes can begin conducting at lower voltages, such as 0.4 volts. A germanium pn junction diode has a forward conduction voltage drop of about 0.3 volts at room temperature. However, such devices are rarely used, not only because they are not compatible with silicon integrated circuit fabrication, but also because of their temperature sensitivity and other undesirable characteristics.

In some applications, diodes are not used due to their rectifying properties, but are always forward biased to provide their characteristic forward voltage drop. For example, in integrated circuits, diodes or diode-connected transistors are often used to provide a forward conduction voltage drop substantially equal to the base-emitter voltage of another transistor in the circuit.

In circuits that take advantage of the true rectifying properties of semiconductor diodes, the forward conduction voltage drop of the diodes is often a considerable disadvantage. As a specific example, a transformer is typically used in a DC-DC step-down converter, where a semiconductor switch controlled by a suitable controller periodically connects and disconnects the primary winding of the transformer from the DC power source. The secondary voltage due to its rectifying properties is connected to the output of the converter via a diode or via another semiconductor switch. The controller varies the duty cycle or frequency at which the primary coil is connected to the power supply as needed to maintain the desired output voltage. If a semiconductor switch is used to connect the secondary coil to the output, the operation of this second switch is also controlled by the controller; one form of the switch configuration circuit described above is known as a synchronous rectifier.

The advantage of using semiconductor switches to couple the secondary coil to the output is the low forward voltage drop. The disadvantage is that careful timing control is required to maintain the efficiency of energy transfer from the primary coil to the secondary coil over the entire operating temperature range of the converter. . The timing of the primary-to-secondary switching is critical and the phase delay of the transformer and other components must be considered. Obviously the cost of these circuits is very high.

The advantage of using a semiconductor diode for this purpose is that it eliminates the need for control of the secondary switch, but the disadvantage is that the forward conduction voltage drop of the semiconductor diode is applied to the secondary circuit. This has at least two extremely large disadvantages. First, the forward voltage drop of the semiconductor diode device can greatly reduce the efficiency of the converter. For example, newer integrated circuits commonly used in computer systems are designed to operate with lower supply voltages such as 3.3 volts, 3 volts and 2.7 volts. With a 3 volt supply, applying a series voltage drop of 0.7 volts means that the converter is actually operating within a load of 3.7 volts, thus limiting the efficiency of the converter to 80%, even before accounting for other circuit losses in this way.

Second, the aforementioned efficiency loss represents power loss within the diode, which generates heat therein. This limits the power conversion capability of the integrated circuit converter and in many applications requires the use of discrete diodes with appropriately sized heat sinks, increasing the size and cost of the overall circuit. Obviously any improvement in forward voltage drop will have a significant impact on overall circuit performance.

Another commonly used AC-DC conversion circuit is a full-wave bridge rectifier, usually coupled to the secondary winding of a transformer whose primary winding is driven by an AC power source. Here the voltage drop of the two diodes is imposed across the peak DC output, making circuits using conventional diodes extremely inefficient and increasing the circuit's heat generation, which needs to be dissipated through large discrete components, heat dissipation Dissipated by structures etc., depending on the DC power to be supplied.

Therefore, semiconductor diodes with low forward voltage drop are very advantageous for use as rectifying elements in circuits where the diodes will be subject to both forward and reverse bias voltages from time to time. While discrete forms of such diodes have many applications, it is further desirable that such diodes be compatible with integrated circuit fabrication techniques so that they can be implemented in integrated circuit form and as part of a larger integrated circuit. Furthermore, while reverse current leakage is always undesirable and usually must be compensated by additional forward conduction current, thereby reducing circuit efficiency, reverse current leakage can have other and more significant detrimental effects on certain circuits . Therefore, it is further desirable for such semiconductor diodes to have a low reverse bias leakage current.

ICDs in passive form offer lower forward voltages compared to Schottky diodes and have enhanced reliability at a competitive price. They also provide attractive alternatives to the high-voltage segment of the synchronous rectifier market; however, they cannot replace the entire synchronous rectifier market.

Contents of the invention

The present invention provides circuits and methods that, when integrated into an IC, will provide on-chip power to run control circuitry on the IC. During the "off" portion of the IC's cycle, it draws power from the applied signal. For example, in the case of an IC equivalent to a rectifier, the circuit will draw power to the power supply with a large reverse voltage during the off state of the rectifier. In the case of an IC, which behaves like a transistor (which does not reverse the applied voltage), when a large bias is developed across the IC, the power supply will draw its power during the "off" state.

During the "on" state of these ICs, the power supply will provide power to drive control circuitry that can be used to produce a more conductive "on" state and a lower leakage "off" state. As far as ICD is concerned, the forward voltage can be greatly reduced to a level equal to or better than that of synchronous rectifiers. In the case of SFET ICs, the gate drive can be significantly enhanced, providing a reduced "on-resistance" equivalent to a reduction in forward voltage.

Description of drawings

Figure 1 is a schematic diagram of a prior art ICD. "Signal 1" (cathode) and "Signal 2" (anode) are standard input signals to the diodes, eg sine or square waves. A "passive ICD" is an n-channel MOSFET device equivalent to a diode.

Figure 2 shows the addition of capacitors and diodes to an ICD chip. This allows the capacitor to charge and act as a battery, driving the control circuit to run the ICD gate.

Figure 2A shows the same principle as Figure 2, except that the diode is moved to the other side of the capacitor. This inverts the polarity of the readout signal, hence the symbols: - and + in Figures 2 and 2A.

Figure 3 shows the same principle, but driving MOSFETs. The integrated circuit MOSFET (ICM) device has external inputs corresponding to source, drain and gate.

Figures 4 and 4A show control circuits using + and - readout configurations, respectively.

Fig. 5 shows the same type of drive circuit as in Figs. 4 and 4A, but with modified n-channel MOSFETs.

Fig. 6 shows a sampling control circuit for a p-channel MOSFET.

Detailed ways

Referring to FIG. 1 , a prior art schematic diagram of an ICD (Integrated Circuit Diode) is shown. Due to the gate connection and depletion threshold voltage, the device acts as a low forward voltage diode. It is specifically designed to handle alternating polarity. Clearly, the addition of an external power supply and control logic would greatly enhance the functionality of this device by allowing the gate to be driven well above the drain potential when on.

The device shown in Figure 1 is an n-channel device. Typically, in conventional field effect devices, the body or backgate is connected to a source of charge carriers when the device is turned on. In this regard, the notation of source and drain as used herein means that source is a region that acts as a source of charge carriers when the device is turned on or conducting, and drain is another region of the same conductivity type. Thus, charge carriers flow from the source through the channel to the drain during conduction. In the case of the ICD of FIG. 1 , conduction occurs when signal 2 is at a higher voltage than signal 1 . Since this figure shows an n-channel device and the previous definitions of source and drain, it should be noted that in the case of a passive integrated circuit diode (ICD), the body or back gate of the ICD is connected to the drain , rather than the source. There is also a slightly negative threshold on the ICD characteristic. Thus, for an ICD, when the source and drain are at the same voltage, although the current is zero because the source and drain are at the same voltage, the channel has a certain degree of conductivity. For n-channel ICDs, conduction along the channel will cause an IR drop in the channel when the drain voltage rises above the source voltage, while the channel near the source has a voltage close to the source voltage . This increases the gate-channel voltage in this region of the channel, thereby reducing the channel resistance. The above-mentioned effect is gradual along the channel, so that most of the channel becomes closer to the source voltage, and thus will be more conductive. Therefore the total channel resistance becomes lower and lower with increasing drain voltage, allowing high current levels to be carried at relatively low forward voltage drop. On the other hand, when the source voltage is higher than the drain voltage, the conduction of the channel brings the voltage of the channel adjacent to the source close to the source voltage and thus has a gate which causes high channel resistance in that region polar channel voltage. In this way, although the leakage current will increase with the increase of the reverse bias on the ICD, the channel resistance will become high, and the channel resistance will increase with the increase of the reverse bias, thus the channel resistance increases with increasing reverse bias, and thus limits the increase in leakage current with increasing reverse bias. This is the standard Id/Vds characteristic of a MOSFET with constant gate potential.

In common diode terminology, the anode of a diode is the positive terminal during forward conduction, and the cathode is the negative terminal. For n-channel ICDs, the forward conducting drain corresponds to the anode, and the source, which is an n-type substrate, corresponds to the cathode. If a p-channel ICD is to be built, then the anode will correspond to the source which is a p-type substrate, and the cathode to the drain. Due to the difference in carrier mobility, the discussion of ICDs will focus on n-channel devices, with the understanding that changing material type and circuit polarity will result in p-channel ICDs.

It will be apparent to those skilled in the art that JFETs can be used instead of MOSFETs to form ICDs and that ICMs can also be made with JFETs.

In the following disclosure, with reference to passive n-channel ICDs and active n-channel and p-channel ICMs, active devices refer to three-terminal devices with separate gate connections. These devices are designed with MOSFETs and the body or back gate of the ICD is connected to the drain of the ICD and the source of the ICM.

The use of discrete MOSFETs driven by control logic is well known in the art, such as synchronous rectifiers. It is also known to add control logic to the IC, which is the integration of on-chip power supplies such as the backgate power supply on the IC, which provide a negative potential to the substrate to control transistor thresholds; however, instead of using an external power supply connection it will be self-sufficient The integration of power supplies into ICs is new in the field. The purpose of the present invention to incorporate circuitry into this IC is on-chip charge storage, thereby acting as an active battery to power the control logic. The energy stored in the battery is extracted from the actual signal lines during the "off" state of the IC.

Figure 2 is a schematic diagram of an active ICD utilizing a control circuit to power its gate electrode. The energy used to drive the control circuit is extracted from the signal lines by adding capacitors and diodes. Regardless of whether the polarity is actually reversed, during the reverse biased state of the ICD (off state, no current flow but high reverse voltage), the diode allows the capacitor to charge and when the potential across the ICD drops below the charging potential When the diode prevents the capacitor from discharging.

As can be seen, if there is an alternating voltage across the diode and load (load not shown), then the peak-to-peak voltage will be stored on the capacitor with positive potential on the signal 1 side and negative potential on the signal 2 side. This effectively acts as a half wave rectification circuit. Also, note that the control circuit will need a sense line to synchronize its control action with the applied signal. This readout line must be isolated from the charge storage device. In the case of Figure 2, the diode acts as an isolation and allows the readout potential to follow the signal 2 independent of the capacitor.

Figure 2A shows the configuration of Figure 2, except that the positions of the diodes and capacitors are swapped. This moves the readout connection to Signal 1; however, the polarity across the capacitor is not reversed. This configuration is arbitrarily denoted with a "-readout" notation relative to the "+readout" notation of FIG. 2 . The completed ICD functions identically to the external circuitry for both - and + readout configurations. Only internal design differences distinguish the two readouts.

Obviously, if a standard MOSFET is substituted into this circuit, which means that there is no change in the polarity of the signal voltage, the diode can be reversed so that it will charge the capacitor during the transistor's off state. See Figure 3 for comparison with Figure 2. This will reverse the polarity on the capacitor and require appropriate modifications to the control circuit. This configuration would allow a MOSFET transistor without an additional power connection to operate with very low visible gate drive; using this drive to trigger a larger drive from the control circuit. One of the design issues associated with power MOSFETs is the need to provide sufficient drive current for their large gate structures. ICM eliminates this concern.

The control circuit can take many forms. The examples described here are used to illustrate the application of the present invention, rather than specific control circuits. Figures 4 and 4A use the same control circuit. Due to the different configuration of the diodes and capacitors, the power lines are routed differently, and the sense lines have reversed polarity. Figure 4 uses the + readout configuration of Figure 2, while Figure 4A uses the - readout configuration of Figure 2A.

The control circuit is designed to take the sense input and use it to control the potential applied to the gate of the N-channel MOSFET. Resistors R3 and R4 and transistors M1 and M2 form a bistable latch. The state of the latch is determined by the potential of the readout signal (trigger signal in FIGS. 4 and 4A). Resistors R3 and R4 are pull-up resistors that provide power to maintain the state of the latch while limiting charge drain on the internal supply. In FIG. 4, the positive trigger signal turns on transistor M1 and turns off transistor M2. This makes the resistor R4 - transistor M2 node V+. Zener diodes limit the extent of this voltage excursion to their rated Zener voltage. This positive voltage turns on transistor M3, the source of which is connected to the gate of the active ICD. When the source potential rises to the Zener potential, charge transfer stops, limiting the positive potential applied to the gate of the active ICD to the Zener voltage plus a small increment.

The configuration of transistor M3 with a zener diode prevents excessive voltage on the gate of the ICD, which could cause breakdown of the gate oxide. When the trigger signal changes polarity, the state of the latch is inverted such that the gate of transistor M3 is driven negatively, while the gate of transistor M4 is positively driven such that the gate of the ICD and the source of transistor M3 is pulled negatively.

As can be seen, the gate of the active ICD is driven between the shutdown signal (V-) and the positive voltage set by the Zener diode. This allows the ICD in the on state to have a much lower voltage drop than in the passive state of FIG. 1 . Looking at Figures 4 and 4A, it can be seen that in both cases the V+ and V- signals are sent to the same point within the control circuit, with V+ going to the resistor side of the latch and V- going to the MOSFET side of the latch. However, the read signal is sent to the opposite latch pole. In FIG. 4 it goes to the drain of transistor M2, while in FIG. 4A it goes to the drain of transistor M1. This is due to the polarity inversion of the readout signal. In both circuits, the positive going state (the gate of the ICD is on) corresponds to Signal 1 being negative with respect to Signal 2.

While the shaping properties of a latch are convenient, in many cases the entire latch is not required for proper circuit operation. For example, in Figure 4A, if the resistor R3 and transistor M1 are removed, the circuit will still work properly with good input signal performance.

Figure 5 shows the same control circuit with N-channel MOSFETs. Note that the diodes have been reversed so that the voltage on the ICM will charge the capacitor when the ICM is off. Now the read signal is the gate input electrode.

Figure 6 shows the same control circuit, but using p-channel MOSFET devices. Note that all MOSFETs are now p-channel devices and the polarity of the voltage applied to the control circuit is reversed.

In the ICM of FIGS. 5 and 6, the control circuit receives the gate control signal and provides an enhanced gate control signal to the field effect transistor. This boosted signal can be boosted voltage swing (larger swing), or can be boosted current drive to quickly charge and discharge transistor gate capacitance (especially in the case of power transistors), can be boosted gate drive The speed of transitions can be enhanced to increase the speed of turn-on and turn-off, or any combination of these or other parameters can be enhanced. Also, due to their improved performance, ICMs can be used in larger integrated circuits, or can be packaged as three-terminal devices and used in place of traditional FETs.

Although certain preferred embodiments of the present invention have been disclosed and described herein, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. change.

Claims (31)

1. A circuit comprising: An integrated circuit comprising: a charge storage device; a current steering device; a field effect transistor having a body, a source, a drain and a gate; and a control circuit, the drain connected to the body, the charge storage device and A current steering device is connected in series between the source and drain terminals of the transistor, the charge on the charge storage device is coupled to and serves as a power supply for a control circuit which has an output coupled to the gate of the field effect transistor, when the source and The control circuit turns on the transistor when the voltage between the drain is of a first polarity, and turns off the transistor when the voltage between the source and drain is of a second polarity, and the control circuit turns off the transistor when the voltage between the source and drain In the second polarity the current steering device has a polarity to charge the charge storage device. 2. The circuit of claim 1, wherein the charge storage device is a capacitor. 3. The circuit of claim 2, wherein the current steering device is a diode. 4. The circuit of claim 1, wherein the circuit is packaged as a two-terminal device. 5. The circuit of claim 1, wherein said field effect transistor is a FET. 6. The circuit of claim 1, wherein said field effect transistor is an n-channel MOSFET, and said field effect transistor is turned on when a source voltage is lower than a drain voltage. 7. The circuit of claim 1, wherein said field effect transistor is a p-channel MOSFET, and said field effect transistor is turned on when the source voltage is higher than the drain voltage. 8. The circuit of claim 1, wherein the field effect transistor is an n-channel JFET, and the field effect transistor is turned on when the source voltage is lower than the drain voltage. 9. The circuit of claim 1, wherein the field effect transistor is a p-channel JFET, and the field effect transistor is turned on when the source voltage is higher than the drain voltage. 10. A circuit comprising: An integrated circuit comprising: capacitor; diode; a field effect transistor having a source, a drain, a gate, and a body connected to the source; and Control circuit; The capacitor and diode are connected in series between said source and drain, the diode is turned on when the transistor is off to charge the capacitor, which is coupled to the control circuit and acts as its power supply, the control circuit has a gate control input and provides an output coupled to the gate of the field effect transistor for providing an enhanced gate control signal to the field effect transistor both when the field effect transistor is turned on and when the field effect transistor is turned off in response to the gate control input. 11. The circuit of claim 10, wherein the field effect transistor is an n-channel MOSFET. 12. The circuit of claim 10, wherein the field effect transistor is a p-channel MOSFET. 13. The circuit of claim 10, wherein the field effect transistor is an n-channel JFET. 14. The circuit of claim 10, wherein the field effect transistor is a p-channel JFET. 15. The circuit of claim 10, wherein the circuit is packaged as a three-terminal device. 16. The circuit of claim 10, wherein the enhanced gate control signal provided to the field effect transistor is enhanced in voltage swing compared to the gate control input. 17. The circuit of claim 10, wherein the enhanced gate control signal provided to the field effect transistor is enhanced in current drive compared to the gate control input. 18. The circuit of claim 10, wherein the enhanced gate control signal provided to the field effect transistor is enhanced in speed of gate drive transitions compared to the gate control input. 19. A circuit comprising: An integrated circuit comprising: capacitor; diode; a field effect transistor having a source, a drain, a gate, and a body connected to the source; and, Control circuit; The capacitor and diode are connected in series between said source and drain, the diode is turned on when the transistor is off to charge a capacitor with respect to said source, which capacitor is coupled to the control circuit and acts as its power supply, The control circuit has a gate control input and provides an output coupled to the gate of the field effect transistor for providing an enhanced gate control signal to the field effect transistor both when the field effect transistor is turned on and when the field effect transistor is turned off in response to the gate control input , the enhanced gate control signal is responsive to the voltage on the capacitor for the case where the field effect transistor is turned on, and the enhanced gate control signal is responsive to the source for the case where the field effect transistor is turned off respond to the voltage on the 20. The circuit of claim 19, wherein when the field effect transistor is on, the enhanced gate control signal is coupled to a voltage across the capacitor, and when the field effect transistor is off, the enhanced gate A pole control signal is coupled to the source. 21. The circuit of claim 20, further comprising a Zener diode coupled to limit a maximum voltage applied from the capacitor to the gate. 22. The circuit of claim 21, wherein the control circuit includes a bistable circuit responsive to the gate control input. 23. The circuit of claim 19, wherein the control circuit includes a bistable circuit responsive to a gate control input. 24. The circuit of claim 19, wherein the field effect transistor is an n-channel MOSFET. 25. The circuit of claim 19, wherein the field effect transistor is a p-channel MOSFET. 26. The circuit of claim 19, wherein the field effect transistor is an n-channel JFET. 27. The circuit of claim 19, wherein the field effect transistor is a p-channel JFET. 28. The circuit of claim 19, wherein the circuit is packaged as a three-terminal device. 29. A method of enhancing a gate control signal input to a field effect transistor having a source, a drain and a gate and responsive to a gate control signal, the method comprising: coupling a capacitor and a diode in series between said source and drain, the capacitor being coupled to said source so that the capacitor is charged by a source-drain voltage when the field effect transistor is off; Powering the gate control circuit with the voltage across the capacitor; coupling a gate control signal to the gate control circuit; causing a gate control circuit to couple the gate to a capacitor when the gate control signal indicates that the field effect transistor is to be turned on; and A gate control circuit is caused to couple the gate to the source when the gate control signal indicates that the field effect transistor is to be turned off. 30. The method of claim 29, wherein the gate control circuit comprises a bistable circuit. 31. The method of claim 29, further comprising limiting a maximum voltage across a capacitor coupled to said gate.

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