CN109586703A - The D-latch of low redundancy nuclear hardening - Google Patents
The D-latch of low redundancy nuclear hardening Download PDFInfo
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- CN109586703A CN109586703A CN201811416960.0A CN201811416960A CN109586703A CN 109586703 A CN109586703 A CN 109586703A CN 201811416960 A CN201811416960 A CN 201811416960A CN 109586703 A CN109586703 A CN 109586703A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
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Abstract
The D-latch of low redundancy nuclear hardening belongs to the nuclear hardening field in IC reliability.Hardware needed for solving traditional D-latch is more, power consumption is high, transmission time is long, although and can realize anti-binode upset, there are anti-binode upset ability is poor, or even cannot achieve the fault-tolerant problem to binode upset.The present invention includes NMOS transistor N1 to N20 and PMOS transistor P1 to P12, and device used is few, and small in size, structure is simple, since device used is few, to reduce the power consumption of entire latch and possess lower hardware spending.The signal of latch inputs only passes through a transmission gate can be for transmission to output port, and data transmission period is short, additionally it is possible to realize to the fault-tolerant of any single node and binode upset, to realize the fault-tolerant protection of anti-single node and binode upset.The present invention can provide protection for the application of IC chip in high radiation environment (such as space flight and aviation and ground nuclear power station).
Description
Technical field
The invention belongs to the field of radioresistance reinforcement in IC reliability.
Background technique
D-latch is chiefly used in integrated circuit, as the memory element of sequence circuit in digital circuit, in certain operations
Sometimes using D-latch as Data buffer in device circuit.But stored function is protected since latch has,
Extraneous radiating particle will change the information of its preservation, so as to cause the mistake of electronic system.
Triplication redundancy is usually used to be reinforced in traditional D-latch, the disadvantage is that required hardware is more, power consumption is high, passes
The defeated time is long, although and can realize anti-binode upset, there are the ability of anti-binode upset is poor, or even cannot achieve pair
Binode upset it is fault-tolerant.Therefore, the problem urgent need to resolve present on.
Summary of the invention
The present invention is in order to which hardware needed for solving traditional D-latch is more, power consumption is high, transmission time is long, although and can
It realizes anti-binode upset, but there are the ability of anti-binode upset is poor, or even cannot achieve to the fault-tolerant of binode upset
Problem, the present invention provides a kind of D-latch of low redundancy nuclear hardening.
The D-latch of low redundancy nuclear hardening, including NMOS transistor N1 to N20 and PMOS transistor P1 to P12；
After the drain electrode of the source electrode, transistor N20 of transistor P12 is connected with the drain electrode of transistor N16 to N17, as latch
One data input pin D of device；
Another data input pin after the drain electrode of transistor N18 is connected with the drain electrode of transistor N19, as latch
DN；Two data input pin received signals of latch are opposite；
A clock signal clk N after the grid of transistor P12 is connected with the grid of transistor N15, as latch
Input terminal；
After the grid of transistor N16 to N20 is connected with the grid of transistor P11, another clock as latch is believed
The input terminal of number CLK；Two clock signal input terminal received signals of latch are opposite；
The drain electrode of transistor P12, the drain electrode of the source electrode of transistor N20, transistor P11 are connected with the drain electrode of transistor N15
Afterwards, as the output end Q of latch；
The source electrode of transistor N16, the grid of transistor N2, the source electrode of transistor N10, the drain electrode of transistor N12 and crystal
After the grid connection of pipe N11, as node A；
The source electrode of transistor N18, the grid of transistor N1, the source electrode of transistor N9, the drain electrode of transistor N11, transistor
After the grid of N12, the grid of transistor P10 are connected with the grid of transistor N14, as node B；
The grid of transistor P5, the grid of transistor N9, the grid of transistor P8, the drain electrode of transistor P6 and transistor N8
Drain electrode connection after, as node C；
The drain electrode of transistor P5, the drain electrode of transistor N7, the grid of transistor P7, transistor N10 grid and transistor
After the grid connection of P6, as node DD；
The drain electrode of transistor P1, the drain electrode of transistor N1, the grid of transistor P3, transistor N4 grid and transistor P2
Grid connection after, as node E；
The source electrode of transistor N19, the source electrode of transistor N3, the drain electrode of transistor N5, the grid of transistor N6, transistor N7
Grid, transistor P9 grid connected with the grid of transistor N13 after, as node F；
The source electrode of transistor N17, the source electrode of transistor N4, the drain electrode of transistor N6, transistor N5 grid and transistor
After the grid connection of N8, as node G；
The grid of transistor P1, the grid of transistor N3, the grid of transistor P4, the drain electrode of transistor P2 and transistor N2
Drain electrode connection after, as node H；
The source electrode of transistor P1 to P9 is connect with power supply, and the source electrode of transistor N1 to N2, transistor N5 are to N6's
The source electrode of source electrode, the source electrode of transistor N7 to N8 and transistor N11 to N13 is connect with power ground；
The drain electrode of transistor P3 is connect with the drain electrode of transistor N3, and the drain electrode of transistor P4 and the drain electrode of transistor N4 connect
It connects, the drain electrode of transistor P7 is connect with the drain electrode of transistor N9, and the drain electrode of transistor P8 is connect with the drain electrode of transistor N10；
The drain electrode of transistor P9 is connect with the source electrode of transistor P10, the drain electrode of transistor P10 and the source electrode of transistor P11
Connection, the source electrode of transistor N15 are connect with the drain electrode of transistor N14, and the drain electrode of the source electrode and transistor N13 of transistor N14 connects
It connects.
Preferably, when clock signal clk is high level " 1 ", latch conducting；Clock signal clk is low level " 0 "
When, latches.
Preferably, when latches low level " 0 ", latch sensitive nodes are B, C, DD, E, F and H；
When latches high level " 1 ", latch sensitive nodes are A, C, DD, E, G and H.
Preferably, the D-latch of the low redundancy nuclear hardening, including normal operating conditions and fault-tolerant operation shape
State.
Normal operating conditions includes following situation:
Situation one: assuming that the data input pin D=1 of latch, then DN=0；
(1) as CLK=1, CLKN=0, at this point, NMOS transistor N2, N4, N5, N8, N10, N11, N16 are beaten to 20
Open, NMOS transistor N1, N3, N6, N7, N9, N12, N13, N14, N15 are turned off, PMOS transistor P1, P4, P5, P8, P9,
P10, P12 are opened, and PMOS transistor P2, P3, P6, P7, P11 are turned off, at this point, A=DD=E=G=Q=1, B=C=F
=H=0；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P12 are closed, PMOS crystal
Pipe P11 is opened, and therefore, the output end Q of latch will connect power supply voltage by the PMOS transistor P9 to P11 of conducting,
Due to latch inner interlocked, output end Q will save always 1 state, and latch enters latch mode；
Situation two: assuming that the data input pin D=0 of latch, then DN=1；
(1) as CLK=1, CLKN=0, at this point, NMOS transistor N1, N3, N6, N7, N9, N12 to N14, N16 extremely
N20 is opened, and NMOS transistor N2, N4, N5, N8, N10, N11, N15 are turned off；PMOS transistor P2, P3, P6, P7, P12
It opens, PMOS transistor P1, P4, P5, P8, P9 to P11 are turned off, at this point, A=DD=E=G=Q=0, B=C=F=H
=1；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P12 are closed, NMOS crystal
Pipe N15 is opened, and therefore, the output end Q of latch will power on ground by the NMOS transistor N13 to N15 be connected, due to
The reason of latch inner interlocked, output end Q will save always 0 state, and latch enters latch mode.
Fault-tolerant operation state occurs during latches, and fault-tolerant operation state includes following situation:
Situation one:
When latches low level " 0 ", sensitive nodes B, C, DD, E, F and H；It is any in above-mentioned sensitive nodes
When one or two sensitive nodes is flipped, due to being constantly present two in the sensitive nodes and node A, G that are not flipped
A or more than two node states remain unchanged, and therefore, can restore above-mentioned one or two node being flipped to respective
State originally；
Situation two:
When latches high level " 1 ", sensitive nodes A, C, DD, E, G and H are any in above-mentioned sensitive nodes
When one or two sensitive nodes is flipped, due to being constantly present two in the sensitive nodes and node B, F that are not flipped
A or more than two node states remain unchanged, and therefore, can restore above-mentioned one or two node being flipped to respective
State originally.
Principle analysis:
Fault-tolerant operation state is unrelated with the received data-signal of data input pin D of latch, and fault-tolerant operation state occurs
In latches state, related with the data that node each inside latch latches, the D-latch of low redundancy nuclear hardening is fault-tolerant
Working state analysis is as follows: clock signal clk=0, CLKN=1,8 internal nodes A=DD=E=G=1, B=C=F=H
=0, output end Q=1, the inside sensitive nodes of the latch have 6, respectively A, C, DD, E, G and H at this time: described above-mentioned 6
Specific situation when one or two of a sensitive nodes are flipped is as follows:
1, when node A is turned to 0, NMOS transistor N11, N2 will be closed.Remaining node will keep respective
State it is constant, therefore, PMOS transistor P8 and NMOS transistor N10 will be opened always, and A node will be pulled back to original
1, then, NMOS transistor N11, N2 will be opened.
2, when node C is turned to 1, PMOS transistor P5 and P8 will be closed, and NMOS transistor N9 will be beaten
It opens.Remaining node will keep respective state constant, and therefore, NMOS transistor N8 will always be in open state, this will drop-down
Recovery nodes C is to original correct 0 state.
3, when node DD is turned to 0, PMOS transistor P7 and P6 will be turned on.Due to node G state not
It changes, or 1 original state, this will be so that NMOS transistor N8 be constantly in open state, therefore node C will be
0 state, PMOS transistor P5 will be constantly on, and node DD will be restored to 1 original state.
4, when node E is turned to 0, PMOS transistor P3 and P2 will be turned on.Since the state of node A is not sent out
Changing, or 1 original state, this will be so that NMOS transistor N2 be constantly in open state, therefore node H will be 0
State, PMOS transistor P1 will be constantly on, and node E will be restored to 1 original state.
5, when node G is turned to 0, NMOS transistor N5, N8 will be closed.Remaining node will keep respective
State is constant, and therefore, PMOS transistor P4 and NMOS transistor N4 will be opened always, and G node will be pulled back to original 1,
Then, NMOS transistor N5, N8 will be opened.
6, when node H is turned to 1, PMOS transistor P1 and P4 will be closed, and NMOS transistor N3 will be beaten
It opens.Remaining node will keep respective state constant, and therefore, NMOS transistor N2 will always be in open state, this will drop-down
Recovery nodes H is to original correct 0 state.
7, when node A and C are flipped, NMOS transistor N11, N2 and PMOS transistor P5 and P8 will be closed
It closes, NMOS transistor N9 will be opened.But since the state of node G does not change, NMOS transistor N8 is by one
Straight in the open state, node C will retract 0 original state, then, PMOS transistor P5 under NMOS transistor N8 switched on
It will be opened with P8, NMOS transistor N9 will be closed, and node A will be extensive by the PMOS transistor P8 and NMOS tube N10 of conducting
It is multiple to arrive 1 original state.
8, when node A and DD are flipped, PMOS transistor P7 and P6 will be turned on, NMOS transistor N10,
N11, N2 will be closed.But since the state of node G does not change, NMOS transistor N8 will always be in opening
State, node C will always be in 0 state, and as a result PMOS transistor P5 will be constantly on, and node DD will be restored to original
1 state, PMOS transistor P7 and P6 will be closed, and NMOS transistor N10 will be turned on, and therefore, node A will pass through conducting
PMOS transistor P8 and NMOS tube N10 is restored to 1 original state.
9, when node C and DD are flipped, PMOS transistor P5 and P8 will be closed, and NMOS transistor N9 will be temporary
When be opened, PMOS transistor P7 and P6 will be opened temporarily, and NMOS transistor N10 will be temporarily closed.But due to node G
State do not change, therefore, NMOS transistor N8 will always be in open state, and node C will be restored to 0 state, because
This, PMOS transistor P5 and P8 will be turned on, and node DD will also be restored to original correct status.
10, when node A and node G is flipped simultaneously, NMOS transistor N11, N2, N5, N8 will be closed.This
It will not influence the state of other nodes, therefore, node A will be extensive by the PMOS transistor P8 and NMOS transistor N10 of conducting
Multiple, node G will be restored by the PMOS transistor P4 and NMOS transistor N4 of conducting.
11, when node A and node E is flipped simultaneously, NMOS transistor N11, N2, N4 will be temporarily closed,
PMOS transistor P2, P3 will be opened briefly near bottom dead center on.Since no change has taken place for the state of G node, NMOS transistor N8 will
Always on, node C will keep 0 original state, and PMOS transistor P8 will be always on.A node will be by leading always
Logical PMOS transistor P8 and NMOS tube N10 is restored to original state.Then, NMOS transistor N11, N2 also will be extensive
Open state is arrived again, and therefore, node H will be always maintained at 0 state, and PMOS transistor P1 is always on opening, so node E
1 original state will be pulled up back.
12, when node A and node H is flipped simultaneously, NMOS transistor N11, N2 and PMOS transistor P1, P4
It will be temporarily closed, NMOS transistor N3 will be opened briefly near bottom dead center on.Since no change has taken place for the state of G node, NMOS is brilliant
Body pipe N8 will be always on, and node C will keep 0 original state, and PMOS transistor P8 will be always on.A node will lead to
Constantly on PMOS transistor P8 and NMOS tube N10 are crossed to be restored to original state.Then, NMOS transistor N11, N2
Also it will be restored to open state, therefore, node H will be restored to 0 original state.
13, when node C and node E is flipped simultaneously, PMOS transistor P5, P8 and NMOS transistor N4 will be by
Temporary close, NMOS transistor N9 and PMOS transistor P2, P3 will be by temporary unlatchings.Since node A and node G do not become
Change, therefore, NMOS transistor N8 and N2 will be always on, and node C will be restored to original state.Node H will be kept
0 state originally, so that PMOS transistor P1 will be in the open state, node E will be pulled up go back to original 1.
14, when node C and node G is flipped simultaneously, PMOS transistor P5, P8 and NMOS transistor N5, N8
It will be temporarily closed, NMOS transistor N9 will be by temporary unlatching.Since the state of node A is unchanged, NMOS transistor N2 will
In the open state, also no change has taken place for the state of node E, H.Therefore, node G passes through the PMOS transistor by conducting
P4 and NMOS transistor N4 restores to 1 original state.Then, NMOS transistor N5, N8 will be switched on again, and node C will lead to
The NMOS transistor N8 for crossing conducting restores to original state 0.
15, when node C and node H is flipped simultaneously, PMOS transistor P5, P8, P1, P4 will be closed temporarily
It closes, NMOS transistor N9, N3 will be by temporary unlatchings.But since all no change has taken place for the state of A and G node,
NMOS transistor N8 and N2 will be constantly on, this restores node C and node H all to original state 0.
16, when node DD and node E is flipped simultaneously, PMOS transistor P7, P6, P3, P3 will be opened temporarily
It opens, NMOS transistor N10 and N4 will be temporarily closed.Since all no change has taken place for the state of node A and node G,
NMOS transistor N8 and N2 will be constantly on, this will make node C and node H is 0 original state, PMOS transistor P5
It will be constantly on state with P1, therefore node DD and node E can be resumed.
17, when node DD and node H is flipped simultaneously, PMOS transistor P7, P6, P1, P4 and NMOS crystal
Pipe N3 will be opened temporarily, and NMOS transistor N10 will be temporarily closed.Due to the state of node A and node G all there is no
Change, therefore, NMOS transistor N8 and N2 will be constantly on, this will make node C be 0 original state, and node H can be extensive
It is multiple to arrive 0 original state.By constantly on PMOS transistor P5, node DD will also be restored to 1 state.
18, when node DD and node G is flipped simultaneously, PMOS transistor P7, P6 will be opened temporarily,
NMOS transistor N5 and N2 will be temporarily closed.Since the state of node A is constantly in 1 original state, NMOS crystal
Pipe N2 will always be in open state, and also all no change has taken place for the state of node E and node H, then PMOS transistor P4 and
NMOS transistor N4 is in open state, therefore node G can be restored to 1.Then, NMOS transistor N8 will be beaten again
It opens, node C will be in 0 original state, therefore PMOS transistor P5 will be in the open state, and node DD will can be restored
To 1 state.
19, when node E and node G is flipped simultaneously, PMOS transistor P3 and P2 will be turned on, and NMOS is brilliant
Body pipe N4, N5, N8 will be closed.But since the state of node A does not change, NMOS transistor N2 will locate always
In open state, node H will always be in 0 state, and as a result PMOS transistor P1 will be constantly on, and node E will be restored to
1 state originally, PMOS transistor P3 and P2 will be closed, and NMOS transistor N4 will be turned on, and therefore, node G will be by leading
Logical PMOS transistor P4 and NMOS tube N4 is restored to 1 original state.
20, when node E and H are flipped, PMOS transistor P1 and P4 will be closed, and NMOS transistor N3 will be temporary
When be opened, PMOS transistor P3 and P2 will be opened temporarily, and NMOS transistor N4 will be temporarily closed.But due to node A
State do not change, therefore, NMOS transistor N2 will always be in open state, and node H will be restored to 0 state, because
This, PMOS transistor P1 and P4 will be turned on, and node E will also be restored to original correct status.
21, when node G and H are flipped, NMOS transistor N8, N5 and PMOS transistor P1 and P4 will be closed
It closes, NMOS transistor N3 will be opened.But since the state of node A does not change, NMOS transistor N2 is by one
Straight in the open state, node H will retract 0 original state, then, PMOS transistor P1 under NMOS transistor N2 switched on
It will be opened with P4, NMOS transistor N3 will be closed, and node G will be extensive by the PMOS transistor P4 and NMOS tube N4 of conducting
It is multiple to arrive 1 original state.
To sum up, when one or two of 6 sensitive nodes are flipped, pass through above-mentioned analysis, it is found that total
There are two or more than two nodes no change has taken place, by its save value, these overturning states can restore.
Inventive concept of the invention is to be reinforced according to the physical characteristic that radiating particle bombarding semiconductor device generates
Sensitive nodes inside latch are reduced to 6 by design, therefore, the present invention, and sensitive area reduces, and cause to be bombarded by radiating particle
Probability also reduce, compared to existing Flouride-resistani acid phesphatase D-latch, area, power consumption, delay will be can be greatly reduced.
The invention has the beneficial effects that
(1) present invention shares 32 transistors and constitutes, and device used is few, and small in size, structure is simple, due to device used
It is few, to reduce the power consumption of entire latch and possess lower hardware spending.
(2) in the present invention, data input pin D only passes through a transmission gate and (that is: can latch for transmission to output port
Device on state, data input pin D only can be transmitted directly by the transmission gate being made of transistor P12 and transistor N20
To latch outputs Q), therefore, data transmission period is short, and delay will also be reduced.
(3) traditional D-latch is typically necessary the ability for the anti-overturning that can be only achieved in conjunction with laying out pattern, and this hair
It is bright not need cooperation diagram optimizing, because can restore after its internal any single node or binode are flipped, because
This, the ability of anti-single node and binode upset is improved, and the D of low redundancy nuclear hardening of the present invention is latched
Device can be realized to the fault-tolerant of any single node and binode upset, to realize the fault-tolerant of anti-single node and binode upset
Protection.
The D-latch for the low redundancy nuclear hardening that the present invention constructs, high reliablity can be high radiation environment (such as space flight
Aviation and ground nuclear power station etc.) in IC chip application provide protection.
Detailed description of the invention
Fig. 1 is the schematic illustration of the D-latch of low redundancy nuclear hardening of the present invention；
Fig. 2 is the analogous diagram of the D-latch of low redundancy nuclear hardening of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without making creative work it is obtained it is all its
Its embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
Illustrate present embodiment referring to Fig. 1, the D-latch of low redundancy nuclear hardening described in present embodiment, including
NMOS transistor N1 to N20 and PMOS transistor P1 to P12；
After the drain electrode of the source electrode, transistor N20 of transistor P12 is connected with the drain electrode of transistor N16 to N17, as latch
One data input pin D of device；
Another data input pin after the drain electrode of transistor N18 is connected with the drain electrode of transistor N19, as latch
DN；Two data input pin received signals of latch are opposite；
A clock signal clk N after the grid of transistor P12 is connected with the grid of transistor N15, as latch
Input terminal；
After the grid of transistor N16 to N20 is connected with the grid of transistor P11, another clock as latch is believed
The input terminal of number CLK；Two clock signal input terminal received signals of latch are opposite；
The drain electrode of transistor P12, the drain electrode of the source electrode of transistor N20, transistor P11 are connected with the drain electrode of transistor N15
Afterwards, as the output end Q of latch；
The source electrode of transistor N16, the grid of transistor N2, the source electrode of transistor N10, the drain electrode of transistor N12 and crystal
After the grid connection of pipe N11, as node A；
The source electrode of transistor N18, the grid of transistor N1, the source electrode of transistor N9, the drain electrode of transistor N11, transistor
After the grid of N12, the grid of transistor P10 are connected with the grid of transistor N14, as node B；
The grid of transistor P5, the grid of transistor N9, the grid of transistor P8, the drain electrode of transistor P6 and transistor N8
Drain electrode connection after, as node C；
The drain electrode of transistor P5, the drain electrode of transistor N7, the grid of transistor P7, transistor N10 grid and transistor
After the grid connection of P6, as node DD；
The drain electrode of transistor P1, the drain electrode of transistor N1, the grid of transistor P3, transistor N4 grid and transistor P2
Grid connection after, as node E；
The source electrode of transistor N19, the source electrode of transistor N3, the drain electrode of transistor N5, the grid of transistor N6, transistor N7
Grid, transistor P9 grid connected with the grid of transistor N13 after, as node F；
The source electrode of transistor N17, the source electrode of transistor N4, the drain electrode of transistor N6, transistor N5 grid and transistor
After the grid connection of N8, as node G；
The grid of transistor P1, the grid of transistor N3, the grid of transistor P4, the drain electrode of transistor P2 and transistor N2
Drain electrode connection after, as node H；
The source electrode of transistor P1 to P9 is connect with power supply, and the source electrode of transistor N1 to N2, transistor N5 are to N6's
The source electrode of source electrode, the source electrode of transistor N7 to N8 and transistor N11 to N13 is connect with power ground；
The drain electrode of transistor P3 is connect with the drain electrode of transistor N3, and the drain electrode of transistor P4 and the drain electrode of transistor N4 connect
It connects, the drain electrode of transistor P7 is connect with the drain electrode of transistor N9, and the drain electrode of transistor P8 is connect with the drain electrode of transistor N10；
The drain electrode of transistor P9 is connect with the source electrode of transistor P10, the drain electrode of transistor P10 and the source electrode of transistor P11
Connection, the source electrode of transistor N15 are connect with the drain electrode of transistor N14, and the drain electrode of the source electrode and transistor N13 of transistor N14 connects
It connects.
The D-latch of low redundancy nuclear hardening described in present embodiment includes two data input pins, two clocks
Signal input part and an output end.
Illustrate that this preferred embodiment, preferred embodiment are referring to Fig. 1, when clock signal clk is high level " 1 ", lock
Storage conducting, it may be assumed that data input pin D only can be transmitted directly by the transmission gate being made of transistor P12 and transistor N20
To latch outputs Q, data transmission period is short；When clock signal clk is low level " 0 ", latches.
Although latch node of the present invention shares 8, respectively A, B, C, DD, E, F, G and H, according to latch
Value, sensitive nodes are reduced to 6:
When latches low level " 0 ", latch sensitive nodes are B, C, DD, E, F and H；
When latches high level " 1 ", latch sensitive nodes are A, C, DD, E, G and H.
Illustrate that this preferred embodiment, preferred embodiment are referring to Fig. 1, the D-latch of low redundancy nuclear hardening includes
Normal operating conditions and fault-tolerant operation state.
(1) normal operating conditions includes following situation:
Situation one: assuming that the data input pin D=1 of latch, then DN=0；
(1) as CLK=1, CLKN=0, at this point, NMOS transistor N2, N4, N5, N8, N10, N11, N16 are beaten to 20
Open, NMOS transistor N1, N3, N6, N7, N9, N12, N13, N14, N15 are turned off, PMOS transistor P1, P4, P5, P8, P9,
P10, P12 are opened, and PMOS transistor P2, P3, P6, P7, P11 are turned off, at this point, A=DD=E=G=Q=1, B=C=F
=H=0；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P12 are closed, PMOS crystal
Pipe P11 is opened, and therefore, the output end Q of latch will connect power supply voltage by the PMOS transistor P9 to P11 of conducting,
Due to latch inner interlocked, output end Q will save always 1 state, and latch enters latch mode；
At this point, any variation of data input pin D will not affect that output end Q；
Situation two: assuming that the data input pin D=0 of latch, then DN=1；
(1) as CLK=1, CLKN=0, at this point, NMOS transistor N1, N3, N6, N7, N9, N12 to N14, N16 extremely
N20 is opened, and NMOS transistor N2, N4, N5, N8, N10, N11, N15 are turned off；PMOS transistor P2, P3, P6, P7, P12 are equal
It opens, PMOS transistor P1, P4, P5, P8, P9 to P11 are turned off, at this point, A=DD=E=G=Q=0, B=C=F=H=
1；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P12 are closed, NMOS crystal
Pipe N15 is opened, and therefore, the output end Q of latch will power on ground by the NMOS transistor N13 to N15 be connected, due to
The reason of latch inner interlocked, output end Q will save always 0 state, and latch enters latch mode, at this point, data input
Any variation of end D will not affect that output end Q.
(2) fault-tolerant operation state occurs during latches, and fault-tolerant operation state includes following situation:
Situation one:
When latches low level " 0 ", sensitive nodes B, C, DD, E, F and H；It is any in above-mentioned sensitive nodes
When one or two sensitive nodes is flipped, due to being constantly present two in the sensitive nodes and node A, G that are not flipped
A or more than two node states remain unchanged, and therefore, can restore above-mentioned one or two node being flipped to respective
State originally；
Situation two:
When latches high level " 1 ", sensitive nodes A, C, DD, E, G and H are any in above-mentioned sensitive nodes
When one or two sensitive nodes is flipped, due to being constantly present two in the sensitive nodes and node B, F that are not flipped
A or more than two node states remain unchanged, and therefore, can restore above-mentioned one or two node being flipped to respective
State originally.
Verification test: referring specifically to Fig. 2, the imitative of the D-latch of low redundancy nuclear hardening of the present invention is shown in Fig. 2
True figure, passes through the analogous diagram, it can be seen that the timing function of the D-latch for the novel low redundancy nuclear hardening that the present invention constructs and
Fault tolerance is correct.For example, node A, C, DD, E, G and H have occurred respectively in the CLK time between 30ns~55ns
Primary change has occurred in once inside out, the i.e. state of these nodes, but can finally return to respective correct state；?
The CLK time, a binode upset had occurred in node A-C, A-DD, A-E, A-G, A-H respectively between 150ns~170ns,
But it can finally return to respective correct state.
Although describing the present invention herein with reference to specific embodiment, it should be understood that, these realities
Apply the example that example is only principles and applications.It should therefore be understood that can be carried out to exemplary embodiment
Many modifications, and can be designed that other arrangements, without departing from spirit of the invention as defined in the appended claims
And range.It should be understood that different appurtenances can be combined by being different from mode described in original claim
Benefit requires and feature described herein.It will also be appreciated that the feature in conjunction with described in separate embodiments can be used
Other embodiments.
Claims (6)
1. the D-latch of low redundancy nuclear hardening, which is characterized in that including NMOS transistor N1 to N20 and PMOS transistor P1
To P12；
After the drain electrode of the source electrode, transistor N20 of transistor P12 is connected with the drain electrode of transistor N16 to N17, as latch
One data input pin D；
Another data input pin DN after the drain electrode of transistor N18 is connected with the drain electrode of transistor N19, as latch；Lock
Two data input pin received signals of storage are opposite；
After the grid of transistor P12 is connected with the grid of transistor N15, the input of a clock signal clk N as latch
End；
Another clock signal clk after the grid of transistor N16 to N20 is connected with the grid of transistor P11, as latch
Input terminal；Two clock signal input terminal received signals of latch are opposite；
After the drain electrode of transistor P12, the drain electrode of the source electrode of transistor N20, transistor P11 are connected with the drain electrode of transistor N15, make
For the output end Q of latch；
The source electrode of transistor N16, the grid of transistor N2, the source electrode of transistor N10, the drain electrode of transistor N12 and transistor N11
Grid connection after, as node A；
The source electrode of transistor N18, the grid of transistor N1, the source electrode of transistor N9, the drain electrode of transistor N11, transistor N12
Grid, transistor P10 grid connected with the grid of transistor N14 after, as node B；
The grid of transistor P5, the grid of transistor N9, the grid of transistor P8, the drain electrode of transistor P6 and transistor N8 leakage
After the connection of pole, as node C；
The drain electrode of transistor P5, the drain electrode of transistor N7, the grid of transistor P7, the grid of transistor N10 and transistor P6
After grid connection, as node DD；
The drain electrode of transistor P1, the drain electrode of transistor N1, the grid of transistor P3, the grid of transistor N4 and transistor P2 grid
After the connection of pole, as node E；
The source electrode of transistor N19, the source electrode of transistor N3, the drain electrode of transistor N5, the grid of transistor N6, transistor N7 grid
Pole, transistor P9 grid connected with the grid of transistor N13 after, as node F；
The source electrode of transistor N17, the source electrode of transistor N4, the drain electrode of transistor N6, the grid of transistor N5 and transistor N8
After grid connection, as node G；
The grid of transistor P1, the grid of transistor N3, the grid of transistor P4, the drain electrode of transistor P2 and transistor N2 leakage
After the connection of pole, as node H；
The source electrode of transistor P1 to P9 is connect with power supply, the source electrode of transistor N1 to N2, transistor N5 to N6 source electrode,
The source electrode of transistor N7 to N8 and the source electrode of transistor N11 to N13 are connect with power ground；
The drain electrode of transistor P3 is connect with the drain electrode of transistor N3, and the drain electrode of transistor P4 is connect with the drain electrode of transistor N4, brilliant
The drain electrode of body pipe P7 is connect with the drain electrode of transistor N9, and the drain electrode of transistor P8 is connect with the drain electrode of transistor N10；
The drain electrode of transistor P9 is connect with the source electrode of transistor P10, and the drain electrode of transistor P10 is connect with the source electrode of transistor P11,
The source electrode of transistor N15 is connect with the drain electrode of transistor N14, and the source electrode of transistor N14 is connect with the drain electrode of transistor N13.
2. the D-latch of low redundancy nuclear hardening according to claim 1, which is characterized in that clock signal clk is high electricity
When flat " 1 ", latch conducting；When clock signal clk is low level " 0 ", latches.
3. the D-latch of low redundancy nuclear hardening according to claim 1 or 2, which is characterized in that
When latches low level " 0 ", latch sensitive nodes are B, C, DD, E, F and H；
When latches high level " 1 ", latch sensitive nodes are A, C, DD, E, G and H.
4. the D-latch of low redundancy nuclear hardening according to claim 1, which is characterized in that including normal operating conditions
With fault-tolerant operation state.
5. the D-latch of low redundancy nuclear hardening according to claim 4, which is characterized in that normal operating conditions includes
Following situation:
Situation one: assuming that the data input pin D=1 of latch, then DN=0；
(1) as CLK=1, CLKN=0, at this point, NMOS transistor N2, N4, N5, N8, N10, N11, N16 are opened to 20,
NMOS transistor N1, N3, N6, N7, N9, N12, N13, N14, N15 are turned off, PMOS transistor P1, P4, P5, P8, P9, P10,
P12 is opened, and PMOS transistor P2, P3, P6, P7, P11 are turned off, at this point, A=DD=E=G=Q=1, B=C=F=H=
0；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P12 are closed, PMOS transistor P11
It opens, therefore, the output end Q of latch will connect power supply voltage by the PMOS transistor P9 to P11 of conducting, due to lock
The reason of storage inner interlocked, output end Q will save always 1 state, and latch enters latch mode；
Situation two: assuming that the data input pin D=0 of latch, then DN=1；
(1) as CLK=1, CLKN=0, at this point, NMOS transistor N1, N3, N6, N7, N9, N12 are beaten to N14, N16 to N20
It opens, NMOS transistor N2, N4, N5, N8, N10, N11, N15 are turned off；PMOS transistor P2, P3, P6, P7, P12 are opened,
PMOS transistor P1, P4, P5, P8, P9 are turned off to P11, at this point, A=DD=E=G=Q=0, B=C=F=H=1；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P12 are closed, NMOS transistor N15
It opens, therefore, the output end Q of latch will power on ground by the NMOS transistor N13 to N15 be connected, due to latch
The reason of inner interlocked, output end Q will save always 0 state, and latch enters latch mode.
6. the D-latch of low redundancy nuclear hardening according to claim 4, which is characterized in that fault-tolerant operation state occurs
During latches, fault-tolerant operation state includes following situation:
Situation one:
When latches low level " 0 ", sensitive nodes B, C, DD, E, F and H；Any one in above-mentioned sensitive nodes
Or two sensitive nodes are when being flipped, due to be constantly present in the sensitive nodes and node A, G that are not flipped two or
More than two node states remain unchanged, and therefore, can restore above-mentioned one or two node being flipped to respectively original
State；
Situation two:
When latches high level " 1 ", sensitive nodes A, C, DD, E, G and H, any one in above-mentioned sensitive nodes
Or two sensitive nodes are when being flipped, due to be constantly present in the sensitive nodes and node B, F that are not flipped two or
More than two node states remain unchanged, and therefore, can restore above-mentioned one or two node being flipped to respectively original
State.
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Cited By (1)
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| CN111223503B (en) * | 2020-03-11 | 2021-10-01 | 河海大学常州校区 | A dual-node single-event flip-immune memory cell and latch |
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