CN105577161A - A single-event multi-node flip-resistant hardened latch based on dual-mode redundancy - Google Patents

Abstract

The invention disclose a single particle resistance multi-node overturning reinforcement latch register based on dual modular redundancy, relating to the radiation resistance integrated circuit design field. The single particle resistance multi-node overturning reinforcement latch register comprises an input module (1), two storage units (MC1,MC2) having identical structures and a 4-tube Muller C unit (2). The invention can realize full recovery on the single particle single node overturning, can fully tolerate the single particle multi-node overturning and improves the reliability of the system.

Description

A single-event multi-node flip-resistant hardened latch based on dual-mode redundancy

technical field

The invention relates to the field of anti-radiation integrated circuit design, using a dual-mode redundant structure and a MullerC unit circuit to form a reinforced latch design, realizing the self-recovery of single-event flipping, and fully tolerant to double-node flipping, specifically A single-event multi-node flip-resistant hardened latch based on dual-mode redundancy.

Background technique

With the continuous advancement of technology, integrated circuits have been widely used in various fields. At the same time, its application in important fields such as deep space exploration, medical equipment, aerospace, and automotive electronics also puts forward higher requirements for its reliability. Energetic particles (neutrons or alpha particles) in a radiation environment deposit charges on their tracks as they pass through sensitive regions of microelectronic devices, and these charges change the stored value in memory elements such as latches. With the rapid development of semiconductor technology, the feature size of integrated circuits has been continuously reduced and the operating voltage has been continuously reduced, resulting in the continuous reduction of the node capacitance of the circuit, so that the amount of charge (critical charge) required for the logic state of the circuit node to flip The probability of causing single event upset (SingleEventUpset, SEU) also increases sharply. With the further reduction of the size of the integrated circuit process, the distance between the circuit nodes is further reduced, and the charge generated by the bombardment of high-energy particles can diffuse and affect adjacent nodes, thereby triggering single event multiple node upset (SEMNU). Therefore, new designs of latches that can tolerate single event multiple node upsets are needed.

Contents of the invention

In order to overcome the shortcomings of existing hardened latches, the present invention provides a dual-mode redundancy-based anti-single-event multi-node upset hardened latch, which can achieve complete self-recovery for SEU effects, and for The SEMNU effect can be fully tolerated, which improves the stability of the system.

The technical scheme adopted in the present invention is:

A dual-mode redundancy-based anti-single-event multi-node flipping hardened latch is characterized in that it includes an input module (1), two storage units MC1 and MC2, and a 4-tube MullerC unit (2); the The input module (1) is composed of 4 PMOS transistors and 1 inverter; the two storage units MC1 and MC2 have the same structure, and each storage unit is composed of 6 PMOS transistors and 4 NMOS transistors; the MullerC unit (2) Consists of two PMOS transistors and two NMOS transistors; the output terminal of the input module (1) is connected to the storage units MC1 and MC2, and the storage units MC1 and MC2 are respectively connected to the two input terminals of the MullerC unit (2).

The anti-single-event multi-node flipping hardened latch based on dual-mode redundancy is characterized in that: the four PMOS transistors of the input module are respectively transistor P7, transistor P8, transistor P7b, and transistor P8b. The input terminal of the phaser is connected to the input signal D signal; the output terminal of the inverter is connected to the sources of the transistor P7b and the transistor P8b; the sources of the transistor P7 and the transistor P8 are connected to the input signal D signal; the transistor P7, the transistor P8, The gates of the transistor P7b and the transistor P8b are connected to the clock signal CLKB; the substrates of the transistor P7, the transistor P8, the transistor P7b and the transistor P8b are connected to the power supply VDD.

The dual-mode redundancy-based anti-single-event multi-node flipping hardened latch is characterized in that: the six PMOS transistors and four NMOS transistors forming the storage unit MC1 are respectively transistor P1 and transistor P2 , transistor P3, transistor P4, transistor P5, transistor P6, transistor N1, transistor N2, transistor N3, transistor N4; the 6 PMOS transistors and 4 NMOS transistors that constitute the storage unit MC2 are respectively transistor P1b, transistor P2b, Source of transistor P3b, transistor P4b, transistor P5b, transistor P6b, transistor N1b, transistor N2b, transistor N3b, transistor N4b; transistor P1, transistor P3, transistor P5, transistor P6, transistor P1b, transistor P3b, transistor P5b, transistor P6b Access power supply VDD; Transistor N2, transistor N4, transistor N2b, transistor N4b source ground GND; transistor P1, transistor P2, transistor P3, transistor P4, transistor P5, transistor P6, transistor P1b, transistor P2b, transistor P3b, transistor The substrates of P4b, transistor P5b, and transistor P6b are connected to the power supply VDD; the substrates of transistors N1, transistor N2, transistor N3, transistor N4, transistor N1b, transistor N2b, transistor N3b, and transistor N4b are grounded to GND;

The drain of transistor P1 is connected to the source of transistor P2, the drain of transistor P2 is connected to the drain of transistor N1, the source of transistor N1 is connected to the drain of transistor N2; the drain of transistor P3 is connected to the source of transistor P4 Connection, the drain of the transistor P4 is connected to the drain of the transistor N3, the source of the transistor N3 is connected to the drain of the transistor N4; the drain of the transistor P1 is simultaneously connected to the gate of the transistor P3, the gate of the transistor P5, the gate of the transistor N3 The gate and the drain of the transistor P7b are connected, and the connection point is called node S3; the drain of the transistor P3 is simultaneously connected with the gate of the transistor P1, the gate of the transistor P6, the gate of the transistor N1, and the drain of the transistor P7 , the connection point is called node S4; the gate of transistor P2 is connected with the gate of transistor N4, the drain of transistor N2, and the drain of transistor P6 at the same time, and this connection point is called node S1; the gate of transistor P4 At the same time, it is connected to the gate of transistor N2, the drain of transistor N4, and the drain of transistor P5, and this connection point is called node S2;

The drain of transistor P1b is connected to the source of transistor P2b, the drain of transistor P2b is connected to the drain of transistor N1b, the source of transistor N1b is connected to the drain of transistor N2b; the drain of transistor P3b is connected to the source of transistor P4b Connect, the drain of transistor P4b is connected with the drain of transistor N3b, the source of transistor N3b is connected with the drain of transistor N4b; The drain of transistor P1b is connected with the gate of transistor P3b, the gate of transistor P5b, the gate of transistor N3b The gate and the drain of the transistor P8b are connected, and the connection point is called node S3b; the drain of the transistor P3b is simultaneously connected with the gate of the transistor P1b, the gate of the transistor P6b, the gate of the transistor N1b, and the drain of the transistor P8 , the connection point is called node S4b; the gate of transistor P2b is connected with the gate of transistor N4b, the drain of transistor N2b, and the drain of transistor P6b at the same time, and this connection point is called node S1b; the gate of transistor P4b At the same time, it is connected to the gate of transistor N2b, the drain of transistor N4b, and the drain of transistor P5b, and this connection point is called node S2b;

The described anti-single-event multi-node flipping hardened latch based on dual-mode redundancy is characterized in that: the MullerC unit is composed of two PMOS transistors and two NMOS transistors; the two PMOS transistors are respectively transistor P9 and transistor P10; the two NMOS transistors are transistor N5 and transistor N6 respectively; wherein, the gate of transistor P9 is connected to the gate of transistor N5, and the node between the gate of transistor P9 and the gate of transistor N5 is a C unit circuit The first signal input terminal IN1 of the transistor P9; the drain of the transistor P9 is connected to the source of the transistor P10; the gate of the transistor P10 is connected to the gate of the transistor N6, and the node between the gate of the transistor P10 and the gate of the transistor N6 It is the second signal input terminal IN2 of the C unit circuit; the drain of the transistor P10 is connected to the drain of the transistor N5, and the node between the drain of the transistor P10 and the drain of the transistor N5 is the signal output terminal of the C unit circuit; The substrate of transistor N5 is grounded; the source of transistor N5 is connected to the drain of transistor N6, and the source of transistor N6 and the substrate of transistor N6 are all grounded; The source of transistor P9, the substrate of transistor P9 and the substrate of transistor P10 The substrates are respectively connected to the power supply VDD.

The node S3 and the node S3b are respectively connected to two input terminals of the MullerC unit, and the output terminal of the MullerC unit is used as the output terminal Q of the latch.

The advantages of the present invention are:

The invention can realize complete self-recovery for single-event and single-node reversal, and can fully tolerate single-event multi-node reversal, thereby improving the reliability of the system.

Description of drawings

FIG. 1 is a block diagram of a hardened latch according to the present invention.

Fig. 2 is a block diagram of the hardened latch input module of the present invention.

FIG. 3 is a transistor structure diagram of memory cell MC1.

Figure 4 Transistor structure diagram of MullerC unit.

FIG. 5 is a structure diagram of the reinforced latch transistor of the present invention.

detailed description

In order to better illustrate the working principle and fault-tolerant mode of the latch, further description will be given below in conjunction with the accompanying drawings.

As shown in FIG. 1 , a dual-mode redundancy-based anti-single-event multi-node flip hardened latch includes an input module 1 , two storage units MC1 and MC2 , and a 4-transistor MullerC unit 2 .

As shown in Figure 2, the input module is composed of 4 PMOS transistors and 1 inverter; the structures of the 2 memory cells MC1 and MC2 are the same, and each memory cell is composed of 6 PMOS transistors and 4 NMOS transistors. The transistor structure of MC1 is shown in Figure 3; the MullerC unit is composed of two PMOS transistors and two NMOS transistors, and its transistor structure and truth table are shown in Figure 4 and Table 1, respectively.

Table I

The first input IN1 of the Muller C unit The second input IN2 of the Muller C unit Signal output OUT of the Muller C unit 0 0 1 1 1 0 0 1 constant 1 0 constant

The 4 PMOS transistors of the input module are respectively transistor P7, transistor P8, transistor P7b, and transistor P8b; the input terminal of the inverter is connected to the input signal D signal; the output terminal of the inverter is connected to the source of the transistor P7b and the transistor P8b The source of transistor P7 and transistor P8 is connected to the input signal D signal; the gate of transistor P7, transistor P8, transistor P7b, and transistor P8b is connected to the clock signal CLKB; transistor P7, transistor P8, transistor P7b, and transistor P8b The substrate access power supply VDD.

The 6 PMOS transistors and 4 NMOS transistors constituting the storage unit MC1 are respectively transistor P1, transistor P2, transistor P3, transistor P4, transistor P5, transistor P6, transistor N1, transistor N2, transistor N3, and transistor N4; The 6 PMOS transistors and 4 NMOS transistors constituting the memory cell MC2 are respectively transistor P1b, transistor P2b, transistor P3b, transistor P4b, transistor P5b, transistor P6b, transistor N1b, transistor N2b, transistor N3b, and transistor N4b.

The source of transistor P1, transistor P3, transistor P5, transistor P6, transistor P1b, transistor P3b, transistor P5b, and transistor P6b is connected to the power supply VDD; the source of transistor N2, transistor N4, transistor N2b, and transistor N4b is grounded to GND; transistor P1 , transistor P2, transistor P3, transistor P4, transistor P5, transistor P6, transistor P1b, transistor P2b, transistor P3b, transistor P4b, transistor P5b, transistor P6b substrate access power supply VDD; transistor N1, transistor N2, transistor N3, The substrates of the transistor N4, the transistor N1b, the transistor N2b, the transistor N3b, and the transistor N4b are grounded GND;

The drain of transistor P1 is connected to the source of transistor P2, the drain of transistor P2 is connected to the drain of transistor N1, the source of transistor N1 is connected to the drain of transistor N2; the drain of transistor P3 is connected to the source of transistor P4 Connection, the drain of the transistor P4 is connected to the drain of the transistor N3, the source of the transistor N3 is connected to the drain of the transistor N4; the drain of the transistor P1 is simultaneously connected to the gate of the transistor P3, the gate of the transistor P5, the gate of the transistor N3 The gate and the drain of transistor P7b are connected, we call this connection point node S3; the drain of transistor P3 is simultaneously connected with the gate of transistor P1, the gate of transistor P6, the gate of transistor N1, and the drain of transistor P7 connection, we call this connection point node S4; the gate of transistor P2 is connected to the gate of transistor N4, the drain of transistor N2, and the drain of transistor P6 at the same time, and we call this connection point node S1; transistor P4 The gate of is connected to the gate of transistor N2, the drain of transistor N4, and the drain of transistor P5 at the same time, and we call this connection point node S2.

The drain of transistor P1b is connected to the source of transistor P2b, the drain of transistor P2b is connected to the drain of transistor N1b, the source of transistor N1b is connected to the drain of transistor N2b; the drain of transistor P3b is connected to the source of transistor P4b Connect, the drain of transistor P4b is connected with the drain of transistor N3b, the source of transistor N3b is connected with the drain of transistor N4b; The drain of transistor P1b is connected with the gate of transistor P3b, the gate of transistor P5b, the gate of transistor N3b The gate and the drain of transistor P8b are connected, we call this connection point node S3b; the drain of transistor P3b is simultaneously connected with the gate of transistor P1b, the gate of transistor P6b, the gate of transistor N1b, and the drain of transistor P8 connection, we call this connection point node S4b; the gate of transistor P2b is connected with the gate of transistor N4b, the drain of transistor N2b, and the drain of transistor P6b at the same time, we call this connection point node S1b; transistor P4b The gate of is connected to the gate of the transistor N2b, the drain of the transistor N4b, and the drain of the transistor P5b at the same time, and we call this connection point a node S2b.

Described MullerC unit is made up of two PMOS transistors and two NMOS transistors; Two PMOS transistors are respectively transistor P9 and transistor P10; Two NMOS transistors are respectively transistor N5 and transistor N6; Wherein, the gate of transistor P9 and transistor N5 The gate of the transistor P9 is connected with the gate of the transistor N5, and the node between the gate of the transistor P9 and the gate of the transistor N5 is the first signal input terminal IN1 of the C unit circuit; the drain of the transistor P9 is connected with the source of the transistor P10; the gate of the transistor P10 Pole is connected with the gate of transistor N6, and the node between the gate of transistor P10 and the gate of transistor N6 is the second signal input end IN2 of C unit circuit; The drain of transistor P10 is connected with the drain of transistor N5, The node between the drain of the transistor P10 and the drain of the transistor N5 is the signal output terminal of the C unit circuit; the substrate of the transistor N5 is grounded; the source of the transistor N5 is connected with the drain of the transistor N6, and the source of the transistor N6 And the substrate of the transistor N6 is grounded; the source of the transistor P9, the substrate of the transistor P9 and the substrate of the transistor P10 are respectively connected to the power supply VDD.

The node S3 and the node S3b are respectively connected to two input terminals of the MullerC unit, and the output terminal of the MullerC unit is used as the output terminal Q of the latch.

The transistor structure of a single-event multi-node reversal hardened latch transistor based on dual-mode redundancy in the present invention is shown in FIG. 5 .

working principle:

When the clock signal CLK=1, CLKB=0, the transistor P7, transistor P8, transistor P7b, and transistor P8b of the input module are in the open state, and the D signal can be transmitted to the nodes S3, S4, S3b, and S4b through the input module. We will This period is called the transparent period.

When the latch is in the transparent period, taking the D signal as an example at this time, the node S3 and the node S3b are at the low level, and the nodes S4 and S4b are at the high level.

In the memory cell MC1, S4 is at a high level, making transistor P1 and transistor P6 in an off state, and making transistor N1 in an on state; S3 is at a low level, making transistor P3 and transistor P5 in an on state, making transistor N3 in an off state state. Transistor P5 is in an open state, so that the node S2 is pulled up to a high level, so that the transistor P4 is turned off, and the transistor N2 is turned on; when the transistor N2 is in an open state, and the transistor P1 is turned off, the node S1 is pulled down to a low level , so that transistor P2 is turned on and transistor N4 is turned off.

Transistor and node states in MC2 can be obtained in the same way.

At this time, the transistors P2, P3, P5, P2b, P3b, P5b, N1, N2, N1b, N2b are on, and the transistors P1, P4, P6, P1b, P4b, P6b, N3, N4, N3b, N4b are off. Storage node S3=0, S4=1, S1=0, S2=1 state, storage node S3b=0, S4b=1, S1b=0, S2b=1 state.

Nodes S3 and S3b are at low level, connected to the two input ends of the MullerC unit, and output Q is at high level.

When the clock signal CLK=0 and CLKB=1, the four transistors P7, P8, P7b, and P8b of the input module are in the off state, and the input D signal is shielded. We call this period the latch period. At this time, all nodes are still in a stable state, and the data is successfully locked in the storage unit.

Anti-radiation performance analysis:

Based on the SEU generation mechanism, when a high-energy particle bombards the drain of a PMOS transistor, only a positive transient pulse can be generated; when it bombards the drain of an NMOS transistor, only a negative transient pulse can be generated.

Since the nodes S3, S4, S3b, and S4b are only connected to the PMOS transistors, when these nodes are in the "1" state, they will not be bombarded and flipped to the "0" state.

Since the structures of memory cells MC1 and MC2 are exactly the same, and the memory cells themselves have a symmetrical structure, we take the state of storage nodes S3=0, S4=1, S1=0, and S2=1 as an example for fault-tolerant analysis.

When the node S3 is flipped from the "0" state to the "1" state, the transistors P3 and P5 will be turned off, and the transistor N3 will be turned on. Due to the capacitive effect, the nodes S4 and S2 are still in the "1" state. Therefore, the transistor P1 is in the off state, the transistors P2, N1, and N2 are in the on state, and the node S3 is pulled down from the "1" state to the initial "0" state.

When node S1 is turned from "0" state to "1" state, transistor P2 is immediately turned off, node S3 is still in "0" state, so that transistor P5 is still in open state, and transistor N2 is also in open state, so that The node S1 is pulled down from the "1" state to the initial "0" state.

When node S2 is flipped from "1" state to "0" state, transistor P4 is turned on and transistor N2 is turned off, but since node S3 is still in "0" state, transistor N3 remains off, and transistor P5 is always Keep the open state, so that the node S2 is pulled up from the "0" state to the initial "1" state.

From the above analysis, it can be seen that the memory cell can realize complete self-recovery for single event upset SEU.

When SEU occurs at the output Q, the nodes S3 and S3b will restore the output Q to the correct value through the MullerC unit.

The reinforced latch designed in the present invention mainly performs radiation resistance reinforcement for two sensitive nodes.

Figure 4 and Table 1 show the transistor structure and truth table of the MullerC unit respectively. It can be seen from Figure 5 that when the two inputs of the MullerC unit are different, the C unit will keep the original state unchanged.

When the two flipped nodes are located in one storage unit, because the other storage unit has latched the correct value, according to the characteristics of the MullerC unit, the output Q still maintains the original correct value.

When the two flipped nodes are located in different storage units, the output Q still maintains the correct value because the storage unit can achieve complete self-recovery for single event flipping.

From the above analysis, it can be seen that when a single sensitive node is flipped, the latch can always realize self-recovery to avoid latching wrong data; The device can also output the correct value. Therefore, the reinforced latch proposed by the present invention can not only fully self-recover for single-event single-node flipping, but also fully tolerate single-event multi-node flipping, thereby improving the reliability of the system.

Claims (4)

1. A dual-mode redundancy-based anti-single-event multi-node flip hardened latch, characterized in that: it includes an input module (1), two storage units MC1, MC2, and a 4-tube MullerC unit (2); The input module (1) is composed of 4 PMOS transistors and 1 inverter; the structures of the 2 memory cells MC1 and MC2 are the same, and each memory cell is composed of 6 PMOS transistors and 4 NMOS transistors; The MullerC unit (2) is composed of two PMOS transistors and two NMOS transistors; the output of the input module (1) is connected to the storage units MC1 and MC2, and the storage units MC1 and MC2 are respectively connected to the two input terminals of the MullerC unit (2) connect. 2. A dual-mode redundancy-based anti-single-event multi-node flipping hardened latch according to claim 1, characterized in that: the four PMOS transistors of the input module are respectively transistor P7, transistor P8, transistor P7b, transistor P8b, the input terminal of the inverter is connected to the input signal D signal; the output terminal of the inverter is connected to the source of the transistor P7b and the transistor P8b; the source of the transistor P7 and the transistor P8 is connected to the input signal D signal; The gates of the transistor P7, the transistor P8, the transistor P7b, and the transistor P8b are connected to the clock signal CLKB; the substrates of the transistor P7, the transistor P8, the transistor P7b, and the transistor P8b are connected to the power supply VDD. 3. A dual-mode redundancy-based anti-single-event multi-node flip hardened latch according to claim 1 or 2, characterized in that: the 6 PMOS transistors and 4 NMOS transistors that constitute the storage unit MC1 , are respectively transistor P1, transistor P2, transistor P3, transistor P4, transistor P5, transistor P6, transistor N1, transistor N2, transistor N3, transistor N4; the 6 PMOS transistors and 4 NMOS transistors constituting the storage unit MC2, Transistor P1b, transistor P2b, transistor P3b, transistor P4b, transistor P5b, transistor P6b, transistor N1b, transistor N2b, transistor N3b, transistor N4b; transistor P1, transistor P3, transistor P5, transistor P6, transistor P1b, transistor P3b, The source of transistor P5b and transistor P6b is connected to the power supply VDD; the source of transistor N2, transistor N4, transistor N2b, and transistor N4b is grounded to GND; transistor P1, transistor P2, transistor P3, transistor P4, transistor P5, transistor P6, and transistor P1b The substrates of transistors P2b, transistors P3b, transistors P4b, transistors P5b, and transistors P6b are connected to the power supply VDD; the substrates of transistors N1, transistors N2, transistors N3, transistors N4, transistors N1b, transistors N2b, transistors N3b, and transistors N4b are grounded GND; The drain of transistor P1 is connected to the source of transistor P2, the drain of transistor P2 is connected to the drain of transistor N1, the source of transistor N1 is connected to the drain of transistor N2; the drain of transistor P3 is connected to the source of transistor P4 Connection, the drain of the transistor P4 is connected to the drain of the transistor N3, the source of the transistor N3 is connected to the drain of the transistor N4; the drain of the transistor P1 is simultaneously connected to the gate of the transistor P3, the gate of the transistor P5, the gate of the transistor N3 The gate and the drain of the transistor P7b are connected, and the connection point is called node S3; the drain of the transistor P3 is simultaneously connected with the gate of the transistor P1, the gate of the transistor P6, the gate of the transistor N1, and the drain of the transistor P7 , the connection point is called node S4; the gate of transistor P2 is connected with the gate of transistor N4, the drain of transistor N2, and the drain of transistor P6 at the same time, and this connection point is called node S1; the gate of transistor P4 At the same time, it is connected to the gate of transistor N2, the drain of transistor N4, and the drain of transistor P5, and this connection point is called node S2; The drain of transistor P1b is connected to the source of transistor P2b, the drain of transistor P2b is connected to the drain of transistor N1b, the source of transistor N1b is connected to the drain of transistor N2b; the drain of transistor P3b is connected to the source of transistor P4b Connect, the drain of transistor P4b is connected with the drain of transistor N3b, the source of transistor N3b is connected with the drain of transistor N4b; The drain of transistor P1b is connected with the gate of transistor P3b, the gate of transistor P5b, the gate of transistor N3b The gate and the drain of the transistor P8b are connected, and the connection point is called node S3b; the drain of the transistor P3b is simultaneously connected with the gate of the transistor P1b, the gate of the transistor P6b, the gate of the transistor N1b, and the drain of the transistor P8 , the connection point is called node S4b; the gate of transistor P2b is connected with the gate of transistor N4b, the drain of transistor N2b, and the drain of transistor P6b at the same time, and this connection point is called node S1b; the gate of transistor P4b At the same time, it is connected to the gate of transistor N2b, the drain of transistor N4b, and the drain of transistor P5b, and this connection point is called node S2b; node S3 and node S3b are respectively connected to the two input ends of the MullerC unit and the output end of the MullerC unit As the output Q of this latch. 4. A kind of anti-single-event multi-node flipping hardened latch based on dual-mode redundancy according to claim 3, characterized in that: the MullerC unit is composed of two PMOS transistors and two NMOS transistors; two The PMOS transistors are transistor P9 and transistor P10 respectively; the two NMOS transistors are transistor N5 and transistor N6 respectively; wherein, the gate of transistor P9 is connected to the gate of transistor N5, and the gate of transistor P9 is connected to the gate of transistor N5 The node of the C unit circuit is the first signal input terminal IN1; the drain of the transistor P9 is connected to the source of the transistor P10; the gate of the transistor P10 is connected to the gate of the transistor N6, and the gate of the transistor P10 is connected to the gate of the transistor N6 The node between the gates is the second signal input terminal IN2 of the C unit circuit; the drain of the transistor P10 is connected to the drain of the transistor N5, and the node between the drain of the transistor P10 and the drain of the transistor N5 is the C unit The signal output end of the circuit; the substrate of the transistor N5 is grounded; the source of the transistor N5 is connected to the drain of the transistor N6, and the source of the transistor N6 and the substrate of the transistor N6 are both grounded; the source of the transistor P9, the transistor P9 The substrate and the substrate of the transistor P10 are connected to the power supply VDD, respectively.