CN109300894A - Power device protection chip and preparation method thereof - Google Patents
Power device protection chip and preparation method thereof Download PDFInfo
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- CN109300894A CN109300894A CN201811151183.1A CN201811151183A CN109300894A CN 109300894 A CN109300894 A CN 109300894A CN 201811151183 A CN201811151183 A CN 201811151183A CN 109300894 A CN109300894 A CN 109300894A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 24
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- 230000004888 barrier function Effects 0.000 claims abstract description 47
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 82
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 30
- 238000002347 injection Methods 0.000 claims description 27
- 239000007924 injection Substances 0.000 claims description 27
- 239000000377 silicon dioxide Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
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- 238000007254 oxidation reaction Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract 2
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 30
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 8
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- 238000001657 homoepitaxy Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 3
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- 238000001039 wet etching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
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- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
本发明提供功率器件保护芯片，其包括衬底；形成在衬底上的第一外延层；间隔形成在第一外延层内的整流区，整流区包括自第一外延层的上表面向第一外延层内形成的第一沟槽、自第一沟槽的底部向第一外延层内形成的第二沟槽及自第二沟槽的底部向第一外延层内形成的第三沟槽，所述第一沟槽、所述第二沟槽及第三沟槽连通且宽度依次减小，第一沟槽、第二沟槽及第三沟槽内的金属层与第一外延层之间的肖特基势垒高度依次减小；位于两个整流区之间自第一外延层的上表面延伸至衬底的隔离区，隔离区包括第四沟槽、位于第四沟槽的底部的注入区、形成在第四沟槽内的第二外延层。本发明还提供功率器件保护芯片的制备方法，增强可靠性，缩小封装面积和降低成本。
The invention provides a power device protection chip, which includes a substrate; a first epitaxial layer formed on the substrate; a first trench formed in the epitaxial layer, a second trench formed from the bottom of the first trench into the first epitaxial layer, and a third trench formed from the bottom of the second trench into the first epitaxial layer, The first trenches, the second trenches and the third trenches are communicated with each other and the widths decrease in turn, and the metal layers in the first trenches, the second trenches and the third trenches and the first epitaxial layer are between The height of the Schottky barrier decreases in turn; the isolation region located between the two rectifying regions extends from the upper surface of the first epitaxial layer to the substrate, and the isolation region includes a fourth trench, a an implanted region, and a second epitaxial layer formed in the fourth trench. The invention also provides a preparation method of a power device protection chip, which enhances reliability, reduces packaging area and reduces cost.
Description
Technical field
The present invention relates to semiconductor chip fabrication process technical fields, more particularly to power device protection chip and its preparation
Method.
Background technique
As semiconductor devices increasingly tends to miniaturization, high density and multi-functional, electronic device becomes increasingly susceptible to electricity
The influence of surge is pressed, various voltage surges can induce transient current spikes from static discharge to lightning etc..Static discharge (ESD)
And the transient voltage that some other voltage surge form occurs at random is present in various electronic devices.
Surge protection chip is a kind of for protecting sensitive semiconductor device, keeps it special from transient voltage surge destruction
The solid-state semiconductor device not designed, it is excellent that it has that clamp coefficient is small, small in size, response is fast, leakage current is small and reliability is high etc.
Point, thus be widely used on voltage transient and carrying out surge protection.Based on different applications, surge protection chip is not only
For protecting sensitive circuit from the impact of surge, can also be risen by changing the clamping voltag of surge discharge path and itself
It is acted on to circuit protection.In high-frequency circuit, circuit signal is caused to decline since surge protection chip can also have parasitic capacitance
Subtract stability that is larger, or even influencing entire circuit.
Summary of the invention
In view of this, the present invention provides, a kind of stability is high, reduces the strong power device of package area, Anti-surging ability protects
Chip is protected, to solve above-mentioned technical problem, on the one hand, the present invention is realized using following technical scheme.
A kind of power device protection chip comprising:
The substrate of first conduction type；
Form the epitaxial layer of the first conduction type over the substrate；
It is spaced the commutating zone being formed in first epitaxial layer, the commutating zone includes from the upper of first epitaxial layer
First groove that surface is formed into first epitaxial layer, from the bottom of the first groove into first epitaxial layer shape
At second groove and third groove from the bottom of the second groove to first epitaxial layer that formed from, first ditch
Slot, the second groove and the third groove are connected to and width is sequentially reduced, the first groove, the second groove and institute
The side wall for stating third groove is each formed with the first barrier layer, in the first groove, the second groove and the third groove
It is filled with metal layer, outside the metal layer and described first in the first groove, the second groove and the third groove
The schottky barrier height prolonged between layer is sequentially reduced；
The isolated area of the substrate is extended to from the upper surface of first epitaxial layer between two commutating zones,
The isolated area include the 4th groove, positioned at the bottom of the 4th groove the second conduction type injection region, be formed in institute
It states the second barrier layer of the side wall of the 4th groove and fills up the second epitaxial layer of the second conduction type of the 4th groove.
The present invention provides the having the beneficial effect that by being formed outside first over the substrate of a kind of power device protection chip
Prolong layer, in first epitaxial layer interval form commutating zone, the commutating zone sequentially form the identical first groove of depth,
Second groove and third groove, and sequentially form and be located in the first groove, the second groove and the third groove
First barrier layer of the side wall of the first groove, the second groove and the third groove, respectively the first groove,
Metal layer is filled in the second groove and the third groove, the parasitic capacitance of the commutating zone is reduced, to prevent institute
The flow direction for controlling electric current when power device protection chip conducting is stated, blocks electric current non-uniform situation occur, thus described in improving
The stability of power device protection chip.The metal filled in the first groove, the second groove and the third groove
Layer forms Schottky contacts with the epitaxial layer respectively, reduces parasitic capacitance, reduces the power device protection chip
Conduction loss equally also increases the current branch that the power device is protected in chip and realizes shunting, to improve the power
The Anti-surging ability of device protection chip.The second epitaxial layer and the substrate formed in 4th groove forms PN junction, from
And the pressure-resistant performance of the power device protection chip is improved, first metal area and second metal area are both formed in
The top of the substrate reduces the package area of the power device protection chip, reduces preparation cost.In the rectification
The isolated area for extending to the substrate is formed between area, makes the current blocking of the commutating zone, is improved the power device and is protected
Protect the reliability of chip.
On the other hand, the present invention also provides a kind of preparation methods of power device protection chip comprising following technique step
It is rapid:
S501: the substrate of first conduction type is provided, is formed outside the first of the first conduction type over the substrate
Prolong layer；
S502: first groove, the second groove that width is sequentially reduced and is connected to are sequentially formed in first epitaxial layer
And third groove；
S503: photoetching is carried out to first epitaxial layer between the first groove, is formed from first epitaxial layer
Upper surface extend to the 4th groove of the substrate；
S504: in the first groove, the second groove, the third groove, the 4th groove and described first
Cvd silicon oxide on epitaxial layer, the silica for removing the bottom of the 4th groove later form the side for being located at the 4th groove
Second barrier layer of wall；
S505: to the 4th groove bottom and be located at the substrate in inject the second conductive type ion formed injection
Area, the injection region upper surface and be located in the 4th groove and form the second epitaxial layer of the second conduction type；
S506: the first groove, the bottom of the second groove and the third groove and first extension are removed
Silica on layer forms the first blocking of the side wall for being located at the first groove, the second groove and the third groove
Layer；
S507: respectively in the first groove, the second groove and the third groove fill metal layer formed it is whole
Area is flowed, between the first groove, the second groove and metal layer and first epitaxial layer in the third groove
Schottky barrier height is sequentially reduced.
The present invention by forming the first epitaxial layer over the substrate, and formation width successively subtracts in first epitaxial layer
First groove, second groove and third groove small and be connected to, form between the first groove from first epitaxial layer
Upper surface extend to the 4th groove of the substrate, the second barrier layer is formed in the side wall of the 4th groove, described the
The side wall of one groove, the second groove and the third groove forms the first barrier layer, the bottom of the 4th groove simultaneously
The injection region different from the conduction type of the substrate is formed in the substrate, the injection region upper surface and be located at
The second epitaxial layer is formed in 4th groove.Wherein, it is filled out in the first groove, the second groove and the third groove
The metal layer and first epitaxial layer filled forms Schottky contacts, reduces parasitic capacitance, reduces the power device and protects
Protect the conduction loss of chip, the metal layer filled in the first groove, the second groove and the third groove with it is described
The schottky barrier height of first epitaxial layer is sequentially reduced, the metal layer and first epitaxial layer filled in the third groove
The Schottky contacts of formation are preferentially connected, outside the metal layer and described first filled in the second groove and the first groove
The Schottky contacts for prolonging layer formation sequentially turn on, and filling in the first groove, the second groove and the third groove
Metal layer respectively with first epitaxial layer formed three Schottky diodes in parallel, equivalent to increase a plurality of electric current road
Diameter, which is realized, to be shunted, and the Anti-surging ability of the power device protection chip, the Reverse recovery of each Schottky diode are improved
The time short feature low with forward conduction voltage drop is made to play rectification in integrated circuits to power device protection chip
With.Setting extends to the isolated area of the substrate from first epitaxial layer between the first groove, for being isolated two
The current direction of the commutating zone, it is ensured that the electric current in power device protection chip uniformly circulates, and improves the power
The stability of device protection chip.The 4th groove bottom and be located at injection and the conduction of the substrate in the substrate
Different types of ion forms injection region, the injection region upper surface and be located in the 4th groove and form the second extension
Layer makes the substrate and the injection region form PN junction, equivalent to increase one layer of Withstand voltage layer, enhances the power device and protects
The reliability of chip is protected, while protecting core as the power device convenient for subsequent second metal area that formed on the second epitaxial layer
The back metal of piece effectively reduces the package area of the power device protection chip, reduces preparation cost.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the structural schematic diagram that power device of the present invention protects chip；
Fig. 2 to Figure 12 is the preparation process figure that power device of the present invention protects chip；
Figure 13 is the preparation flow figure that power device of the present invention protects chip；
Figure 14 is the equivalent circuit diagram that power device of the present invention protects chip.
In figure: power device protects chip 1；Substrate 10；First epitaxial layer 20；Commutating zone 30；First groove 31；Second ditch
Slot 32；Third groove 33；4th groove 34；Isolated area 40；First barrier layer 41；Second barrier layer 42；Injection region 43；Outside second
Prolong layer 44；Metal layer 50；First silicon oxide layer 51；Second silicon oxide layer 52；First metal area 61；Second metal area 62.
Specific embodiment
In order to be more clearly understood that the specific technical solution of the present invention, feature and advantage, with reference to the accompanying drawing and have
The present invention is further described in detail for body embodiment.
In the description of the present invention, it should be noted that term " on ", "lower", "left", "right", " transverse direction ", " longitudinal direction ",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
Refering to fig. 1, on the one hand, the present invention provides a kind of power device protection chip 1, using following technical scheme come real
It is existing.
A kind of power device protection chip 1 comprising:
The substrate 10 of first conduction type；
It is formed in the first epitaxial layer 20 of the first conduction type on the substrate 10；
It is spaced the commutating zone 30 being formed in first epitaxial layer 20, the commutating zone 30 includes from first extension
First groove 31 that the upper surface of layer 20 is formed into first epitaxial layer 20, from the bottom of the first groove 31 to described
The second groove 32 that is formed in first epitaxial layer 20 and from the bottom of the second groove 32 into first epitaxial layer 20 shape
At third groove 33, the first groove 31, the second groove 32 and the third groove 33 connection and width successively subtract
Small, the side wall of the first groove 31, the second groove 32 and the third groove 33 is each formed with the first barrier layer 41, institute
It states and is filled with metal layer 50 in first groove 31, the second groove 32 and the third groove 33, the first groove 31,
Schottky barrier between the second groove 32 and metal layer 50 and first epitaxial layer 20 in the third groove 33
Height is sequentially reduced；
The substrate 10 is extended to from the upper surface of first epitaxial layer 20 between two commutating zones 30
Isolated area 40, the isolated area 40 include the 4th groove 34, the second conduction type positioned at the bottom of the 4th groove 34
Injection region 43, be formed in the 4th groove 34 side wall the second barrier layer 42 and fill up the second of the 4th groove 34 and lead
Second epitaxial layer 44 of electric type.
The present invention is spaced in first epitaxial layer 20 and is formed by forming the first epitaxial layer 20 on the substrate 10
Commutating zone 30 sequentially forms the identical first groove 31 of depth, second groove 32 and third groove 33 in the commutating zone 30, and
Sequentially formed in the first groove 31, the second groove 32 and the third groove 33 positioned at the first groove 31,
First barrier layer 41 of the side wall of the second groove 32 and the third groove 33, respectively in the first groove 31, described
Metal layer 50 is filled in second groove 32 and the third groove 33, reduces the parasitic capacitance of the commutating zone 30, thus anti-
The flow direction that electric current is controlled when only the power device protection chip 1 is connected, blocks electric current to occur uneven, to improve the function
The stability of rate device protection chip 1.It is filled in the first groove 31, the second groove 32 and the third groove 33
Metal layer 50 forms Schottky contacts with first epitaxial layer 20 respectively, reduces parasitic capacitance, reduces the power device
Part protects the conduction loss of chip 1, equally also increases the current branch that the power device is protected in chip 1 and realizes shunting, from
And improve the Anti-surging ability of the power device protection chip 1.Second epitaxial layer 44 and 10 conduction type of substrate
Difference is equivalent to increase Withstand voltage layer, to improve the pressure-resistant performance of the power device protection chip 1, first metal
Area 61 and second metal area 62 are both formed in the top of first epitaxial layer 20, reduce the power device protection core
The package area of piece 1, reduces preparation cost.The isolated area for extending to the substrate 10 is formed between the commutating zone 30
40, make the current blocking of the commutating zone 30, improves the reliability of the power device protection chip 1.
Further, the depth of the first groove 31, the second groove 32 and the third groove 33 is all the same.?
In present embodiment, the first groove 31, the second groove 32 and the third groove 33 are sequentially communicated and depth is identical
It is formed in the substrate 10, effectively realizes that electric current uniformly circulates when the subsequent power device protection chip 1 is connected, and is convenient for
It is subsequent to prepare the metal layer 50.
Further, the width of the 4th groove 34 is greater than the half of the width of the third groove 33.In this implementation
In mode, sink simultaneously in the first groove 31, the second groove 32, the third groove 33 and the 4th groove 34
Product silica, forms the silica barrier layer for being located at above-mentioned all trenched side-walls, is convenient for the subsequent shape in the 4th groove 34
At second epitaxial layer 44, preparation process flow is saved, improves preparation efficiency, reduces preparation cost.
Further, the power device protection chip 1 further includes the upper table that interval is formed in first epitaxial layer 20
First silicon oxide layer 51 in face is formed in the upper surface of first silicon oxide layer 51 and extends to the upper of the first groove 31
First metal area 61 on surface, be formed in the isolated area 40 upper surface two sides the second silicon oxide layer 52 and be formed in institute
It states the upper surface of the second silicon oxide layer 52 and runs through the upper surface phase of second silicon oxide layer 52 and second epitaxial layer 44
The second metal area 62 even.In the present embodiment, spaced first silica is formed on first epitaxial layer 20
Layer 51 and the second silicon oxide layer 52, and the first gold medal is formed between first silicon oxide layer 51 and second silicon oxide layer 52
Belong to front metal of the area 61 as power device protection chip 1, and traditional power device is protected to the back of chip 1
Face metal and front metal are fabricated into the top for being respectively positioned on first epitaxial layer 20, can reduce the power device protection core
The area of piece 1, saves cost.
Refering to Fig. 2 to Figure 12 and Figure 13, on the other hand, the present invention also provides a kind of preparations of power device protection chip 1
Method comprising following processing step:
S501: providing the substrate 10 of first conduction type, and the of the first conduction type is formed on the substrate 10
One epitaxial layer 20；
Referring to Fig.2, the material of the substrate 10 can be silicon specifically, providing the substrate 10 of first conduction type
Or germanium selects material of the high purity silicon as substrate 10, in this way, being easy to implement, and can reduce manufacture in the present embodiment
Cost.Epitaxial growth can be homogeneity epitaxial layer, be also possible to epitaxially deposited layer, preferred homoepitaxy in present embodiment, i.e.,
The substrate 10 is the first conduction type, and first epitaxial layer 20 is the first conduction type, in other embodiments, according to
The conduction type of actual conditions, the substrate 10 and first epitaxial layer 20 can be the same or different.Same realization is outer
Prolonging growth also has a many methods, including molecular beam epitaxy, ultra-high vacuum CVD, normal pressure and reduced pressure epitaxy etc., can be with
First epitaxial layer 20 met the requirements.In present embodiment, using low pressure homoepitaxy, extension: refer in monocrystalline
On substrate, press the technical process that 10 crystal orientation of substrate grows monocrystal thin films.Homoepitaxy: one epitaxial layer 20 of growth regulation and substrate 10 are
Same material, this technique are homoepitaxy, this kind of simple process, but higher cost.Hetero-epitaxy: the film of epitaxial growth
Material and substrate 10 material are different, grow in other words chemical constituent, even physical structure and substrate it is entirely different first outside
Prolong layer 20, corresponding technique is just called hetero-epitaxy, and this kind of complex process, cost is relatively low, it is available meet the requirements it is certain
First epitaxial layer 20 of thickness is convenient for subsequent preparation process.
S502: the first groove 31, second that width is sequentially reduced and is connected to is sequentially formed in first epitaxial layer 20
Groove 32 and third groove 33；
Refering to Fig. 3, specifically, the first interval coating photoresist on first epitaxial layer 20, to not being covered by photoresist
The epitaxial layer 20 carry out photoetching, sequentially form the first groove 31, second groove 32 and third groove 33.In this implementation
In mode, the detailed process of the first groove 31 is formed are as follows: etching barrier layer is formed on first epitaxial layer 20, and (figure is not
Show), photoresist layer (not shown) is then formed on etching barrier layer, later using covering with 31 figure of first groove
Film version is exposed the photoresist layer, then develops, and obtains the photoresist layer with 31 figure of first groove.With
Photoresist layer with 31 figure of first groove is exposure mask, using lithographic methods such as reactive ion etching methods, is hindered in etching
Etching forms the figure opening (not shown) of the first groove 31 in barrier.Then to be opened with 31 figure of first groove
The etching barrier layer of mouth is exposure mask, using the methods of wet etching or dry etching, removes the institute for the barrier layer covering that is not etched
20 region of the first epitaxial layer is stated, and then forms the first groove 31 in first epitaxial layer 20, chemistry hereafter can be used
The methods of cleaning removal photoresist layer and etching barrier layer.It in above process, can also be in photoresist in order to guarantee exposure accuracy
Anti-reflecting layer is formed between layer and etching barrier layer.After completing the first groove 31, then in the first groove 31
It is interior that using above-mentioned identical photoetching technique formation, identical but width is less than the first groove with the depth of the first groove 31
31 second groove 32 is formed using above-mentioned identical photoetching technique identical but wide as the depth of the second groove 32 after the completion
Degree is less than the third groove 33 of the second groove 32, on the direction of the upper surface perpendicular to the substrate 10, described first
Groove 31, second groove 32 and the trapezoidal structural arrangement of third groove 33, convenient for subsequent in the first groove 31, described second
Filling metal and formation monox lateral wall in groove 32 and the third groove 33.
S503: photoetching is carried out to first epitaxial layer 20 between the first groove 31, is formed from outside described first
The upper surface for prolonging layer 20 extends to the 4th groove 34 of the substrate 10；
Refering to Fig. 4, specifically, the first interval coating photoresist on first epitaxial layer 20, using dry etching technology
The first epitaxial layer 20 between the commutating zone 30 carries out photoetching, forms the 4th groove 34 for extending to the substrate 10.?
In present embodiment, the detailed process of the 4th groove 34 is formed are as follows: form etch stopper on first epitaxial layer 20
Layer (not shown), then forms photoresist layer (not shown) on etching barrier layer, later using with the 4th groove figure
The mask plate of shape is exposed the photoresist layer, then develops, and obtains the photoetching with 34 figure of the 4th groove
Glue-line.Using the photoresist layer with 34 figure of the 4th groove as exposure mask, using lithographic methods such as reactive ion etching methods,
Etching forms the figure opening (not shown) of the 4th groove 34 on etching barrier layer.Then with the 4th groove 34
The etching barrier layer of figure opening is exposure mask, using the methods of wet etching or dry etching, removes the barrier layer that is not etched and covers
20 region of the first epitaxial layer of lid, and then the 4th groove 34 is formed in first epitaxial layer 20, hereafter it can adopt
Photoresist layer and etching barrier layer are removed with the methods of chemical cleaning.It in above process, can also be in order to guarantee exposure accuracy
Anti-reflecting layer is formed between photoresist layer and etching barrier layer.The width for forming the 4th groove 34 is greater than the third groove
The half of 33 width is convenient for subsequent preparation process, when power device chip protection chip 1 is connected, the isolated area
40 can be effectively isolated the electric current of the commutating zone 30, improve the stability of the power device protection chip 1.
S504: the first groove 31, the second groove 32, the third groove 33, the 4th groove 34 and
Cvd silicon oxide on first epitaxial layer 20, the silica for removing the bottom of the 4th groove 34 later are formed positioned at described
Second barrier layer 42 of the side wall of the 4th groove 34；
Refering to Fig. 5 and Fig. 6, specifically, first the first groove 31, the second groove 32, the third groove 33,
One layer of silica is deposited using thermal oxidation method on 4th groove 34 and first epitaxial layer 20, it is carved later using dry method
Etching off is located at the second barrier layer 42 of the side wall of the 4th groove 34 except the silica of the bottom of the 4th groove 34 is formed.
In the present embodiment, the width of the 4th groove 34 is greater than the half of the width of the third groove 33, the 4th ditch
The silica deposited in slot 34 is unfilled, convenient for forming monox lateral wall in above-mentioned all grooves, in the subsequent power device
When part protects chip 1 to be connected, prevent electric current from uneven circulation occur, to enhance the work of the power device protection chip 1
Stability.
S505: to the 4th groove 34 bottom and be located in the substrate 10 and inject the second conductive type ion and formed
Injection region 43, the injection region 43 upper surface and be located at the 4th groove 34 in formed outside the second of the second conduction type
Prolong layer 44；
Refering to Fig. 7 and Fig. 8, specifically, first in the bottom of the 4th groove 34 and the position in the substrate 10
Using light shield, exposure, development, show that the figure of the injection region 43, the ion of the second conduction type of injection form injection region
43.In the present embodiment, the ion of the second conduction type is phosphorus, and the concentration of the injection region 43 is greater than the substrate 10
The conduction type of concentration, the substrate and the injection region is differently formed PN junction, improves the pressure resistance of the power device protection core 1
Performance forms the second epitaxial layer 44 in the 4th groove 34, further increases the breakdown of the power device protection chip 1
Voltage.
S506: the first groove 31, the bottom of the second groove 32 and the third groove 33 and described are removed
Silica on one epitaxial layer 20 forms the side for being located at the first groove 31, the second groove 32 and the third groove 33
First barrier layer 41 of wall；
Refering to Fig. 9, specifically, first using dry etching technology remove the first groove 31, the second groove 32 and
The silica of 33 bottom of third groove, while the silica on first epitaxial layer 20 is removed, retain first ditch
The silica of the side wall of slot 31, the second groove 32 and the third groove 33 forms and is located at the first groove 31, described
First barrier layer 41 of the side wall of second groove 32 and the third groove 33.In the present embodiment, first barrier layer
41 material is silica, can be prepared by thermal oxidation method cvd silicon oxide, and first barrier layer 41 is located at above-mentioned all
The side wall of groove, effectively control electric current are successively in the third groove 33, the second groove 32 and the first groove 31
Uniformly circulation further increases the reliability of the power device protection chip 1.
S507: metal layer is filled in the first groove 31, the second groove 32 and the third groove 33 respectively
50 form commutating zone 30, the first groove 31, the second groove 32 and metal layer 50 and institute in the third groove 33
The schottky barrier height stated between the first epitaxial layer 20 is sequentially reduced；
Refering to fig. 10, specifically, first filling metal in the third groove 33 using the technology of magnetron sputtering, then exist
Metal is filled using magnetron sputtering technique in the second groove 32, magnetron sputtering skill is finally used in the first groove 31
Art fills metal, later rapid thermal annealing.In the present embodiment, the material of the metal of filling may be the same or different,
The material of the i.e. described metal layer 50 can be one of gold, aluminium, copper or three kinds, and the first groove 31, second ditch
The schottky barrier height formed between slot 32 and metal layer 50 and first epitaxial layer 20 in the third groove 33 according to
Secondary reduction, the conduction voltage drop that the Schottky contacts of metal layer 50 and first epitaxial layer 20 in the third groove 33 are formed
Minimum, after subsequent power device protection chip 1 is connected, the first groove 31, the second groove 32 and described the
Metal layer 50 in three grooves 33 forms three Schottky diodes in parallel with first epitaxial layer 20, is equivalent to three electricity
Flow path, which is realized, to be shunted, and the Anti-surging ability of the power device protection chip 1, the third groove 33, described second are enhanced
Groove 32 and the corresponding Schottky diode of the first groove 31 sequentially turn on, so that it is guaranteed that the power device protects chip
The stability of electric current in 1.
S508: one layer is deposited in the upper surface of the first groove 31, the isolated area 40 and first epitaxial layer 20
Silica, the corresponding silica formation in upper surface that etching removes the first groove 31 are arranged at first epitaxial layer
The first silicon oxide layer 51 on 20, the corresponding silica in upper surface for removing second epitaxial layer 44 form the second silicon oxide layer
52；
Refering to fig. 11, specifically, first in the upper of the first groove 31, the isolated area 40 and first epitaxial layer 20
Surface deposits one layer of silica using thermal oxidation method, and the corresponding oxygen in upper surface of the first groove 31 is removed using dry etching
SiClx forms the first silicon oxide layer being arranged on first epitaxial layer 20, is removed outside described second using dry etching
The corresponding silica in upper surface for prolonging layer 44 forms spaced second silicon oxide layer 52.In the present embodiment, described
Silicon dioxide layer 52 forms first metal area 61 and described between first silicon oxide layer 51, convenient for subsequent preparation
Second metal area 62.
S509: the upper surface of the first groove 31 is formed and extended in the upper surface of first silicon oxide layer 51
First metal area 61, second silicon oxide layer 52 upper surface and extend to second epitaxial layer 44 upper surface
Two metal areas 62, first metal area 61 are alternatively arranged with second metal area 62, finally obtain power device protection core
Piece 1.
Refering to fig. 12, specifically, first using magnetron sputtering technique in first silicon oxide layer 51 and second oxidation
One layer of metal is filled in the upper surface of silicon layer 52, removes the part metals of second silicon oxide layer 52 using dry etching later,
It forms the upper surface positioned at first silicon oxide layer 51 and extends to the first metal area of the upper surface of the first groove 31
61, and it is formed in spaced second metal area 62 of first metal area 62.In the present embodiment, first metal
Area 61 and second metal area 62 are respectively positioned on the top of first epitaxial layer 20, and second metal area 62 is from described the
The upper surface of silicon dioxide layer 52 extends to second epitaxial layer 44, and first metal area 61 is protected as the power device
The anode of chip 1 is protected, therefore cathode of second metal area 62 as power device protection chip 1 reduces described
Power device protects the package area of chip 1, reduces costs.
Refering to fig. 14, in the present embodiment, the first conduction type is p-type, and the second conduction type is N-type, described first
Metal area 61 is the anode that the power device protects chip 1, and second metal area 62 is that the power device protects chip 1
Cathode.
The present invention on the substrate 10 by forming the first epitaxial layer 20, the formation width in first epitaxial layer 20
First groove 31, second groove 32 and the third groove 33 for being sequentially reduced and being connected to are formed certainly between the first groove 31
The upper surface of first epitaxial layer 2.0 extends to the 4th groove 34 of the substrate 10, in the side wall of the 4th groove 34
The second barrier layer 42 is formed, forms the in the side wall of the first groove 31, the second groove 32 and the third groove 33
One barrier layer 41 is formed and the conduction type of the substrate 10 in the bottom and being located in the substrate 10 of the 4th groove 34
Different injection regions 43, the injection region 43 upper surface and be located at the 4th groove 34 in form the second epitaxial layer 44.
Wherein, the metal layer 50 and described first filled in the first groove 31, the second groove 32 and the third groove 33
Epitaxial layer 20 forms Schottky contacts, reduces parasitic capacitance, reduces the conduction loss of the power device protection chip 1,
The metal layer 50 and first epitaxial layer filled in the first groove 31, the second groove 32 and the third groove 33
20 schottky barrier height is sequentially reduced, the metal layer 50 filled in the third groove 33 and 20 shape of the first epitaxial layer
At Schottky contacts be preferentially connected, the metal layer 50 filled in the second groove 32 and the first groove 31 and described the
The Schottky contacts that one epitaxial layer 20 is formed sequentially turn on, and the first groove 31, the second groove 32 and the third
The metal layer 50 filled in groove 33 forms three Schottky diodes in parallel with first epitaxial layer 20 respectively, is equivalent to
It increases a plurality of current path and realizes shunting, improve the Anti-surging ability of the power device protection chip 1, each Schottky
The reverse recovery time of the diode short feature low with forward conduction voltage drop, to collect to power device protection chip 1
At playing rectified action in circuit.It is arranged between the first groove 31 from first epitaxial layer 20 and extends to the substrate
10 isolated area 40, for the current direction of two commutating zones 30 to be isolated, it is ensured that in power device protection chip 1
Electric current uniformly circulate, improve the stability of power device protection chip 1.The 4th groove 34 bottom and be located at
The injection ion different from the conduction type of the substrate 10 forms injection region 43 in the substrate 10, in the injection region 43
Upper surface is simultaneously located at the second epitaxial layer 44 of formation in the 4th groove 34, and the substrate 10 is made to form PN with the injection region 43
Knot, second epitaxial layer 43 enhance the reliability of the power device protection chip 1, together equivalent to increase Withstand voltage layer
When convenient for it is subsequent formed on the second epitaxial layer 44 second metal area 62 as the power device protection chip 1 back-side gold
Belong to, effectively reduces the package area of the power device protection chip 1, reduce preparation cost.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly be will be evident.
Therefore, appended claims should regard the whole variations and modifications for covering true intention and range of the invention as.It is weighing
The range and content of any and all equivalences, are all considered as still belonging to the intent and scope of the invention within the scope of sharp claim.
Claims (10)
1. a kind of power device protects chip, it is characterised in that: comprising:
The substrate of first conduction type；
Form the first epitaxial layer of the first conduction type over the substrate；
It is spaced the commutating zone being formed in first epitaxial layer, the commutating zone includes from the upper surface of first epitaxial layer
The first groove that is formed into first epitaxial layer is formed from the bottom of the first groove into first epitaxial layer
Second groove and the third groove formed from the bottom of the second groove into first epitaxial layer, the first groove,
The second groove and third groove connection and width is sequentially reduced, the first groove, the second groove and described
The side wall of third groove is each formed with the first barrier layer, in the first groove, the second groove and the third groove
Metal layer and first extension filled with metal layer, in the first groove, the second groove and the third groove
Schottky barrier height between layer is sequentially reduced；
The isolated area of the substrate is extended to from the upper surface of first epitaxial layer between two commutating zones, it is described
Isolated area include the 4th groove, positioned at the bottom of the 4th groove the second conduction type injection region, be formed in described
Second barrier layer of the side wall of four grooves and fill up the 4th groove the second conduction type the second epitaxial layer.
2. power device according to claim 1 protects chip, it is characterised in that: the first groove, second ditch
The depth of slot and the third groove is all the same.
3. power device according to claim 1 protects chip, it is characterised in that: the width of the 4th groove is greater than institute
State the half of the width of third groove.
4. power device according to claim 1 protects chip, it is characterised in that: the power device protection chip also wraps
Include the first silicon oxide layer for being spaced the upper surface for being formed in first epitaxial layer, the upper surface for being formed in first oxide layer
And extend to the first metal area of the upper surface of the first groove, the upper surface for being formed in the isolated area two sides second
Silicon oxide layer and it is formed in the upper surface of second silicon oxide layer and through second silicon oxide layer and second extension
The second connected metal area of the upper surface of layer.
5. a kind of preparation method of power device protection chip as described in claim 1, which is characterized in that it includes following work
Skill step:
S501: the substrate of first conduction type is provided, forms the first epitaxial layer of the first conduction type over the substrate；
S502: first groove, the second groove and that width is sequentially reduced and is connected to are sequentially formed in first epitaxial layer
Three grooves；
S503: photoetching is carried out to first epitaxial layer between the first groove, is formed from the upper of first epitaxial layer
Surface extends to the 4th groove of the substrate；
S504: in the first groove, the second groove, the third groove, the 4th groove and first extension
Cvd silicon oxide on layer, the silica for removing the bottom of the 4th groove later form the side wall for being located at the 4th groove
Second barrier layer；
S505: to the 4th groove bottom and be located at the substrate in inject the second conductive type ion formed injection region,
The injection region upper surface and be located in the 4th groove and form the second epitaxial layer of the second conduction type；
S506: it removes on the first groove, the bottom of the second groove and the third groove and first epitaxial layer
Silica formed be located at the first groove, the second groove and the third groove side wall the first barrier layer；
S507: filling metal layer respectively in the first groove, the second groove and the third groove and form commutating zone,
Schottky barrier between the first groove, the second groove and metal layer and the epitaxial layer in the third groove
Height is sequentially reduced.
6. the preparation method of power device protection chip according to claim 5, which is characterized in that further include:
S508: one layer of silica, etching are deposited in the upper surface of the first groove, the isolated area and first epitaxial layer
The corresponding silica in upper surface for removing the first groove forms the first oxidation being arranged on first epitaxial layer
Silicon layer, the corresponding silica in upper surface for removing second epitaxial layer form the second silicon oxide layer.
7. the preparation method of power device protection chip according to claim 6, which is characterized in that further include:
S509: the first metal in the upper surface that the upper surface of first silicon oxide layer is formed and extends to the first groove
Area, second oxide layer upper surface and extend to second epitaxial layer upper surface the second metal area, described
One metal area is alternatively arranged with second metal area, finally obtains power device protection chip.
8. the preparation method of power device protection chip according to claim 5, it is characterised in that: the step S503
In, the 4th groove is formed using dry etching, the width of the 4th groove is greater than the one of the width of the third groove
Half.
9. the preparation method of power device protection chip according to claim 5, it is characterised in that: the first groove,
The second groove and the depth of the third groove are identical, and the width of the first groove is less than between the first groove
Distance.
10. the preparation method of power device protection chip according to claim 5, it is characterised in that: the step S505
In, metal layer is successively filled in the third groove, the second groove and the first groove using magnetron sputtering.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111192826A (en) * | 2019-05-31 | 2020-05-22 | 深圳方正微电子有限公司 | Double-barrier trench epitaxial high-voltage PIN chip and its manufacturing method |
| CN114023737A (en) * | 2021-11-05 | 2022-02-08 | 深圳市鑫飞宏电子有限公司 | A kind of electrostatic protection chip based on power management and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205319164U (en) * | 2016-01-05 | 2016-06-15 | 上海美高森美半导体有限公司 | Transient voltage suppressor |
| US20170345906A1 (en) * | 2015-07-13 | 2017-11-30 | Diodes Incorporated | Self-Aligned Dual Trench Device |
| CN107910374A (en) * | 2017-12-13 | 2018-04-13 | 深圳市晶特智造科技有限公司 | Superjunction devices and its manufacture method |
-
2018
- 2018-09-29 CN CN201811151183.1A patent/CN109300894B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170345906A1 (en) * | 2015-07-13 | 2017-11-30 | Diodes Incorporated | Self-Aligned Dual Trench Device |
| CN205319164U (en) * | 2016-01-05 | 2016-06-15 | 上海美高森美半导体有限公司 | Transient voltage suppressor |
| CN107910374A (en) * | 2017-12-13 | 2018-04-13 | 深圳市晶特智造科技有限公司 | Superjunction devices and its manufacture method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111192826A (en) * | 2019-05-31 | 2020-05-22 | 深圳方正微电子有限公司 | Double-barrier trench epitaxial high-voltage PIN chip and its manufacturing method |
| CN111192826B (en) * | 2019-05-31 | 2023-05-26 | 深圳方正微电子有限公司 | Double barrier trench epitaxial high voltage PIN chip and manufacturing method thereof |
| CN114023737A (en) * | 2021-11-05 | 2022-02-08 | 深圳市鑫飞宏电子有限公司 | A kind of electrostatic protection chip based on power management and preparation method thereof |
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