CN109166837A - Semiconductor devices and manufacturing method - Google Patents
Semiconductor devices and manufacturing method Download PDFInfo
- Publication number
- CN109166837A CN109166837A CN201810933697.6A CN201810933697A CN109166837A CN 109166837 A CN109166837 A CN 109166837A CN 201810933697 A CN201810933697 A CN 201810933697A CN 109166837 A CN109166837 A CN 109166837A
- Authority
- CN
- China
- Prior art keywords
- lower conductor
- top surface
- barrier film
- sidewall
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H10D64/011—
-
- H10W20/43—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
- H10D30/6219—Fin field-effect transistors [FinFET] characterised by the source or drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
-
- H10W20/083—
-
- H10W20/088—
-
- H10W20/089—
-
- H10W20/40—
-
- H10W20/42—
-
- H10W20/47—
-
- H10W20/425—
-
- H10W20/435—
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
Abstract
一种半导体器件包括具有下导体侧壁的下导体、具有直接形成在下导体侧壁上的阻挡膜侧壁的阻挡膜、和形成在下导体的顶表面上的通路。阻挡膜侧壁的顶部分是凹入的，使得阻挡膜侧壁的顶表面在比下导体的顶表面低的水平。
A semiconductor device includes a lower conductor having lower conductor sidewalls, a barrier film having barrier film sidewalls formed directly on the lower conductor sidewalls, and a via formed on a top surface of the lower conductor. The top portion of the barrier film sidewall is concave such that the top surface of the barrier film sidewall is at a lower level than the top surface of the lower conductor.
Description
The application for be the applying date be August in 2013 27, application No. is 201310378594.5, it is entitled
The divisional application of the patent application of " semiconductor devices and manufacturing method ".
Technical field
Present inventive concept relates in general to semiconductor devices and its manufacturing method.
Background technique
Modern semiconductor devices is manufactured by the manufacturing process of a series of complex.It is some including standard in these techniques
Standby substrate, deposition materials, selective etch material part, cleaning substrate etc..In applied set, complexity is continuously partly led
Body manufacturing process forms very small structure, component, element, region, connector, feature etc..Most of emerging semiconductor
Device is even more more dense than its antecessor to be integrated.Thus, the composition component of modem semi-conductor devices is designed to mutually very
It is close, and usually characterized by fabulously small geometry.It is such neighbouring to narrow and size reduces and requires making
Precision big in the application of technique is made, because the even very small deviation relative to predetermined design also results in overall semiconductor
The catastrophic failure of device.
Almost all of modem semi-conductor devices all include that the multiple of different material layer being arranged in above basic substrate lead
Electric device.Arbitrary directionality is distributed to semiconductor devices, that is, the material layer of composition, therefore many formed by the material layer
Component and/or region " laterally " extend across the main surface or " laterally " extension on it of substrate.In this respect, certain
" vertical " electrical connector can be used will be generally referred to as access (via) structure be formed in down " conductor " (for example, element or
Region) and upper conductor between.Therefore, term " access " indicates the vertically extending conductive interconnection between two or more conductors,
Described two or more conductors are at least partly being made on lining with (in z-direction) different " height " or "horizontal" setting
Above semiconductor devices in the lateral surfaces (direction X/Y) at bottom.
Consider it is above-mentioned the separation being steadily decreasing between size, ratio, geometry and semiconductor subassembly away from
Problem from aspect, the accurate manufacture of lower conductor, upper conductor and corresponding connecting path are the careful things considered and trouble executes
Object.
For example, if the gained resistance meeting between lower conductor and access, between lower conductor and access occurs for misalignment
It undesirably increases.In addition, the interlayer dielectric around lower conductor, which is arranged in, to be damaged during access is formed.It is such
Meeting is damaged so that semiconductor devices is with reduced reliability operation.
Summary of the invention
The embodiment of present inventive concept provides the semiconductor devices with bigger precision and less manufacturing fault.This
The embodiment of inventive concept shows improved reliability, because damaging quilt to the manufacture that is not intended to of indirect material layer and component
It avoids or is greatly reduced.
The one side conceived according to the present invention provides a kind of semiconductor devices, which includes: with lower conductor
The lower conductor of side wall, the barrier film with the barrier film side wall being formed directly on lower conductor side wall and it is formed in lower conductor
Access on top surface.The top part of barrier film side wall is recessed, so that the top surface of barrier film side wall is located at the top than lower conductor
The low level in surface.
The one side conceived according to the present invention provides a kind of semiconductor devices, which includes: to lead under first
Body has the first lower conductor side wall；Second lower conductor has the second lower conductor side wall, wherein leading under the first lower conductor and second
The same metal layer of semiconductor devices is arranged in body；First barrier film has the be formed directly on the first lower conductor side wall
One barrier film side wall；Second barrier film has the second barrier film side wall being formed directly on the second lower conductor side wall；With it is logical
Road is formed on the top surface of the first lower conductor, wherein the top part of the first barrier film side wall is recessed, so that the first barrier film side
The top surface of wall is in the level lower than the top surface of the first lower conductor.
The one side conceived according to the present invention provides a kind of method of manufacturing semiconductor devices, this method comprises: in substrate
It is upper to form the lower conductor with lower conductor side wall；Barrier film is formed, which, which has, is formed directly on lower conductor side wall
Barrier film side wall, wherein the combination of lower conductor and barrier film by the first insulating layer horizontally around；In the first insulating layer, lower conductor
With second insulating layer is formed on barrier film；Third insulating layer is formed over the second dielectric；It is formed through third insulating layer and the
The through-hole of two insulating layers is to expose the top surface of lower conductor and the top part of barrier film side wall；Make the top of the exposure of barrier film side wall
It is partially recessed into, so that the level that the top surface of barrier film side wall is low in the top surface than lower conductor.
Detailed description of the invention
In the certain embodiments for considering to be described with reference to the drawings, for those skilled in the art, structure of the present invention
The above and other feature and advantage thought will be apparent, in the accompanying drawings:
Fig. 1 is the partial layout diagram for showing the semiconductor devices for the embodiment conceived according to the present invention；
Fig. 2 is local perspective view, the semiconductor devices of Fig. 1 is further shown and have been shown in particular the first upper conductor,
Relationship between first lower conductor and access；
Fig. 3 is the sectional view intercepted along the line A-A of Fig. 1；
Fig. 4 is the enlarged drawing for further showing the region part ' C ' indicated in Fig. 3；
Fig. 5 is the sectional view intercepted along the line B-B of Fig. 1；
Fig. 6 is the sectional view of the semiconductor devices for another embodiment conceived according to the present invention；
Fig. 7 is the sectional view of the semiconductor devices for another embodiment conceived according to the present invention；
Fig. 8 is the partial cross-sectional view of the semiconductor devices for another embodiment conceived according to the present invention；
Fig. 9 is the perspective view of the semiconductor devices for another embodiment conceived according to the present invention；
Figure 10 is the sectional view intercepted along the line D-D of Fig. 9；
Figure 11 is the sectional view intercepted along the line E-E of Fig. 9；
Figure 12 is the overall layout chart for showing the semiconductor devices for another embodiment conceived according to the present invention；
Figure 13 be may include the embodiment conceived according to the present invention semiconductor devices electronic system block diagram；
Figure 14 and Figure 15 show jointly may include the embodiment conceived according to the present invention semiconductor devices electronics
System；With
Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, Figure 21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26 and Figure 27 are (hereinafter, figure
It 16 to Figure 27) is that the certain centres that can be used during the manufacturing method for the certain embodiments conceived according to the present invention are shown
Processing step.
Specific embodiment
By reference to that, to the described in detail below of embodiment, present inventive concept can be more easily to understand in conjunction with attached drawing
The advantages of and feature and the method for completing it.However, present inventive concept can be embodied in many different forms and should not be by
It is understood to be limited to shown embodiment.But these embodiments are provided so that the disclosure will be thoroughly and complete, and
The concept of present inventive concept will be conveyed comprehensively to those skilled in the art.The range of present inventive concept is by claim below
And its equivalent limits.Thus, it is in the following description, certain well-known in order to avoid unnecessary and details that is may obscuring
Method, step, component and circuit be not described in detail.
It will be understood that although term first, second etc. can be used for this describe different elements, component, region, layer and/
Or part, but these elements, component, regions, layers, and/or portions should not be limited by these terms.These terms are only used to areas
Divide an element, component, region, layer or part and another element, component, region, layer or part.Thus, discussed below
One element, component, region, layer or part can be referred to as second element, component, region, layer or part, without departing from the present invention
Introduction.
Term as used herein is only for the purpose of description particular implementation, is not intended to limit the present invention.Make herein
Used time, singular are also intended to including plural form, unless in addition context clearly indicates.It will also be understood that when in this explanation
In use, the terms "include", "comprise" indicate the presence of the feature, integer, step, operation, element and/or component in book,
But it is not excluded for one or more other features, integer, step, operation, the presence or addition of element, component and/or its group.
Unless otherwise defined, all terms (including technical and scientific term) as used herein have with belonging to the present invention
Field in the normally understood identical meanings of those of ordinary skill.It will also be understood that term is (such as in usually used dictionary
It is defined those) should be understood have with the consistent meaning of meaning in the background of related fields, will not be understood to
Idealization or excessively formal meaning, unless being clearly so defined herein.
It hereinafter, will be with reference to Fig. 1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5 (hereinafter, Fig. 1 to Fig. 5) description is conceived according to the present invention
Embodiment certain semiconductor devices.
Figure (figure) 1 is the layout for showing the semiconductor devices for the embodiment conceived according to the present invention.Fig. 2 is Fig. 1
Semiconductor devices local perspective view, particularly illustrate the structure between the first upper conductor, the first lower conductor and access
Relationship.Fig. 3 is the sectional view intercepted along the line A-A of Fig. 1.Fig. 4 is the enlarged drawing of the specified portions ' C ' of Fig. 3.Fig. 5 is along Fig. 1
The sectional view of line B-B interception.
Collective reference Fig. 1 to Fig. 5, semiconductor devices 1 in the first upper conductor 120, the second upper conductor 110, third including leading
Body 130, lower conductor 160, barrier film 170, the 150, first insulating film 180 of access (via), the second insulating film 190 and third insulation
Film 195.
First insulating film 180 surrounds lower conductor 160 and barrier film 170, but exposure lower conductor 160 and barrier film 170
Upper surface.Second insulating film 190 can be formed on the first insulating film 180 as etching effective during forming access 150
Stopper film.Third insulating film 195 can be formed on the second insulating film 190 to lead on (and electrically separated) access 150, first
Body 120, the second upper conductor 110 and third upper conductor 130.In some embodiments, the first insulating film 180, the second insulating film
And/or third insulating film 195 can be by one or more materials such as SiO2, SiN, SiON, SiCN and low k dielectric material etc.
It is formed.However, technical personnel in this field will understand that the embodiment of the problem of this is design alternative and present inventive concept is simultaneously
It is not strictly limited to these materials.
In the certain embodiments of present inventive concept, the first upper conductor 120, the second upper conductor 110 and third upper conductor
130 can be interconnection.As shown in FIG. 1, the first upper conductor 120, the second upper conductor 110 and third upper conductor 130 can be
Laterally advance (for example, X-direction) interconnection, but this be only can with the consistent semiconductor of the embodiment of present inventive concept
A selection example in many differences " upper conductor " used in device.In first upper conductor 120, the second upper conductor and third
Conductor 130 can be characterized by constant space (P), but this situation for being not required in other embodiments.Spacing P will lead to
Often extremely it is small-(for example) between 10nm and 100nm.
In the shown example of Fig. 3, access 150 is for vertically interconnecting the first upper conductor 120 and lower conductor 160.Also
It is that access 150 " can be formed in " 160 "upper" of lower conductor, and/or 120 "lower" of " being formed in " first upper conductor.In structure of the present invention
In the certain embodiments of think of, access 150 will be referred to as " autoregistration access ".
It can be used to form a kind of manufacturing method of autoregistration access below with reference to Figure 16 to Figure 27 description.Use autoregistration
Access manufacturing method simultaneously refers to Fig. 3, and the width " W5 " of the width " W1 " of the first upper conductor 120 and access 150 can substantially phase
Deng.It is, depend on the variation of such as treatment conditions, the width W5 of the width W1 of the first upper conductor 120 and access 150 can be with
It is essentially equal or they can be slightly different.In many embodiments, very desirably, the side wall of the first upper conductor 120
The side wall 150a and 150b of 120a and 120b and access 150 are matched with precisely aligning respectively as much as practically possible.
It is formed for this purpose, dual damascene (dual damascene) method can be used in the first upper conductor 120 and access 150.?
It is exactly that the first upper conductor 120 is dual daascence interconnection, access 150 can be dual damascene access.
In some embodiments, lower conductor 160 can be contact or interconnection.As shown in figure 3, lower conductor 160 can be with
For island shape and can extend transversely with.Lower conductor 160 can be by all such as (e.g.) aluminium of one or more conductive materials, tungsten etc.
It is formed.Lower conductor 160 is formed into the first side wall 160a and second sidewall 160b.
Design rule is generally understood by the person skilled in the art certain crucial rulers for restriction and regulation semiconductor devices
Very little (CD) and/or spatial relationship.Critical size relationship another example is the top surfaces of lower conductor 160 relative to access 150
The relative size of bottom surface.For example, design rule can require the width " W3 " of lower conductor 160 to be necessarily less than the width of access 150
Spend W5.
The manufacture of lower conductor 160 is further related to, barrier film 170 may include the first side wall 170a, second sidewall 170b
With bottom section 170d.The first side wall 170a can be formed on the first side wall 160a of lower conductor 160, and second sidewall 170b can
To be formed on the second sidewall 160b of lower conductor 160.Bottom section 170d can be formed under the bottom surface of lower conductor 160
Face.Barrier film 170 can be formed by one or more materials including such as Ti and/or TiN.In some embodiments, it hinders
Gear film 170 can have the stepped construction of Ti/TiN.
Lower conductor 160 is formed close to the first groove 171, and the first groove 171 and the first side wall 170a is related (associate)
And it is similarly related with second sidewall 170b.Relative to the top surface of lower conductor 160, the first groove 171 can be certain
Be formed as (for example) existing in embodimentWithBetween depth.In a specific embodiment,
First groove 171 is formed asThe depth of left and right.
Thus, with specific reference to Fig. 4, the top surface of lower conductor 160 can extend upwardly to the first side wall than barrier film 170
The high level of the top surface of the top surface 170c and second sidewall 170b of 170a.It should be it is noted here that about lower conductor
When 160 the first side wall 160a and second sidewall 160b extend, the turning (or edge) of the top surface of lower conductor 160 partially can be with
It is circular.Thus, difference in height " H " (or " height step ") can reside in the phase of the first side wall 170a and second sidewall 170b
It answers between top surface and the top surface of lower conductor 160.The height step is substantially close to lower conductor 160 and barrier film 170
Top surface between boundary formed the first groove 171.
In addition, the first insulating film 180 may include the first insulating film 180 in the adjacent part of the first groove 171
The second groove 181 formed.As shown in Fig. 4 more specifically, " the recessed area including the first groove 171 and the second groove 181
Domain ", which can have, to be upwardly extended and increased width with recessed area from the top surface 170c of barrier film 170.It is used to form logical
The conductive material on road 150 will fill both the first groove 171 and the second groove 181 of recessed area.
It is not right in the case of wherein the first groove 171 or the second groove 181 are not continuously formed as fabricated structure
It will definitely can occur during subsequently forming access 150.For example, in the first insulating film 180 not suitably along the first side wall 170a
Entire vertical length formed (that is, some hollow spaces are present between the first insulating film 180 and the first side wall 170a) feelings
Under shape, the canine tooth shape protrusion for forming the conductive material of access 150 may downwardly drop to the along the first side wall 170a
In one insulating film 180.This unwanted material migration has the critical width size (critical of lower conductor 160
Width dimension) to change (that is, expansion) be the effect for being likely larger than the width of access 150.
Thus, it is the decline of conductive material, canine tooth shape prominent even if there is no some misalignments during forming access
It rises and is also possible to be formed in the first insulating film 180.The protrusion of such canine tooth shape can make lower conductor 160 and access 150
Between resistance increase be more than specification.
In the semiconductor devices shown in Fig. 1 to Fig. 5, decline, canine tooth are generated in the first insulating film 180 in order to prevent
The protrusion of shape, a part of the first side wall 170a are selectively removed.It is, the first groove 171 is formed in the first side wall
Between the top surface 170c of 170a and the top surface 160c of lower conductor 160.Therefore, because access 150 is filled up completely the first groove
171, so the contact area between lower conductor 160 and access 150 increases.As a result, between the first lower conductor 160 and access 150
Resistance can reduce.In addition, the recessed area including the first groove 171 and the second groove 181 " will increase upwards ".Namely
It says, the width of recessed area will increase with the height above the top surface 170c of the first side wall 170a.Therefore, access
150 will easily fill the entire recessed area including the first groove 171 and the second groove 181.
In addition, as shown shown in example, the top surface 160c of lower conductor 160 can its vpg connection relatively
" protrusion " (that is, relatively high in its peripheral edge in its center).However, the top surface 160c of lower conductor 160 is " relatively convex
Rise " description allow in central part to be to a certain degree flat and in the relatively more raised sphering in edge (or bending).It is logical
It crosses and relatively raised top surface 160c is provided for lower conductor 160, the contact area between lower conductor 160 and access 150 increases.Cause
This, the resistance between the first lower conductor 160 and access 150 can reduce.And even if little Cheng occurs during manufacturing access 150
The misalignment of degree, the resistance between lower conductor 160 and access 150 will not be significant increase.Therefore, each lower conductor 160 and phase
The resistance deviation between access 150 answered is not too large.As a result, the semiconductor devices for the embodiment conceived according to the present invention
Operating reliability is very high.
Fig. 6 is the sectional view of the semiconductor devices for another embodiment conceived according to the present invention.For simplicity, real
Similar component, region and element will be similarly numbered or mark between the embodiment respectively shown in matter.
With reference to Fig. 6, semiconductor devices 2 includes the first lower conductor 160 and the second lower conductor 260 being disposed adjacent to each other.Such as
Shown in Fig. 6, the first lower conductor 160 and the second lower conductor 260 can form identical gold in the overall structure of semiconductor devices 2
Belong to level, can be formed by substantially the same material, and can be formed simultaneously during manufacture.
As described above, the first lower conductor 160 includes the first side wall 160a and second sidewall 160b, and 170 shape of barrier film
At around the first lower conductor 160.
Third side wall 260a and the 4th side wall 260b, 270 shape of the second barrier film can be similarly included in second lower conductor 260
At around the second lower conductor 260.It is, the second barrier film 270 includes the third side wall for being formed in the second lower conductor 260
Third side wall 270a on 260a and the 4th side wall 270b being formed on the 4th side wall 260b of the second lower conductor 260.
As previously mentioned, access 150 is formed on the first lower conductor 160.Because barrier film 170 the first side wall 170a (or
Second sidewall 170b) place in place is formed with the first groove 171, so the first side wall 170a (or second sidewall 170b)
Top surface 170c can be formed in the level lower than the top surface 160c of the first lower conductor 160.First insulating film 180 is similar to landform
At corresponding second groove 181 having close to the formation of the first groove 171.Including the first groove 171 and the second groove 181 therefore,
The recessed area of the two could be formed with upward increased width, so that access 150 will fill the first groove 171 and the second groove
Both 181, as previously described.
On the contrary, access is not formed on the second lower conductor 260 of Fig. 6.Therefore, the third side wall of the second barrier film 270
The similar top surface of the top surface 270c and the 4th side wall 270b of 270a are at least with the top surface 260c's of the second lower conductor 260
Highly equal (that is, being formed in equal level or level more higher than the top surface 260c of the second lower conductor 260).Fig. 6's
In the embodiment shown, the top surface and the second lower conductor of the top surface 270c and the 4th side wall 270b of third side wall 270a
260 top surface 260c height is equal.
The embodiment of Fig. 6 is further related to, the top surface 160c of the first lower conductor 160 can be less than or wait in height
In the top surface 260c of the second lower conductor 260.
After forming through-hole 197 (being described below), the first groove 171 and the second groove 181 can pass through etching first
The top surface 170c of side wall 170a (and/or second sidewall 170b) exposed by through-hole 197 and formed.Thus, because under second
Conductor 260 is not connected to access 150, the second barrier film 270 third side wall 270a (or the 4th side wall 270b) it is corresponding
Top surface 270c on will be formed without such groove.
As described above, the top surface 160c of the first lower conductor 160 can be relatively raised, and the top table of the second lower conductor 260
Face 260c can be completely flat.
Fig. 7 is the sectional view of the semiconductor devices for another embodiment conceived according to the present invention.
With reference to Fig. 7, semiconductor devices 3 includes lower conductor 160 and access 150.However, with previously described embodiment phase
Than the substantial misalignment of the two elements.It is, as shown in fig. 7, access 150 be formed as only covering lower conductor 160 include
The side of the first side wall 170a, and because of the misalignment of lower conductor 160 and access 150, some parts of second sidewall 170b " do not have
Have by " access 150 " covering ".
However, top surface step of the first side wall 170a of barrier film 170 with the first groove 171 relative to lower conductor 160
The mode of formula decline is formed.On the contrary, the top surface of the second sidewall 170b of barrier film 170 does not include the first groove, but have
At least equal to the top surface height of the top surface of lower conductor 160.This different formation itself is related with unintentionally misalignment, and with
The context-free of the embodiment of present inventive concept.
Thus, architectural difference increase the reason of be that after forming through-hole 197, the first groove 171 can pass through selectivity
Ground etches a part of barrier film 170 exposed by through-hole 197 and is readily formed in through-hole 197.Here, barrier film 170
The first side wall 170a exposed by through-hole 197, but second sidewall 170b is not exposed by through-hole 197.Therefore, the first groove
171 will form relatedly with exposed the first side wall 170a, while will be without forming the in unexposed second sidewall 170b
One groove.As a result, the top surface holding of the second sidewall 170b of barrier film 170 is not etched, and will have at least equal under
The height of the top surface of conductor 160.
Fig. 8 is the sectional view of the semiconductor devices for another embodiment conceived according to the present invention.
With reference to Fig. 8, semiconductor devices 4 partly includes the barrier film 170 for being formed with the first groove 171 as described above
The first side wall 170a.Therefore, the height of the top surface 170c of the first side wall 170a will be less than the top surface 160c of lower conductor 160.
However, it is different from previously shown embodiment, for example, not formed in the first insulating film 180 close to the first groove 171
Second groove (the 181 of Fig. 4).
Fig. 9 is perspective view, shows the semiconductor devices for the another embodiment conceived according to the present invention.Figure 10 is along figure
The sectional view of 9 line D-D interception, Figure 11 are the sectional views intercepted along the line E-E of Fig. 9.
Collective reference Fig. 9, Figure 10 and Figure 11, semiconductor devices 5 include fin transistor 403, the fin transistor 403 packet
Include fin structure F1, gate electrode 447, groove 425 and source/drain region 475/476.
Fin F1 is extended transversely on second direction (Y1).Fin F1 can be a part of substrate 401, and may include
The epitaxial layer grown from substrate 401.The surface of the covering of device isolation film 410 fin F1 being laterally extended.
Gate electrode 447 can be formed as intersecting fin F1 and extending on (X1) (for example) in a first direction.
In the embodiment shown in Fig. 9, gate electrode 447 may include stepped construction, the stepped construction include two or
More metal layer (for example) MG1 and MG2.The first metal layer MG1 adjusts work function, and second metal layer MG2 is filled by the first metal
The space that layer MG1 is formed.The first metal layer MG1 can be by one or more metal shapes including such as TiN, TaN, TiC and TaC
At.Second metal layer MG2 can be by including that such as one or more metals of tungsten (W) and/or aluminium (Al) are formed.Gate electrode 447
It may further include nonmetallic materials, for example, Si or SiGe.Gate electrode 447 can be by for example, replacement technique be formed, still
Those skilled in the art understands the alternative for these specific manufacture possibilities, other embodiment party for present inventive concept
Formula.
Gate insulating film 445 can be formed between fin F1 and gate electrode 447.Gate insulating film 445 can be formed in fin F1's
On the upper part of horizontal side surface and the top surface of fin F1.In addition, gate insulating film 445 can be located at gate electrode 447 and device isolation
Between film 410.Gate insulating film 445 can be formed by the high-k dielectric material with the dielectric constant higher than silicon oxide film.Example
Such as, gate insulating film 445 may include HfO2、ZrO2Or Ta2O5。
Groove 425 can be formed in fin F1 in the two sides of gate electrode 447.Because the side wall of groove 425 is inclined, institute
It can be shaped so that its width increases far from substrate 400 with groove 425.The width of groove 425 can be greater than the width of fin F1
Degree.
Source/drain region 475/476 can be formed in groove 425.Thus, source/drain region 475/476 can be claimed
For the source/drain region of promotion.It is, the top surface of source/drain region 475/476 can be than the first interlayer dielectric
The high level of 455 bottom surface.Source/drain region 475/476 and gate electrode 447 can pass through 451 phase of spacer of offer
Mutually insulation.
Assuming that fin transistor 403 is PMOS transistor, source/drain region 475/476 may include compression material.Example
Such as, compression material can be the material with the lattice constant bigger than silicon (Si), such as SiGe.Compression material can apply
Thus compression improves the mobility of the carrier in channel region to fin F1.
Spacer 451 may include at least one of nitride film and oxynitride film.
Interlayer dielectric 490 can be formed on substrate 400 to cover fin transistor 403,481 and of multiple contacts
482 and barrier film 491 and 492.For example, interlayer dielectric 465 can be by SiN or SiO2It is formed.
Here, each of multiple contacts 481 and 482 can be corresponded to about Fig. 1 to Fig. 8 in lower conductor described above
160 (or first lower conductors 160).Barrier film 491 and 492 can be formed about contact 481 and 482.491 He of barrier film
492 can be respectively corresponding to about Fig. 1 to Fig. 8 in barrier film 170 described above.Access 498 and 499 can be formed in contact
On part 481 and 482.Thus, access 498 and 499 can be corresponded to about Fig. 1 to Fig. 8 in access 150 described above.
Figure 12 is the overall layout chart for showing the semiconductor devices for the another embodiment conceived according to the present invention.
With reference to Figure 12, semiconductor devices 6 includes the first substrate region 520 and second being respectively defined on substrate 510
Substrate regions 530.For example, first substrate region 520 can be what wherein static random access memory (SRAM) unit was formed
Region, while the second substrate region 530 can be and wherein access the region that the logic circuit of sram cell is formed.Alternatively,
One substrate regions 520 can during manufacturing SRAM using and can be relevant logic circuit, and the second substrate region 530
For manufacturing input/output (I/O) circuit.
Lower conductor, barrier film and connecting path can be such as fabricated in about Fig. 1 to Fig. 8 in those described above
In first substrate region 520.It is, the bottom CD of access (is related to the top surface 170c of the contact barrier film side wall of access 150
Part) can be less than corresponding lower conductor top CD (being related to top surface 160c).In addition, because the first side wall of barrier film
Including the first groove, the top surface of the first side wall will be at the low level of the top surface than lower conductor.
On the contrary, the barrier film around the lower conductor being formed in the second substrate region 530 does not need to include this kind of first recessed
Slot and top surface difference in height.It is, the height of the top surface of barrier film can be in the height of the top surface at least equal to lower conductor
At the level of degree.
Figure 13 be may include the embodiment conceived according to the present invention semiconductor devices electronic system block diagram.
With reference to Figure 13, electronic system 1300 may include controller 1310, input/output (I/O) device 1120, memory
Part 1130, interface 1140 and bus 1150.Controller 1110, I/O device 1120, memory device 1130 and/or interface 1140
It can be connected to each other by bus 1150.Bus 1150 can be used for communication data, control and/or address signal.
Controller 1110 may include microprocessor, digital signal processor, microcontroller and be able to carry out with by these
At least one of the logical device for the functionally similar function that device executes.I/O device 1120 may include keypad, keyboard,
Display etc..Memory 1130 can store data and/or instruction.Interface 1140 can transmit data to communication network/from
Communication network receives data.Interface 1140 can be wired or wireless.For example, interface 1140 may include antenna or wired/
Wireless transceiver.Although it is not shown, electronic system 1100 may be used as the operation of the operation for improving controller 1110
Memory, and can also include high-speed DRAM and/or SRAM.The fin transistor for the embodiment conceived according to the present invention can
To be provided in memory device 1130 or can provide the component as controller 1110 or I/O device 1120.
Electronic system 1100 can be applied to personal digital assistant (PDA), portable computer, net book, radio telephone,
Portable phone, digital music player, storage card or the various electronics production that information can be transferred and/or received in wireless environments
Product.
Figure 14 and Figure 15 show may include the embodiment conceived according to the present invention semiconductor devices Department of Electronics
System.Specifically, Figure 14 shows tablet PC, and Figure 15 shows laptop.With about Fig. 1 to Fig. 6 it is described above that
A little at least one similar semiconductor devices can be incorporated into tablet PC, laptop etc..
Hereinafter, now collective reference Figure 16 to Figure 27 and Fig. 1 to Fig. 5 description is used to conceive according to the present invention
One example of the manufacturing method of the semiconductor devices of certain embodiments.
More specifically, Figure 16 to Figure 27 shows the manufacturer of the semiconductor devices for the embodiment conceived according to the present invention
The various intermediate process steps of method.Figure 17, Figure 22, Figure 24 and Figure 26 are the sectional views intercepted along the line A-A of Figure 16.Figure 18, figure
23, Figure 25 and Figure 27 is the sectional view intercepted along the line B-B of Figure 16.
With reference to Figure 16, Figure 17 and Figure 18, lower conductor 160 and barrier film 170 are formed on substrate.The first lower conductor of exposure
160 and the first insulating film 180 of top surface of barrier film 170 formed around the combinations of the two elements.
That is, for example, lower conductor 160 can be formed by (for example) aluminium (Al) or tungsten (W).Lower conductor 160 includes the
One side wall 160a and second sidewall 160b.Barrier film 170 includes the first side wall 170a, second sidewall 170b and bottom section
170d.The first side wall 170a is formed on the first side wall 160a of lower conductor 160, and second sidewall 170b is formed in lower conductor 160
Second sidewall 160b on.Bottom section 170d is formed on the bottom surface of lower conductor 160.For example, barrier film 170 can be by all
As one or more materials of Ti and/or TiN are formed.In some embodiments, the layer of Ti/TiN can be used in barrier film 170
Folded film is implemented.For example, the first insulating film 180 can be by SiO2, SiN, SiON, SiCN and/or low k dielectric material formed.
Then, the second insulating film 190 and third insulating film 195 can be formed in lower conductor 160, barrier film 170 and first
On insulating film 180.Second insulating film 190 can be formed by SiCN, for example, third insulating film 195 can be by low k dielectric material
It is formed.
Then, etch stop film 303 and including first opening 310, (for example) 320 and 330 hard mask pattern 301 formation
On third insulating film 195.
That is, hard mask pattern 301 may include the metal hard mask pattern 305 and insulation hard mask of sequence stacking
Pattern 307.For example, metal hard mask pattern 305 may include at least one of TiN, Ta and TaN, insulate hard mask pattern
307 may include SiO2, SiN, SiON and SiCN at least one.
Metal hard mask pattern 305 has high etch-selectivity.For example, metal hard mask pattern 305 is to third insulating film
The etching selectivity of 195 (that is, low k dielectric materials) can be 1:20 or higher.Using with such high etching
The metal hard mask pattern 305 of selectivity allows to accurately keep/adjust the width of through-hole (for example, 197 of Fig. 3).
When through-hole 197 is using the formation of metal hard mask pattern 305, metallicity polymer can produce.Here, insulation is covered firmly
Mould pattern 307 can reduce the generation of metallicity polymer.If metal hard mask pattern 305 is used alone without the use of exhausted
Edge hard mask pattern 307, metallicity polymer are generated from metal hard mask pattern 305, are then deposited over around through-hole 197,
And it is hereafter extremely difficult to remove deposited metallicity polymer.
In addition, reducing the metallicity polymer fallen on the bottom of through-hole 197 using insulation hard mask pattern 307
Thus amount improves the bottom profile of through-hole 197.
During insulation hard mask pattern 307 can be formed as being enough the step of forming local groove (see Figure 22 and Figure 23)
The thickness being completely removed.For example, insulation hard mask pattern 307 can be formed asExtremelyBetween
Thickness, metal hard mask pattern 305 can be formed asExtremelyIn the range of thickness, but structure of the present invention
The embodiment of think of is without being limited thereto.The thickness of metal hard mask pattern 305 can be reduced using insulation hard mask pattern 307.
Referring now to Figure 19, Figure 20 and Figure 21, the mask pattern 350 including the second opening 340 is formed in hard mask pattern
On 301.Here, mask pattern 350 can be such as photoresist pattern.
Particularly, as shown in figure 20, the width " W6 " of the first opening 320 can be less than the width " W7 " of the second opening 340.
Then, through-hole (local through-hole) 197a can use mask pattern 350 and hard mask pattern 301 is formed in second absolutely
In velum 195.It is, local through-hole 197a does not expose the top surface of lower conductor 160.As shown in figure 20, local through-hole 197a
The top surface of the second insulating film 190 can not even be exposed.For example, part through-hole 197a can be formed by dry ecthing.In shape
When at through-hole 197a, a part insulation hard mask pattern 307 can be also etched.As indicated, as a result, insulation hard mask pattern 307
Can have chamfering or round.
With reference to Figure 22 and Figure 23, mask pattern 350 is removed using cineration technics.
Then, a part of second insulating film 195 is etched using hard mask pattern 301, thus exposes lower conductor 160 and resistance
Keep off the top surface of film 170.Here, local groove 196a can be formed in the second insulating film 195 while expose 160 He of lower conductor
Barrier film 170.For example, part groove 196a can be formed by dry ecthing.When forming part groove 196a, insulate hard mask
Pattern 307 can be possible to determine when the sample has been completely etched, and metal hard mask pattern 305 can be partially etched.As indicated, as a result, metallic hard
Mask pattern 305 can have chamfering or round.
With reference to Figure 24 and Figure 25, a part for the barrier film 170 being exposed is etched now, and barrier film 170 is consequently formed
The first groove 171.
That is, the first groove 171 can be formed for example, by dry ecthing, because if wet etching is used to form
First groove 171, then etchant solutions may penetrate the first side wall 170a and second sidewall 170b and the part of barrier film 170
Ground fully removes these first areas.This will make the deteriorated reliability of gained semiconductor devices.Therefore, it should use dry corrosion
It carves, to only remove the desired upper part of the first side wall 170a and second sidewall 170b.
In some embodiments, the first groove 171 is formed intoExtremelyDepth, and specific at one
Be formed as about in embodimentDepth.
Barrier film 170 and metal hard mask pattern 305 may include identical material.For example, barrier film 170 and metallic hard
Mask pattern 305 may include TiN.As indicated, metal hard mask pattern 305 can be complete when forming the first groove 171
Etching, but the aspect of present inventive concept is without being limited thereto.
With reference to Figure 26 and Figure 27, the part close to the first groove 171 of the first insulating film 180 and/or the second insulating film 190
The second groove 181 can be removed to form.
Here, when forming the second groove 181, groove 196 is completed.It is, when forming the second groove 181, part
Groove 196a is formed as the groove 196 completed.Here, when completing groove 196, etch stop film 303 can obtain chamfering or
The edge shape of sphering.
Now, referring back to Fig. 1 to Fig. 5, conductive material is deposited as being fully filled groove 196 and through-hole 197.Example
Such as, conductive material can be copper, and but not limited to this.During the depositing operation, conductive material will fill 171 He of the first groove
Second groove 181.
Then, the first upper conductor 120, the second upper conductor 110, third upper conductor 130 and access 150 can be used traditionally
The flatening process (for example, CMP process) of understanding is completed.The flatening process can completely remove etch stop film 303 simultaneously
Partly remove third insulating film 195.
Pass through example in the manufacturing method of the semiconductor devices for the certain embodiments conceived according to the present invention to be retouched
When stating, it will be appreciated by those skilled in the art that these other manufacturing methods for illustrating how that semiconductor devices can be extended to.
Although present inventive concept is especially shown and described by reference to its illustrative embodiments, this field it is general
It is logical the skilled person will understand that, various changes can be carried out in form and detail without departing from the scope of the claims.Therefore, in advance
Phase present embodiment is all understood to illustrative rather than restrictive in all respects, with reference to claim rather than foregoing description
To indicate the range of present inventive concept.
This application claims enjoy the preferred of on August 28th, 2012 South Korea patent application No.10-2012-0094478 submitted
Power, content are incorporated herein by reference.
Claims (28)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120094478A KR101994237B1 (en) | 2012-08-28 | 2012-08-28 | Semiconductor device and fabricating method thereof |
| KR10-2012-0094478 | 2012-08-28 | ||
| CN201310378594.5A CN103681550B (en) | 2012-08-28 | 2013-08-27 | Semiconductor device and manufacturing method |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310378594.5A Division CN103681550B (en) | 2012-08-28 | 2013-08-27 | Semiconductor device and manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109166837A true CN109166837A (en) | 2019-01-08 |
| CN109166837B CN109166837B (en) | 2023-01-24 |
Family
ID=50186354
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810933697.6A Active CN109166837B (en) | 2012-08-28 | 2013-08-27 | Semiconductor device and manufacturing method |
| CN201810933529.7A Active CN109166836B (en) | 2012-08-28 | 2013-08-27 | Semiconductor device and method of manufacture |
| CN201310378594.5A Active CN103681550B (en) | 2012-08-28 | 2013-08-27 | Semiconductor device and manufacturing method |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810933529.7A Active CN109166836B (en) | 2012-08-28 | 2013-08-27 | Semiconductor device and method of manufacture |
| CN201310378594.5A Active CN103681550B (en) | 2012-08-28 | 2013-08-27 | Semiconductor device and manufacturing method |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9087844B2 (en) |
| KR (1) | KR101994237B1 (en) |
| CN (3) | CN109166837B (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9059166B2 (en) * | 2013-05-09 | 2015-06-16 | International Business Machines Corporation | Interconnect with hybrid metallization |
| US9236397B2 (en) * | 2014-02-04 | 2016-01-12 | Globalfoundries Inc. | FinFET device containing a composite spacer structure |
| US9583485B2 (en) | 2015-05-15 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field effect transistor (FinFET) device structure with uneven gate structure and method for forming the same |
| US9536964B2 (en) * | 2015-05-29 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming via profile of interconnect structure of semiconductor device structure |
| US9837309B2 (en) | 2015-11-19 | 2017-12-05 | International Business Machines Corporation | Semiconductor via structure with lower electrical resistance |
| US10319625B2 (en) | 2015-12-22 | 2019-06-11 | Intel Corporation | Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures |
| US10707331B2 (en) * | 2017-04-28 | 2020-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device with a reduced width |
| TWI642333B (en) | 2017-10-25 | 2018-11-21 | 欣興電子股份有限公司 | Circuit board and manufacturing method thereof |
| TWI642334B (en) | 2017-10-25 | 2018-11-21 | 欣興電子股份有限公司 | Circuit board and manufacturing method thereof |
| KR102674584B1 (en) * | 2019-01-04 | 2024-06-11 | 삼성전자주식회사 | Semiconductor device |
| CN112201746B (en) | 2019-07-08 | 2024-11-19 | 联华电子股份有限公司 | Semiconductor element and method for manufacturing the same |
| KR102770334B1 (en) * | 2019-09-25 | 2025-02-18 | 삼성전자주식회사 | Semiconductor device and method for fabricating thereof |
| US11177163B2 (en) * | 2020-03-17 | 2021-11-16 | International Business Machines Corporation | Top via structure with enlarged contact area with upper metallization level |
| US12412833B2 (en) | 2021-06-24 | 2025-09-09 | International Business Machines Corporation | TopVia interconnect with enlarged via top |
| KR102907018B1 (en) * | 2021-08-19 | 2026-01-05 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
| US11923246B2 (en) | 2021-09-15 | 2024-03-05 | International Business Machines Corporation | Via CD controllable top via structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1527375A (en) * | 2003-02-11 | 2004-09-08 | �����ɷ� | Robust through-hole structure and method |
| US20050082089A1 (en) * | 2003-10-18 | 2005-04-21 | Stephan Grunow | Stacked interconnect structure between copper lines of a semiconductor circuit |
| CN101236918A (en) * | 2007-01-31 | 2008-08-06 | 富士通株式会社 | Method for manufacturing semiconductor device and semiconductor device |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001176872A (en) | 1999-12-20 | 2001-06-29 | Sanyo Electric Co Ltd | Method for manufacturing semiconductor device |
| KR20010086522A (en) | 2000-03-02 | 2001-09-13 | 윤종용 | The method of forming metal lines in semiconductor memory devices |
| KR100379530B1 (en) | 2000-12-29 | 2003-04-10 | 주식회사 하이닉스반도체 | method for forming dual damascene of semiconductor device |
| KR20030058261A (en) * | 2001-12-31 | 2003-07-07 | 주식회사 하이닉스반도체 | Method for forming metal wire using dual damascene process |
| JP2004031866A (en) | 2002-06-28 | 2004-01-29 | Trecenti Technologies Inc | Semiconductor integrated circuit device |
| US7105894B2 (en) * | 2003-02-27 | 2006-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contacts to semiconductor fin devices |
| JP2005072384A (en) * | 2003-08-26 | 2005-03-17 | Matsushita Electric Ind Co Ltd | Manufacturing method of electronic device |
| JP4266901B2 (en) * | 2003-09-30 | 2009-05-27 | 三洋電機株式会社 | Semiconductor device and manufacturing method thereof |
| KR100667905B1 (en) | 2005-07-06 | 2007-01-11 | 매그나칩 반도체 유한회사 | Copper metal wiring formation method of semiconductor device |
| KR100657964B1 (en) * | 2005-07-22 | 2006-12-14 | 삼성전자주식회사 | Random access memory and semiconductor device having a single gate electrode corresponding to a pair of pin-type channel regions |
| JP2007053133A (en) | 2005-08-15 | 2007-03-01 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| US7800228B2 (en) * | 2006-05-17 | 2010-09-21 | International Business Machines Corporation | Reliable via contact interconnect structure |
| JP5162869B2 (en) * | 2006-09-20 | 2013-03-13 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| US7452758B2 (en) * | 2007-03-14 | 2008-11-18 | International Business Machines Corporation | Process for making FinFET device with body contact and buried oxide junction isolation |
| KR20080091990A (en) | 2007-04-10 | 2008-10-15 | 삼성전자주식회사 | Method for forming wiring structure of semiconductor device and wiring structure manufactured thereby |
| JP2009158657A (en) * | 2007-12-26 | 2009-07-16 | Renesas Technology Corp | Wiring structure and wiring method thereof |
| CN102074582B (en) * | 2009-11-20 | 2013-06-12 | 台湾积体电路制造股份有限公司 | Integrated circuit structure and method of forming the same |
| JP2011114049A (en) * | 2009-11-25 | 2011-06-09 | Renesas Electronics Corp | Semiconductor device |
| US8614484B2 (en) * | 2009-12-24 | 2013-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage device with partial silicon germanium epi source/drain |
| JP2012009617A (en) | 2010-06-24 | 2012-01-12 | Renesas Electronics Corp | Semiconductor device manufacturing method, copper alloy for wiring, and semiconductor device |
-
2012
- 2012-08-28 KR KR1020120094478A patent/KR101994237B1/en active Active
-
2013
- 2013-06-28 US US13/930,187 patent/US9087844B2/en active Active
- 2013-08-27 CN CN201810933697.6A patent/CN109166837B/en active Active
- 2013-08-27 CN CN201810933529.7A patent/CN109166836B/en active Active
- 2013-08-27 CN CN201310378594.5A patent/CN103681550B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1527375A (en) * | 2003-02-11 | 2004-09-08 | �����ɷ� | Robust through-hole structure and method |
| US20050082089A1 (en) * | 2003-10-18 | 2005-04-21 | Stephan Grunow | Stacked interconnect structure between copper lines of a semiconductor circuit |
| CN101236918A (en) * | 2007-01-31 | 2008-08-06 | 富士通株式会社 | Method for manufacturing semiconductor device and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101994237B1 (en) | 2019-06-28 |
| US9087844B2 (en) | 2015-07-21 |
| CN109166837B (en) | 2023-01-24 |
| US20140061917A1 (en) | 2014-03-06 |
| CN103681550A (en) | 2014-03-26 |
| CN103681550B (en) | 2018-09-14 |
| CN109166836A (en) | 2019-01-08 |
| KR20140028376A (en) | 2014-03-10 |
| CN109166836B (en) | 2022-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109166837A (en) | Semiconductor devices and manufacturing method | |
| TWI808100B (en) | Heterogeneous metal line compositions for advanced integrated circuit structure fabrication | |
| TWI772378B (en) | Integrated circuit device and method of manufacturing the same | |
| CN108133934B (en) | Semiconductor device with a plurality of semiconductor chips | |
| KR102480219B1 (en) | Semiconductor devices and methods of manufacturing semiconductor devices | |
| KR20240166600A (en) | Staircase structure in three-dimensional memory device and method for forming the same | |
| TWI686880B (en) | Semiconductor device and methods of fabrication thereof | |
| US10186485B2 (en) | Planarized interlayer dielectric with air gap isolation | |
| TW202129910A (en) | Integrated circuit device | |
| KR20130134139A (en) | Semiconductor device and method for using the same | |
| TW202147576A (en) | Contact pad structure of three-dimensional memory device and method of forming the same | |
| KR20200022147A (en) | Semiconducotr device and method of manufacturing the same | |
| TW202018953A (en) | Finfet having insulating layers between gate and source/drain contacts | |
| KR20120048791A (en) | Method of manufacturing a vertical type semiconductor device | |
| TW202301677A (en) | Inverse taper via to self-aligned gate contact | |
| US20200203156A1 (en) | Stack viabar structures | |
| US20230136674A1 (en) | Self-aligned double patterning (sadp) integration with wide line spacing | |
| US20240128313A1 (en) | Semiconductor structure and methods for manufacturing the same | |
| JP2002050702A (en) | Semiconductor device | |
| US6776622B2 (en) | Conductive contact structure and process for producing the same | |
| TWI813426B (en) | Semiconductor structure and methods for manufacturing the same | |
| CN115692416B (en) | Semiconductor structure and method for forming the same | |
| JP2003068742A (en) | Semiconductor device and method of manufacturing the same | |
| US20240120369A1 (en) | High density trench capacitor | |
| CN104658977B (en) | Method for forming semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |