CN109166803A - A kind of transistor and preparation method thereof - Google Patents
A kind of transistor and preparation method thereof Download PDFInfo
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- CN109166803A CN109166803A CN201810927822.2A CN201810927822A CN109166803A CN 109166803 A CN109166803 A CN 109166803A CN 201810927822 A CN201810927822 A CN 201810927822A CN 109166803 A CN109166803 A CN 109166803A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to technical field of semiconductors, more particularly to a kind of novel semi-conductor transistor and preparation method thereof, it include: substrate by the transistor that this method makes, the substrate is equipped with a source region, the channel region of one drain region and the connection source region and drain region, one grid, the gate structure is vertical structure, transistor is when opening, the electronics of source electrode drains along the two sides horizontal direction of internal vertical polysilicon to be flowed, to realize that the single plane channel for being located at device surface, which is transferred to trenched side-wall, forms a plurality of conducting channel, transistor provided by the invention has lower conducting resistance by special gate structure, higher current driving ability.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of novel semi-conductor transistor and preparation method thereof.
Background technique
Metal (metal)-oxide (oxide)-semiconductor (semiconductor) field effect transistor (metal-oxide-semiconductor) is
A kind of field-effect transistor that can be widely used in analog circuit and digital circuit, wherein according to its ' channel ' work carrier
Polarity is different, can be divided into " N-type " and " p-type " two types.Its working principle (is enhanced with N-channel enhancement mode MOSFET
For type N-MOS pipe) be controlled using grid voltage " charge inducing " number, with change formed by these " charge inducings "
Conducting channel situation, then achieve the purpose that control drain current.When grid voltage changes, the charge of induction in channel
Amount also changes, and the width of conducting channel also becomes therewith, thus drain current changes, traditional work with the variation of grid voltage
The silicon face of skill only has single layer channel, and transistor carrier flowing is limited to silicon face, thus the conductive capability quilt of transistor
Structure is limited.
Summary of the invention
In view of the above circumstances, the present invention to be solved its technical problem the following technical solution is employed to realize.
In a first aspect, the embodiment of the present invention provides a kind of production method of transistor, comprising: semiconductor substrate, described
Well region is formed in semiconductor substrate, forms several grooves in the well region, over the substrate surface and the groove
Inner wall forms gate oxide, and forming source region and drain region, the source region and drain region in the groove two sides has one side to be located at institute
Trenched side-wall is stated, another side is located at the upper surface of the well region, carries out polysilicon in the groove and fills to form the grid
Structure.
Further, groove is formed in the well region to specifically include, formed on the well region by chemical wet etching several
Groove of the item perpendicular to the semiconductor substrate upper surface.
Further, it is specifically included before forming the gate oxide: wedge angle processing is carried out to the channel bottom；In ditch
Sacrificial oxide layer is formed inside slot and removes sacrificial oxide layer；Ion implanting, which is carried out, in channel bottom forms implanted layer；In groove
Field oxide is formed on bottom.
Further, channel bottom carry out ion implanting formed implanted layer specifically include, the channel bottom carry out from
Son injection, the implanted layer is for preventing carrier from circulating through channel bottom.
Further, specifically included before forming the source region and drain region, form body area in well region side, the body area with
The source region is located at the same side of the groove.
Further, it forms the source region and drain region specifically includes, the source region and drain region are passed through and table on the well region
Under the action of face is at the injection ion beam of angle, the source region and drain region form heavy doping N+ layers close to the position on well region surface,
The sidewall locations of the source region and drain region close to groove side form lightly-doped layer N- layers, and the source region and drain region are formed as " 7 "
The section shape of font.
Second aspect, the embodiment of the present invention also provide a kind of transistor, comprising: semiconductor substrate, the semiconductor substrate
On several grooves being formed with well region and be formed in the well region, wall forms gate oxide in the groove, in institute
The two sides for stating groove are respectively formed active area and drain region, and the source region and drain region have one side to be located at the trenched side-wall, separately
One side is located at the upper surface of the well region, and polysilicon is filled in the groove to form gate structure.
Further, the groove is formed by chemical wet etching, and the groove vertical is in table in the semiconductor substrate
Face.
Further, the semiconductor further includes the body area for being formed in the well region side, the body area and the source region
Positioned at the same side of the groove.
Further, the groove carries out polysilicon filling, the polysilicon filling by Low Pressure Chemical Vapor Deposition
Afterwards using gate oxide as barrier layer, only retain the polysilicon of trench interiors, etching removes the polysilicon in other regions.
The technical solution of the embodiment of the present invention has the advantage that on the basis of the silicon face single layer channel of traditional handicraft
On, by changing the channel and gate structure of transistor, gate structure side forms conducting channel, so that between source and drain
All-directional conductive structure is formed, the significant increase conductive capability of transistor reduces the conducting resistance of transistor, great sexual valence
Compare advantage.
Detailed description of the invention
The attached drawing for constituting a part of the invention is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, do not constitute improper limitations of the present invention.
In the accompanying drawings:
Figure 1A is overall structure top view described in the embodiment of the present invention；
Figure 1B is the sectional view splitted along the A-A ' line of Figure 1A；
Fig. 1 C is the sectional view splitted along the B-B ' line of Figure 1A；
Fig. 2 is substrate and well region structural schematic diagram described in the embodiment of the present invention；
Fig. 3 A is groove top view described in the embodiment of the present invention；
Fig. 3 B is the sectional view splitted along the A-A ' line of Fig. 3 A；
Fig. 4 is the structural schematic diagram of the processing of wedge angle described in the embodiment of the present invention；
Fig. 5 is the structural schematic diagram of ion implanting described in the embodiment of the present invention；
Fig. 6 is the structural schematic diagram of field oxide described in the embodiment of the present invention；
Fig. 7 is the structural schematic diagram of gate oxide described in the embodiment of the present invention；
Fig. 8 A is body plot structure schematic diagram described in the embodiment of the present invention；
Fig. 8 B is the sectional view splitted along the A-A ' line of Fig. 8 A；
Fig. 9 A is source region and drain structure schematic diagram described in the embodiment of the present invention；
Fig. 9 B is the sectional view splitted along the A-A ' line of Fig. 9 A；
Figure 10 is the structural schematic diagram that polysilicon is filled described in the embodiment of the present invention；
Figure 11 is gate structure schematic diagram described in the embodiment of the present invention.
Specific embodiment
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Those of ordinary skill's every other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
Usually using two complicated manufacture craft manufacturing semiconductor devices: front end manufacture and back-end manufacturing.Front end manufacture
It include that multiple small pieces are formed on the surface of semiconductor wafer.Each small pieces include active and passive electronic member on the wafer
Part, described active and passive electronic components are electrically connected to form functional circuitry, active electron component, such as transistor and two poles
Pipe has the ability of control electric current flowing.Passive electronic components, such as capacitor, inductor, resistor and transformer.It generates
Relationship between voltage and current necessary to execution circuit function.
By a series of processing step, passive and active element, the processing step are formed on the surface of semiconductor
Including doping, deposition, photoetching, etching and planarization.Doping passes through the technology of such as ion implanting or thermal diffusion, adds impurities to
In semiconductor material.Doping process changes the conductivity of the semiconductor material in active device, and semiconductor material is converted to absolutely
Edge body, conductor, or dynamically change in response to electric field or base current the conductivity of semiconductor material.
Active and passive element is formed by the layer of the material with different electrical properties.It can be by partly by deposited material
A variety of deposition techniques that the type of material is determined form these layers.For example, film deposition may include chemical vapor deposition, physics
Vapor deposition, electrolysis plating and plated by electroless plating technique.Usually pattern each layer with formed active component, passive element or
The part of electrical connection between element.
Below in conjunction with Fig. 2-Figure 11, the production method for providing a kind of transistor to the embodiment of the present invention is described in detail,
This method comprises:
S01: semiconductor substrate 10 is provided；
S02: well region 20 is formed in the semiconductor substrate 10；
S03: several grooves 30 are formed in the well region 20；
S04: gate oxide 60 is formed in 10 upper surface of substrate and 30 inner wall of the groove；
S05: source region 80 and drain region 82 are formed in 30 two sides of groove, there is one side position in the source region 80 and drain region 82
In 30 side wall of groove, another side is located at the upper surface of the well region 20；
S06: polysilicon filling 90 is carried out in the groove 30 and forms the gate structure 91.
Channel and gate structure of the technical solution of the embodiment of the present invention by change transistor, gate structure side shape
At conducting channel, so that forming all-directional conductive structure between source and drain, the significant increase conductive capability of transistor is reduced
The conducting resistance of transistor, great superiority of effectiveness.
With reference to the accompanying drawings, the specific method of the above-mentioned formation transistor is elaborated.
As shown in Fig. 2, step S01: semiconductor substrate 10 is provided, specifically, substrate can be the following material being previously mentioned
At least one of: silicon, germanium, GaAs, indium phosphide or silicon carbide etc., in addition, can be defined in semiconductor substrate active
Area.To put it more simply, semiconductor substrate is only indicated with a blank herein, carrier of the substrate as the transistor, mainly
Play the role of structural support, in the present embodiment, the material of the substrate is preferably silicon substrate, and silicon is most common, cheap
And the semiconductor material that performance is stable.
As shown in Fig. 2, step S02: well region 20 is formed in the semiconductor substrate 10, specifically, the semiconductor serves as a contrast
Photoresist is covered in primary coat, ion implantation technology is carried out to the semiconductor using photoresist as masking film, by injecting N-type impurity shape
At N well region.In some embodiments, semiconductor substrate by thermal oxidation technology formed silicon oxide film, using silicon oxide film as
It shelters film and ion implantation technology or diffusion technique is carried out to the semiconductor, N well region is diffuseed to form by N-type impurity, lead to
Cross the p-well region that diffuses to form of p type impurity, the well region is horizontally formed under the surface of substrate, the p type impurity be boron, aluminium,
Gallium, indium etc., the N-type impurity are phosphorus, arsenic, antimony, bismuth etc..It in other embodiments, can not also be by way of exposure mask, directly
It connects and well region is formed to the ion implanting mode that the semiconductor substrate being lightly doped is focused.
As shown in figs.3 a and 3b, step S03: several grooves 30 are formed in the well region 20, specifically, on well region
30 carry out coating photoresist 100, and then chemical wet etching forms several grooves 30, it is possible to understand that, it, need to by using photoetching
Pattern to be formed is transferred on photoresist from photomask, uses the part through light of solvent removal photoetching agent pattern, exposure
The part to be patterned of cutting optimal, removes the residue of photoresist, leaves patterned layer.In the present embodiment, ditch
The depth of slot is less than well region junction depth, and groove width is the minimum feature that technique allows, and is spaced about two between several grooves
The width of times groove.
As described above, using quick peeler, by one layer of photosensitive material of semiconductor surface spin coating, referred to as light
Photoresist is toasted, to drive away the solvent in photoresist after taking down semiconductor from whirler between 80 DEG C -150 DEG C of temperature
And hardened photoresist, reinforce the adhesive force of photoresist and chip, light source is then used, by a figuratum mask plate to chip
It is exposed, the chip being covered by photoresist is chemically reacted the kenel according to photoresist in the region of its exposure,
And the photoetching xanthan polymer being exposed in light will do it decomposition reaction, in subsequent development, the region being exposed will
Dissolution removal forms photoresist window, and the region photoresist without exposure still retains.
As shown in Figure 4-Figure 7, step S04: gate oxidation is formed in 10 upper surface of substrate and 30 inner wall of the groove
It is specifically included before layer 60, round and smooth groove 31 is formed by wedge angle processing to 30 bottom of groove；It is formed inside groove 30
Sacrificial oxide layer simultaneously removes sacrificial oxide layer；Ion implanting, which is carried out, in channel bottom forms implanted layer 40；It is formed in channel bottom
Field oxide 50.It is appreciated that by surface and the trench wall form grid oxygen over the substrate after above step
Change layer 60.
Wherein, wedge angle processing is carried out to 30 bottom of groove and forms round and smooth groove 31, specifically, passing through plasma
Isotropic etching can eliminate bottom wedge angle and form the round and smooth shape in bottom, avoid electric field concentration effect, promote transistor
Pressure resistance and reliability, etching gas are usually chlorine-based gas.It should be understood that wedge angle is formed on groove bottom after over etching, hold
Easily form internal field's concentration effect.
Wherein, it is formed inside round and smooth groove 31 and sacrificial oxide layer and removes sacrificial oxide layer, it, can be with after silica is formed
Silica as sacrificial layer is removed using the method for wet etching or dry etching, present embodiment preferably passes through wet etching
Remove the silica of sacrificial layer.More specifically, usual sacrificial layer oxidizing temperature is between 800 DEG C -1000 DEG C, the thickness of sacrificial layer
For degree between 100A (Angstrom, angstrom) -1000A (Angstrom, angstrom), the method for sacrificial layer removal is that hydrofluoric acid wet process is rotten
Erosion, strips all surface silicon oxide layer.Pass through formation sacrificial oxide layer and removes the etching that sacrificial oxide layer eliminates trench interiors
Damage, makes trench interiors flat-satin, effectively promotes the q&r of subsequent gate oxide.
Wherein, ion implanting is carried out in round and smooth 31 bottom of groove and form implanted layer 40, specifically, semiconductor coats photoetching
Glue carries out ion implantation technology to the semiconductor using photoresist as masking film, and more specifically, injection element is boron ion,
Dosage between 1E13-1E14/CM2, energy between 100-300Kev (kilo electron volt, kilo electron volt),
Ion beam current is vertical with silicon upper surface, then only bottom is not injected by injection boron ion, side wall, by channel bottom inject from
Son can prevent carrier from circulating from channel bottom, prevent base semiconductor from leaking electricity.
Wherein, field oxide 50 is formed in round and smooth 31 bottom of groove, specifically, carrying out oxygen element injection to silicon trench bottom
And rapid thermal annealing forms field oxide, channel bottom forms the field oxide that two sides are thin, bottom is thick, more specifically, oxygen element
Implantation Energy is between 100Kev-300kev, and implantation concentration is between 1E17-1E19/CM2.Annealing temperature is at 1000 DEG C -1100
Between DEG C, for annealing time between 15s (second, second) -60s, on the one hand annealing can repair lattice damage, on the other hand may be used
To activate the oxygen element of injection to be allowed to react to form silica with the silicon of beneath trenches, after annealing, channel bottom is formed
Two sides are thin, and the oxide layer of bottom thickness, bottom oxidization layer thickness is usually 3 times of subsequent gate oxide or more (usually in 300A-
Between 3000A), bottom thickness oxygen can not only weaken the electric field between polysilicon and bottom well region, promote device resistance to pressure energy, also
Bottom conductive channel can be promoted and open threshold value, prevent channel bottom from leaking electricity.
Wherein, gate oxide 60, tool are formed in 20 upper surface of the substrate 10 and well region, 31 bottom surface of round and smooth groove and side wall
Body, gate oxide is formed to after semiconductor removal photoresist and by dry-oxygen oxidation, wherein method for oxidation includes dry oxygen oxygen
Change, steam oxidation, mixes oxychloride, Oxidation Process By Hydrogen Oxygen Synthesis etc. at wet-oxygen oxidation, in the present embodiment preferred dry-oxygen oxidation, in oxygen
During change, it is passed directly into oxygen and is aoxidized, by the gate oxide compact structure of dry-oxygen oxidation generation, uniformity and repetition
The advantages that property is good, strong to impurity screening ability, good with the adhesion of photoresist.The thickness of gate oxide depends on the threshold of transistor
Threshold voltage and grid pressure resistance demand, it is preferable that can be between 50A-500A.
It as shown in figs. 8 a and 8b, further include in well region side shape before executing step S05 and forming source region 80 and drain region 82
Adult area 70, the body area 70 is located at the same side of the round and smooth groove 31 with the source region 80, specifically, passing through silicon in well region
Grid self-aligned technology carries out the photoetching and injection of body area P+ floor, and more specifically, carrying out coating photoresist to substrate, then photoetching is carved
The area Shi Chuti, for body area etching in the side of source region, the area Zai Duiti carries out ion implantation technology, and the impurity of injection is beryllium element, note
Enter energy between 15-60Kev, implantation dosage is between 1E15-1E16/CM2, it is preferable that body section length and source region length one
It causes, width can be between 0.2-1um (micron), and body area P+ floor forms body area in well region side, for avoiding latch-up.
As illustrated in figures 9a and 9b, step S05: 80 source region and 82 drain region N+ layers are formed, specifically, the source region and leakage
Area pass through with the well region upper surface at the injection ion beam of angle under the action of, position shape of the source region close to well region surface
At heavy doping N+ layer 80, the drain region forms heavy doping N+ layer 82 close to the position on well region surface, and the source region is close to groove one
N- layer 81 is lightly doped in the sidewall locations formation of side, and N- layer 83 is lightly doped in sidewall locations formation of the drain region close to groove side,
The section shape of the source region and drain region N+ layers and N- layers formation " 7 " font, more specifically, N+ layers of injection ion is usually arsenic
Or P elements, Implantation Energy is between 15-50kev, and implantation concentration is usually between 1E15-1E16/CM2, and N+ layers with P+ layer
Between distance usually between 0.5-1um, N+ layers of covering part well region groove, the size of covering usually between 0.1-0.2um, and
The distance between both ends N+ is approximately equal to channel length.
As described above, injection mode be side wall injection, specifically, make upper semiconductor with inject ion beam be in
70 ° -83 ° or so of angle β carries out the injection of four N+, and every injection is completed once, is carried out to semiconductor to the same direction
90 ° of rotation not only enables N+ photoetching window be efficiently injected into impurity, but also also can be miscellaneous by injection close to the side wall of source and drain side
Matter, but far below the impurity concentration in N+ layer, its side wall close to source and drain side can play N- is lightly doped the concentration of impurity in turn
The effect of layer, the sidewall locations formation of the source region and drain region close to groove side are lightly doped N- layers, the source region side and leakage
The N+ floor and N- floor of area side form the section shape of " 7 " font.
As shown in Figure 10 and Figure 11, step S06: polysilicon filling 90 is carried out in the round and smooth groove 31 and forms the grid
Structure 91, specifically, round and smooth groove 31 be filled up completely by polysilicon after again using silicon face gate oxide 60 as barrier layer, removal
The polysilicon in other regions only retains the polysilicon of trench interiors as gate structure 91, specifically, its filling mode includes normal
Pressure chemical vapor deposition method, Low Pressure Chemical Vapor Deposition, plasma auxiliary chemical vapor deposition method etc., in present embodiment
In, it is therefore preferable to Low Pressure Chemical Vapor Deposition, the polysilicon purity is high of doping, uniformity are strong.More specifically, polysilicon
Thickness is substantially equal to the width of groove, and after polycrystalline silicon growth, groove is completely filled, then using upper surface of substrate gate oxide as
Barrier layer carries out chemically mechanical polishing to polysilicon or dry back is carved, retains the polysilicon of trench interiors, remove other regions
Polysilicon.
Further, to semiconductor carry out source and drain heat treatment, specifically, heat treatment temperature usually 850 ° -1050 ° it
Between, the time usually within a hour, for activating the impurity of source and drain and body area.Subsequent step is consistent with common process,
Thin-film deposition, chemical wet etching contact hole grow metal, chemical wet etching, metal interconnection, element manufacturing completion.
As shown in Figure 1A, 1B and 1C, the embodiment of the present invention provides a kind of transistor, comprising: semiconductor substrate 10, described half
Several grooves 30 for being formed with well region 20 on conductor substrate 10 and being formed in the well region 20, in 30 inner wall of groove
Gate oxide 60 is formed, is respectively formed active area 80 and drain region 82, the source region 80 and drain region 82 in the two sides of the groove 30
There is one side to be located at the trenched side-wall, another side is located at the upper surface of the well region, is filled with polycrystalline in the groove
Silicon 90 is to form gate structure 91.
Planar gate structure is changed into vertical structure by the gate structure of change transistor by the embodiment of the present invention, so that
The side of vertical gate structure forms conducting channel in transistor body, so that forming all-directional conductive structure between source and drain.
Further, semiconductor substrate 10, including base semiconductor material, such as silicon, germanium, GaAs, indium phosphide or
Silicon carbide is used for structural support.For N-MOS device, substrate initial dopant has p-type semiconductor material, such as boron, aluminium or gallium
Impurity, with the dosage of 1E13-1E14/CM2 with the ion implanting of hundreds of Kev, deposits p to form well region under substrate surface
Type dopant.Other injections can be deposited with dosage appropriate and energy level.Exposure mask is not needed for ion implanting.Well region can
To reduce punchthrough effect, drains for clamper to the breakdown voltage of source electrode, reduce reverse recovery time, and can be generally improved
The robustness of transistor.
Further, well region 20 is formed in semiconductor substrate 10, transistor can be n-channel field-effect tube (N-MOS)
Or p-channel field-effect tube (P-MOS), wherein " p " indicates that positive carrier type (hole) and " n " indicates negative carrier type (electricity
Son).Although the present embodiment can be used for being formed P-MOS device with the description of N-MOS device, the semiconductor material of opposite types.
For example, n-type substrate is initially adulterated with n-type semiconductor, such as phosphorus, antimony or arsenic impurities, to form n-well region.
Further, several grooves 30 in well region 20, form groove by using photoetching, by using photoetching,
The pattern needed to form is transferred on photoresist from photomask, the part through light of photoetching agent pattern is removed using solvent,
The part to be patterned of exposure cutting optimal, removes the residue of photoresist, leaves patterned layer.Alternatively, some
The material of type is so patterned: being deposited directly to material by using the technology of such as non-electrolytic and electrolysis plating
In the region or gap formed by previous depositing operation.
Further, 20 bottom of groove forms round and smooth groove 31 by wedge angle processing and passes through in one embodiment
The isotropic etching of plasma can eliminate bottom wedge angle and form the round and smooth shape in bottom, avoid electric field concentration effect, mention
Rise the pressure resistance and reliability of transistor.
Further, sacrificial oxide layer is formed by thermal oxide to inside round and smooth groove 31, and removes sacrificial oxide layer,
In one embodiment, thermal oxidation process is dry-oxygen oxidation, and sacrificial layer oxidizing temperature is between 800 DEG C -1000 DEG C, the thickness of sacrificial layer
For degree between 100A-1000A, the method for sacrificial layer removal is HF wet etching, strips all surface oxide layer.Sacrificial layer processing
Purpose be mainly eliminate trench interiors etching injury, make trench interiors flat-satin, can effectively promote subsequent gate oxidation
The q&r of layer.
Further, implanted layer 40, in one embodiment, groove are formed by ion implanting in round and smooth 31 bottom of groove
Bottom, which terminates ion implanting, can prevent carrier from circulating from channel bottom, prevent base semiconductor from leaking electricity, more specifically, injection
Element is boron ion, and dosage is between 1E13-1E14/CM2, and energy is between 100-300kev, on ion beam current and semiconductor
Surface is vertical, then only bottom is not injected by injection boron ion, side wall.
Further, field oxide 50, channel bottom are formed by oxidation and rapid thermal annealing to round and smooth 31 bottom of groove
The field oxide that two sides are thin, bottom is thick is formed, in one embodiment, wherein method for oxidation is wet-oxygen oxidation, and bottom thickness oxygen is not
The electric field between polysilicon and bottom well region can be only weakened, device pressure resistance is promoted, the unlatching of bottom conductive channel can also be promoted
Threshold value prevents channel bottom from leaking electricity.
Further, gate oxide 60, insulation are formed in 10 upper surface of substrate and 31 inner wall of round and smooth groove
Or dielectric layer is formed on the upper surface and trench wall of substrate, as grid oxic horizon.The thickness control of gate oxide level
Threshold voltage, hot carrier in jection and grid-source voltage rated value processed.
Further, active area 80 and drain region 82,80 He of source region are respectively formed in the two sides of the round and smooth groove 31
Drain region 82 has one side to be located at the trenched side-wall, and another side is located at the upper surface of the well region 20, passes through etching technics
The photoresist 100 for removing corresponding source region and drain region is heavily doped with the n-type semiconductor of arsenic to the part injection of source region 80 and drain region 82
Material, to form 80 region of source electrode N+ layer and drain electrode 82 region of N+ layer.Use photoresist layer as exposure mask, with 1E15-1E16/
The dosage of CM2 is with the ion injection deposition n-type dopant of 10-50kev.In the present embodiment, by the way of side wall injection, tool
The mode of body are as follows: make upper semiconductor and inject the angle β that ion beam current is in 70 ° -83 ° or so, carries out four injections, and it is every
Injection is completed primary, and 90 ° of rotation is carried out to the same direction to transistor device.In this way, not only making to be located at well region upper surface
The region N+ can be efficiently injected into impurity, and the side wall close to groove side also can be by implanted dopant, but the concentration of impurity is remote
Lower than the impurity concentration in the region N+ for being located at well region upper surface, so its side wall close to source and drain side can be played and is lightly doped
The sidewall locations formation of N- layers of effect, the source region and drain region close to groove side is lightly doped N- layer, the source region side with
The N+ layer of drain region side forms the section shape of " 7 " font.
Further, in the groove filled with polysilicon 90 to form gate structure 91, the resistance of polysilicon layer can
To be lowered and being heavily doped with n-type semiconductor, such as arsenic.In this embodiment, it is preferred that filling mode is low pressure
Chemical vapor deposition, makes groove and semiconductor surface be filled up completely full polysilicon, and the thickness of polysilicon is substantially equal to the width of groove
Degree after the completion of filling, using upper surface of substrate gate oxide as barrier layer, carries out chemically mechanical polishing or dry method to polysilicon
It returns and carves, retain the polysilicon of trench interiors, polysilicon upper surface is concordant with upper surface of substrate, the polysilicon in other regions is removed,
The polysilicon of reservation forms gate structure, and the gate structure shape is, the depth of the gate structure corresponding with groove shape
It is corresponding with trench depth.
Planar gate structure is changed into vertical structure by the conducting channel and grid structure of change transistor by the present invention,
Grid structure side forms conducting channel, so that all-directional conductive structure is formed between source and drain, significant increase transistor
Conductive capability reduces the conducting resistance of transistor.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the present invention.
Claims (10)
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113594031A (en) * | 2021-07-29 | 2021-11-02 | 上海华力微电子有限公司 | Method for manufacturing semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6452231B1 (en) * | 1997-07-31 | 2002-09-17 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN101593704A (en) * | 2009-04-22 | 2009-12-02 | 上海宏力半导体制造有限公司 | The manufacture method of mos field effect transistor |
| CN105742353A (en) * | 2014-12-11 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and formation method thereof |
| WO2017174603A1 (en) * | 2016-04-07 | 2017-10-12 | Abb Schweiz Ag | Short channel trench power mosfet |
-
2018
- 2018-08-15 CN CN201810927822.2A patent/CN109166803A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6452231B1 (en) * | 1997-07-31 | 2002-09-17 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN101593704A (en) * | 2009-04-22 | 2009-12-02 | 上海宏力半导体制造有限公司 | The manufacture method of mos field effect transistor |
| CN105742353A (en) * | 2014-12-11 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and formation method thereof |
| WO2017174603A1 (en) * | 2016-04-07 | 2017-10-12 | Abb Schweiz Ag | Short channel trench power mosfet |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113594031A (en) * | 2021-07-29 | 2021-11-02 | 上海华力微电子有限公司 | Method for manufacturing semiconductor device |
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