CN108269816A - A kind of method for reducing cmos image sensor white-spot defects - Google Patents

Abstract

This disclosure relates to cmos image sensor and the method for reducing cmos image sensor white-spot defects.One of embodiment provides a kind of production method of cmos image sensor, including：Semi-conductive substrate is provided, sequentially forms grid oxic horizon and gate silicon layer on the semiconductor substrate；And then before the gate is formed, by the use of gate silicon layer as protective layer, multiple ion implanting is carried out to Semiconductor substrate, to form multiple doped regions inside Semiconductor substrate.

Description

A Method for Reducing White Point Defects of CMOS Image Sensors

technical field

The present disclosure relates to the technical field of semiconductors, in particular to a CMOS image sensor and a method for reducing white point defects of the CMOS image sensor.

Background technique

Image sensors are devices that convert optical images into electronic signals, and are widely used in digital cameras and other electro-optical devices. Generally, image sensors are mainly divided into two categories: charge coupled device (Charge Coupled Device, CCD) and metal oxide semiconductor device (Complementary Metal-Oxide Semiconductor, CMOS). Among them, CMOS sensors have the advantages of high integration, low power consumption, fast response, and low cost. With the continuous improvement of CMOS manufacturing process and technology, and the continuous decline in the price of high-end CMOS sensors, CMOS sensors will occupy an increasingly important position in the future development of high-definition cameras.

In a CMOS image sensor, a transfer transistor (TX) is used to transfer photogenerated electrons in a photodiode. FIG. 1 illustrates a schematic structural diagram of a conventional CMOS image sensor. As shown in FIG. 1, a conventional image sensor includes: a semiconductor substrate 100, a photodiode region 101, a pinned diode region 102 (including an N-type doped region 102-1, a P-type doped region 102-2 and 102-3 ), floating diffusion region 103 , gate 104 , gate spacer 105 and gate oxide layer 106 . Wherein, the photosensitive diode region 101, the pinned diode region 102 and the floating diffusion region 103 are arranged in the semiconductor substrate 100; the P-type doped regions 102-2 and 102-3 and the floating diffusion region 103 of the pinned diode region on the surface of the semiconductor substrate. The gate 104 , the gate spacer 105 and the gate oxide layer 106 constitute a gate structure located above the semiconductor substrate.

In the manufacturing process of the traditional CMOS image sensor, the ion implantation for forming the device is completed after the definition of the gate pattern, which will cause damage to the surface of the semiconductor substrate, resulting in white spots in the CMOS image sensor. In order to reduce the damage to the surface of the semiconductor substrate by ion implantation, an oxide layer with a certain thickness is usually used as a protective layer for ion implantation, but this increases the process of re-forming the oxide layer, increases the time cost and complicates the process. In addition, the oxide layer is consumed during processes such as dry etching and wet cleaning, which makes it difficult to control the distribution of ion implantation, which in turn adversely affects the performance of CMOS transistors.

It can be seen that there is a need to reduce the damage to the surface of the semiconductor substrate by ion implantation without increasing the number of process steps.

Contents of the invention

An object of the present disclosure is to provide a CMOS image sensor and a method of manufacturing the CMOS image sensor, so as to improve the performance of the CMOS image sensor.

According to a first aspect of the present disclosure, there is provided a method for fabricating a CMOS image sensor, comprising: providing a semiconductor substrate, on which a gate oxide layer and a gate silicon layer are sequentially formed; and subsequently forming Before the gate, using the gate silicon layer as a protective layer, multiple ion implantations are performed on the semiconductor substrate to form multiple doped regions inside the semiconductor substrate.

According to the first aspect of the present disclosure, before forming the gate oxide layer and the gate silicon layer, a first ion implantation is performed on the semiconductor substrate to form a first doped region inside the semiconductor substrate.

According to the first aspect of the present disclosure, after forming the gate oxide layer and the gate silicon layer and before forming the gate, a second ion implantation is performed on the semiconductor substrate to form a second doped region inside the semiconductor substrate , the second doped region is located above and in contact with the first doped region, and the second doped region is located at one side of the gate.

According to the first aspect of the present disclosure, after the second doped region is formed, the semiconductor substrate is subjected to third and fourth ion implantations to form a third doped region and a fourth doped region inside the semiconductor substrate. impurity region, the third doped region is located above one side of the second doped region and is in contact with the second doped region, the fourth doped region is located on the side of the second doped region The other side is above and in contact with the second doped region, and the third doped region and the fourth doped region are located on one side of the gate.

According to the first aspect of the present disclosure, after the formation of the third doped region and the fourth doped region, a fifth ion implantation is performed on the semiconductor substrate to form a fifth doped region inside the semiconductor substrate, the The fifth doped region is located above the first doped region and not in contact with the first doped region, and is located on the other side of the gate.

According to the first aspect of the present disclosure, the doping types of the first doped region, the second doped region, and the fifth doped region are the same as those of the third doped region, the fourth doped region The doping type of the region is opposite.

According to the first aspect of the present disclosure, the first doped region, the second doped region, and the fifth doped region are n-type doped regions, and the third doped region, the fourth doped region The doped region is a p-type doped region.

According to the first aspect of the present disclosure, after forming the plurality of doped regions, the gate and the gate spacer are sequentially formed.

According to the first aspect of the present disclosure, the thickness of the gate silicon layer is

According to a second aspect of the present disclosure, there is provided a CMOS image sensor, comprising: a semiconductor substrate; a photosensitive diode region, a floating diffusion region, and a pinned diode region located in the semiconductor substrate; The transmission tube on the bottom, wherein, the photosensitive diode region is the first doped region; the floating diffusion region is the fifth doped region; the pinned diode region includes the second doped region. region, the third doped region, the fourth doped region; and the transmission tube includes the gate oxide layer, the gate and the gate spacer.

Other features and advantages of the present invention will become more apparent through the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which constitute a part of this specification, illustrate the embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

FIG. 1 illustrates a schematic structural diagram of a traditional CMOS image sensor;

FIG. 2 illustrates a flowchart of a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present disclosure;

3A-3E illustrate the structural schematic diagrams of the steps of manufacturing a traditional CMOS image sensor;

4A-4D illustrate another existing structural schematic view of the steps of manufacturing a CMOS image sensor;

5A-5C illustrate structural schematic diagrams of steps of manufacturing a CMOS image sensor according to an exemplary embodiment of the present disclosure.

Note that in the embodiments described below, the same reference numerals may be used in common between different drawings to denote the same parts or parts having the same functions, and repeated descriptions thereof will be omitted. In this specification, similar reference numerals and letters are used to refer to similar items, therefore, once an item is defined in one figure, it does not require further discussion in subsequent figures.

In order to facilitate understanding, the position, size, range, etc. of each structure shown in the drawings and the like may not represent the actual position, size, range, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, etc. disclosed in the drawings and the like.

Detailed ways

As mentioned above, in the traditional CMOS image sensor manufacturing process, the ion implantation process after forming the gate will cause damage to the semiconductor substrate surface of the photosensitive diode, and the white spot is very sensitive to the surface quality and integrity of the photosensitive diode, so It will cause white spots on the CMOS image sensor. To solve this problem, related technologies propose to use an oxide layer or a dielectric layer as a protective layer for ion implantation. However, the inventors of the present application have found that using the oxide layer as a protective layer requires further arrangement of the oxide layer. In addition, since ion implantation is performed using a patterned photoresist, a certain amount of oxide layer will be consumed during the process, making the thickness of the oxide layer changes, making it difficult to control the distribution of ion implantation. Moreover, using the dielectric layer as a protection layer requires multiple etchings of the dielectric layer. It can be seen that these protection methods increase the process steps and introduce new process problems.

After in-depth research, considering the above, the inventors of the present application thought of adjusting the sequence of ion implantation and etching to form the gate pattern, using the gate silicon layer as a protective layer on the substrate surface, and proposed a method to reduce the CMOS image Method for sensor white point defects. Since the thickness of the gate silicon layer is generally thicker and its performance is more stable, it can not only effectively reduce the damage to the surface of the semiconductor substrate caused by ion implantation, reduce the generation of white spots in the image sensor, but also optimize the process flow.

Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that relative arrangements of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and in no way intended as any limitation of the disclosure, its application or uses. That is, the semiconductor devices and methods of fabrication thereof herein are shown in an exemplary manner to illustrate various embodiments of the structures and methods of the present disclosure. However, those skilled in the art will appreciate that they illustrate only exemplary, rather than exhaustive, ways in which the invention may be practiced. Furthermore, the figures are not necessarily to scale and some features may be exaggerated to show details of particular components.

Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be considered part of the Authorized Specification.

In all examples shown and discussed herein, any specific values should be construed as exemplary only, and not as limitations. Therefore, other examples of the exemplary embodiment may have different values.

In order to understand the present invention more comprehensively and clearly, the novel technology according to the present disclosure will be described below in conjunction with the accompanying drawings.

FIG. 2 illustrates a flowchart of a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present disclosure.

Specifically, as shown in FIG. 2 , at step 201 , a semiconductor substrate is provided. In some embodiments, the substrate may be made of any semiconductor material suitable for semiconductor devices, such as Si, SiC, SiGe, etc. In some other implementation manners, the substrate may also be various composite substrates such as silicon-on-insulator (SOI), silicon-germanium-on-insulator, and the like. Those skilled in the art understand that the substrate is not subject to any limitation, but can be selected according to actual applications. Other semiconductor device components may be formed in the substrate, eg, isolations (such as shallow trench isolations (STIs), wells, and/or other components formed in earlier processing steps. Other layers or features may have been formed on the substrate prior to the application of the first photoresist layer, such as contact holes, underlying metal lines and vias, and/or other features formed in earlier processing steps. Interlayer dielectric layers, etc.

At step 202, a first ion implantation is performed on the semiconductor substrate to form a photodiode region (ie, a first doped region) inside the semiconductor substrate.

At step 203, a gate oxide layer and a gate silicon layer are sequentially formed on the semiconductor substrate, the gate silicon layer covers the gate oxide layer, and the gate oxide layer covers the semiconductor substrate.

At step 204, multiple ion implantations are performed on the semiconductor substrate by using the gate silicon layer as a protection layer, so as to form a plurality of doped regions inside the semiconductor substrate. Specifically, in one embodiment of the present invention, the second to fifth ion implantations are performed on the semiconductor substrate to form second to fifth doped regions inside the semiconductor substrate.

At step 205 , the gate and the gate spacer are sequentially formed. The gate is formed by photolithography, and the sidewall of the gate is formed by dry etching. Specifically, the step of forming the gate includes: forming a photoresist layer on the surface of the gate silicon layer; exposing and developing the photoresist layer to form a patterned photoresist layer; taking the patterned photoresist layer as mask, etch the gate silicon layer; and remove the patterned photoresist layer.

Those skilled in the art should understand that the above steps do not limit the solutions of the present invention, but can be modified or deleted arbitrarily according to actual applications. Moreover, manufacturing the CMOS image sensor may also include other steps not listed here as required.

In order to understand the present invention more completely, the manufacturing method of the CMOS image sensor proposed by the present invention and its advantages over related technologies will be described in detail below with reference to FIGS. 3A-3E , 4A-4D, and 5A-5C. For the sake of brevity, the figure does not exemplify the structure of each step, but only exemplifies key steps.

3A-3E illustrate the structural schematic diagrams of the steps of manufacturing a conventional CMOS image sensor. First, as shown in FIG. 3A, a semiconductor substrate 100 is provided, and the first ion implantation is performed on the semiconductor substrate 100 to form a photodiode region 101. Subsequently, a gate oxide layer 106 and a gate oxide layer 106 are sequentially formed on the semiconductor substrate 100. pole silicon layer 104 . Wherein, the gate oxide layer 106 may be silicon dioxide, and the gate silicon layer 104 may be polysilicon. The gate silicon layer 104 is on top of the gate oxide layer 106 used to isolate the gate 104 from the semiconductor substrate 100 , which covers the channel region of the CMOS transistor of the semiconductor substrate 100 .

Subsequently, as shown in FIG. 3B , a photoresist layer is formed on the surface of the gate silicon layer 104 , and the formed photoresist layer is exposed and developed to form a patterned photoresist layer. Then, using the patterned photoresist layer as a mask, the gate silicon layer 104 is etched, and then the patterned photoresist layer is removed to form an etched gate.

Subsequently, as shown in FIG. 3C , an oxide layer 107 is formed on the surface of the semiconductor substrate 100 except the gate 104 as a protection layer for subsequent ion implantation. The oxide layer 107 may be a silicon dioxide layer formed by thermal oxidation.

Subsequently, as shown in FIG. 3D, multiple ion implantations are performed on the semiconductor substrate 100 with the oxide layer 107 as a protective layer to form a pinned diode region 102 and a floating doped region 103. The pinned diode region 102 includes doped region 102-1, doped region 102-2 and doped region 102-3.

Subsequently, as shown in FIG. 3E , after the multiple ion implantations shown in FIG. 3D are completed, a dielectric layer is formed on the semiconductor substrate 100 , and then the gate spacer 105 is formed. Although the specific process of forming the gate spacer 105 is not illustrated in FIG. 3E , it should be understood that the gate spacer 105 can be formed by dry etching.

It can be seen that the traditional method of using the oxide layer as a protective layer to manufacture a CMOS image sensor needs to form an additional layer of oxide layer 107, which increases the process steps. In addition, the thickness of the oxide layer 107 has a great influence on the distribution of ion implantation. Since ion implantation is performed by patterned photolithography, each ion implantation requires the formation and removal of a photoresist layer, which consumes a certain oxide layer, and the thickness of the consumed oxide layer is difficult to predict Therefore, it is difficult to control the distribution of ion implantation. Therefore, using the oxide layer as a protective layer reduces the damage to the surface of the semiconductor substrate caused by ion implantation to a certain extent, but increases the process flow and introduces new process problems.

4A-4D illustrate structural schematic diagrams of another existing manufacturing process of a CMOS image sensor. As shown in FIG. 4A, a semiconductor substrate 100 is provided, and the first ion implantation is performed on the semiconductor substrate 100 to form a photodiode region 101, and then a gate oxide layer 106 and gate silicon are sequentially formed on the semiconductor substrate 100. Layer 104.

Subsequently, as shown in FIG. 4B, a dielectric layer 105 is formed on the surface of the semiconductor substrate 100 by chemical vapor deposition, and then the dielectric layer 105 is etched to leave the semiconductor substrate. thick dielectric layer as a protective layer for subsequent ion implantation.

Subsequently, as shown in FIG. 4C, multiple ion implantations are performed on the semiconductor substrate 100 with the dielectric layer as a protective layer to form a pinned diode region 102 and a floating doped region 103. The pinned diode region 102 includes a doped region 102-1, a doped region 102-2 and a doped region 102-3.

Subsequently, as shown in FIG. 4D , all dielectric layers except the gate spacer 105 are removed by dry etching to form the gate spacer 105 .

It can be seen that the method of using the dielectric layer as a protective layer to manufacture a CMOS image sensor needs to etch the dielectric layer twice. Considering that the etching process actually includes multiple steps, this method increases the process to a certain extent. process, which results in a non-negligible time overhead.

5A-5C illustrate structural schematic diagrams of steps of manufacturing a CMOS image sensor according to an exemplary embodiment of the present disclosure. First, similar to FIGS. 3A and 4A, as shown in FIG. 5A, a semiconductor substrate 100 is provided, and the first ion implantation is performed on the semiconductor substrate 100 to form a photodiode region 101 (ie, a first doped region), Subsequently, a gate oxide layer 106 and a gate silicon layer 104 are sequentially formed on the semiconductor substrate 100. Preferably, the thickness of the gate silicon layer is

Subsequently, as shown in FIG. 5B, before forming the gate, the gate silicon layer 104 is used as a protective layer, and multiple ion implantations are performed on the semiconductor substrate 100 to form the pinned diode region 102 and the floating doped region 103 (that is, fifth doped region). The pinned diode region 102 includes a doped region 102-1 (ie, a second doped region), a doped region 102-2 (ie, a third doped region), and a doped region 102-3 (ie, a fourth doped region). Miscellaneous area). Wherein, the process of performing ion implantation on the semiconductor substrate 100 includes: forming a patterned photoresist layer on the semiconductor substrate, defining the position of the doped region, and then using the patterned photoresist as a mask to The substrate is implanted with ions to form a doped region, and the patterned photoresist layer is removed after the doped region is formed.

In FIG. 5B, the doped region 102-2 is located on the surface of the semiconductor substrate 100 on the side of the gate 104 and close to the gate 104, and the doped region 102-3 is located on the surface of the semiconductor substrate 100 and is adjacent to the doped region 102-2. On the same side but away from the gate 104 . Those skilled in the art should understand that the positions of the doped region 102 - 2 and the doped region 102 - 3 are not limited to those shown in FIG. 5C , and the positions of the two can also be interchanged. The doped region 102-1 is located between the photodiode region 101 and the doped regions 102-2 and 102-3, and is in contact with the photodiode region 101, the doped region 102-2 and the doped region 102-3. The floating diffusion region 103 is located above and not in contact with the photodiode region 101 , and is located on the surface of the semiconductor substrate 100 at the other side of the gate 104 . Wherein, the photodiode region 101 , the doped region 102 - 1 , the doped region 102 - 2 , and the doped region 102 - 3 are in contact with each other up and down to facilitate electron transmission.

In addition, the doping types of the photodiode region 101 , the doped region 102 - 1 , and the floating diffusion region 103 formed by ion implantation are opposite to those of the doped region 102 - 2 and the doped region 102 - 3 . According to an embodiment of the present disclosure, the photodiode region 101, the doped region 102-1, and the floating diffusion region 103 are n-type doped regions, that is, the ions implanted in the ion implantation process are n-type ions, such as phosphorus (P) The doped region 102-2 and the doped region 102-3 are p-type doped regions, that is, the ions implanted in the ion implantation process are p-type ions, such as boron (B). However, those skilled in the art should understand that the n-type and p-type ions implanted in the ion implantation process are not limited to phosphorus and boron.

Subsequently, as shown in FIG. 5C , after forming a plurality of doped regions, the gate and gate spacers are sequentially formed. Wherein, the gate is formed by photolithography, and the gate spacer is formed by dry etching. Wherein, the process of forming the gate includes: forming a photoresist layer on the surface of the gate silicon layer 104; exposing and developing the photoresist layer to form a patterned photoresist layer; taking the patterned photoresist layer as mask, etch the gate silicon layer 104; remove the patterned photoresist layer.

According to this embodiment, by adjusting the order of ion implantation and etching to form gate patterns, using the gate silicon layer as a protective layer on the substrate surface, not only does not add additional process steps such as deposition and etching, the process flow is optimized, Moreover, since the gate silicon layer is thicker and more stable than other protective layers in the related art, the damage to the surface of the semiconductor substrate caused by ion implantation is further reduced, and the generation of white spots of the image sensor is reduced. The method for manufacturing a CMOS image sensor according to this embodiment does not increase time and process costs, is simple and easy to operate, not only can improve the performance of the image sensor, but also does not introduce other technical difficulties.

Those skilled in the art will understand that, in addition to the illustrated processes and structures, the present disclosure also includes any other processes and structures necessary to form a CMOS image sensor.

In the specification and claims, the words "front", "rear", "top", "bottom", "above", "under", etc., if present, are used for descriptive purposes and not necessarily to describe a constant relative position. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. Orientation operation.

As used herein, the word "exemplary" means "serving as an example, instance, or illustration" rather than as a "model" to be exactly reproduced. Any implementation described illustratively herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the disclosure is not to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or detailed description.

As used herein, the word "substantially" is meant to include any minor variations due to defects in design or manufacturing, device or component tolerances, environmental influences, and/or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in an actual implementation.

In addition, "first", "second", and similar terms may also be used herein for reference purposes only, and thus are not intended to be limiting. For example, the words "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.

It should also be understood that when the word "comprises/comprises" is used herein, it indicates the presence of indicated features, integers, steps, operations, units and/or components, but does not exclude the presence or addition of one or more other features, whole, steps, operations, units and/or components and/or combinations thereof.

In this disclosure, the term "provide" is used broadly to cover all ways of obtaining an object, thus "provide something" includes, but is not limited to, "purchase", "preparation/manufacture", "arrangement/setup", "installation/ Assembly", and/or "Order" objects, etc.

Those skilled in the art will appreciate that the boundaries between the above-described operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Also, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in other various embodiments. However, other modifications, changes and substitutions are also possible. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

In addition, implementations of the present disclosure may also include the following examples:

(1) a manufacturing method of a CMOS image sensor, characterized in that, comprising:

providing a semiconductor substrate on which a gate oxide layer and a gate silicon layer are sequentially formed; and

Then, before forming the gate, using the gate silicon layer as a protective layer, multiple ion implantations are performed on the semiconductor substrate to form multiple doped regions inside the semiconductor substrate.

(2) The method according to 1, wherein,

Before forming the gate oxide layer and the gate silicon layer, a first ion implantation is performed on the semiconductor substrate to form a first doped region inside the semiconductor substrate.

(3) The method according to 2, wherein,

After the gate oxide layer and the gate silicon layer are formed and before the gate is formed, a second ion implantation is performed on the semiconductor substrate to form a second doped region inside the semiconductor substrate, and the second doped region Located above and in contact with the first doped region, and the second doped region is located on one side of the gate.

(4) The method according to 3, wherein,

After forming the second doped region, the semiconductor substrate is subjected to the third and fourth ion implantation to form a third doped region and a fourth doped region inside the semiconductor substrate, the third doped region The impurity region is located above one side of the second doped region and is in contact with the second doped region, and the fourth doped region is located above the other side of the second doped region and is in contact with the second doped region. The second doped region is in contact with the second doped region, and the third doped region and the fourth doped region are located on one side of the gate.

(5) The method according to 4, wherein,

After forming the third doped region and the fourth doped region, the semiconductor substrate is implanted with ions for the fifth time to form a fifth doped region inside the semiconductor substrate, and the fifth doped region is located in the above and not in contact with the first doped region, and located on the other side of the gate.

(6) The method according to any one of 2-5, characterized in that,

The doping types of the first doping region, the second doping region and the fifth doping region are opposite to those of the third doping region and the fourth doping region.

(7) The method according to any one of 2-5, characterized in that,

The first doped region, the second doped region, and the fifth doped region are n-type doped regions, and the third doped region and the fourth doped region are p-type doped regions. Area.

(8) The method according to 1, wherein,

After forming a plurality of doped regions, the gate and gate sidewalls are sequentially formed.

(9) The method according to 8, wherein the step of forming the gate comprises:

forming a photoresist layer on the surface of the gate silicon layer;

Exposing and developing the photoresist layer to form a patterned photoresist layer;

using the patterned photoresist layer as a mask to etch the gate silicon layer; and

The patterned photoresist layer is removed.

(10) The method according to 1, wherein

The thickness of the gate silicon layer is

(11) A CMOS image sensor made using the method according to any one of 1-10, characterized in that it comprises:

semiconductor substrate;

a photodiode region, a floating diffusion region, a pinned diode region in the semiconductor substrate; and

a transfer tube on said semiconductor substrate, wherein,

The photosensitive diode region is the first doped region;

The floating diffusion region is the fifth doped region;

the pinned diode region includes the second doped region, the third doped region, the fourth doped region; and

The transmission tube includes the gate oxide layer, the gate and the gate spacer.

Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art should understand that the above examples are for illustration only, rather than limiting the scope of the present disclosure. The various embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (10)

1. A method for making a CMOS image sensor, comprising: providing a semiconductor substrate on which a gate oxide layer and a gate silicon layer are sequentially formed; and Then, before forming the gate, using the gate silicon layer as a protective layer, multiple ion implantations are performed on the semiconductor substrate to form multiple doped regions inside the semiconductor substrate. 2. The method of claim 1, wherein, Before forming the gate oxide layer and the gate silicon layer, a first ion implantation is performed on the semiconductor substrate to form a first doped region inside the semiconductor substrate. 3. The method of claim 2, wherein, After the gate oxide layer and the gate silicon layer are formed and before the gate is formed, a second ion implantation is performed on the semiconductor substrate to form a second doped region inside the semiconductor substrate, and the second doped region Located above and in contact with the first doped region, and the second doped region is located on one side of the gate. 4. The method of claim 3, wherein, After forming the second doped region, the semiconductor substrate is subjected to the third and fourth ion implantation to form a third doped region and a fourth doped region inside the semiconductor substrate, the third doped region The impurity region is located above one side of the second doped region and is in contact with the second doped region, and the fourth doped region is located above the other side of the second doped region and is in contact with the second doped region. The second doped region is in contact with the second doped region, and the third doped region and the fourth doped region are located on one side of the gate. 5. The method of claim 4, wherein, After forming the third doped region and the fourth doped region, the semiconductor substrate is implanted with ions for the fifth time to form a fifth doped region inside the semiconductor substrate, and the fifth doped region is located in the above and not in contact with the first doped region, and located on the other side of the gate. 6. The method according to any one of claims 2-5, characterized in that, The doping types of the first doping region, the second doping region and the fifth doping region are opposite to those of the third doping region and the fourth doping region. 7. The method according to any one of claims 2-5, characterized in that, The first doped region, the second doped region, and the fifth doped region are n-type doped regions, and the third doped region and the fourth doped region are p-type doped regions. Area. 8. The method of claim 1, wherein, After forming a plurality of doped regions, the gate and gate sidewalls are sequentially formed. 9. The method of claim 1, wherein, The thickness of the gate silicon layer is 10. A CMOS image sensor manufactured by the method according to any one of claims 1-9, characterized in that it comprises: semiconductor substrate; a photodiode region, a floating diffusion region, a pinned diode region in the semiconductor substrate; and a transfer tube on said semiconductor substrate, wherein, The photosensitive diode region is the first doped region; The floating diffusion region is the fifth doped region; the pinned diode region includes the second doped region, the third doped region, the fourth doped region; and The transmission tube includes the gate oxide layer, the gate and the gate spacer.