CN108231900A - Power semiconductor device and preparation method thereof - Google Patents

Abstract

The invention relates to a power semiconductor device and a preparation method thereof, relates to a power semiconductor device, and aims to solve the problems that the photoetching alignment precision between a source electrode contact hole and a grid electrode groove limits the channel density of the device and a cavity is easy to generate in a filling material in the groove filling process. In the novel trench field effect transistor provided by the invention, the width of the top of the gate trench is larger than that of the bottom, so that the filling of the trench gate material is facilitated.

Description

A kind of power semiconductor device and its preparation method

technical field

The invention relates to a power semiconductor device, especially a structure of a power field effect transistor (Power MOSFET) and a manufacturing method thereof.

Background technique

Power field effect transistor (Power MOSFET) is a key semiconductor component, which is widely used in various medium and low voltage power control systems, such as motor drive, electric energy conversion, etc. Figure 1 shows a schematic cross-sectional view of a conventional trench-type power field effect transistor device, the bottom of which is a drain electrode formed of a metal layer. Above the drain electrode is an N+ type substrate layer (102). An N-type drift region (101) is located above the substrate layer (102). On the upper surface of the N-type drift region (101), there are a series of trenches (106) with the same structural characteristics, the trenches (106) are filled with a gate conductive material (105), and the gate conductive material (105) is connected to the gate electrode . A commonly used gate conductive material is heavily doped polysilicon. There is a gate oxide layer (111) between the gate conductive material (105) and the inner wall of the gate trench (106). Between adjacent gate trenches (106), there is a P-type body region (107). Above the P-type body region (107), there are N+-type source region (108) and P ⁺ -type contact region (109) arranged side by side, and the N ⁺ -type source region (108) and gate trench (106 ) adjacent to one side wall. Above the gate trench (106), there is an interlayer dielectric layer (104). Above the interlayer dielectric layer (104) is a metal layer (103) constituting the source electrode. The source metal (103) is connected to the N ⁺ type source region (108) and the P ⁺ type contact region (109) through the source contact hole (110) in the dielectric layer (104).

When the above-mentioned device works in the forward conduction state, a positive voltage is placed on the gate electrode; when the gate electrode voltage is higher than the threshold voltage of the device, the P-type body region (107) is adjacent to the gate trench (106) Part of it will form a conductive channel. The number of channels per unit area of the device is called the channel density of the device, and the periodic spacing of adjacent gate trenches of the device is called the cell pitch of the device. It is not difficult to understand that the smaller the cell spacing of the device, the greater the channel density, the lower the channel resistance, and the lower the on-resistance of the device. However, in traditional trench field effect transistors, there are certain limitations in increasing the trench density. The main limiting factor is that in the process of traditional trench field effect transistors, the gate trench (106) and the source The electrode contact hole (110) is formed through two photolithography and etching processes, that is, the gate trench (106) is formed through the first photolithography and etching process, and then the gate trench (106) is formed through the second photolithography and etching process. etch to form a source contact hole (110). In order to ensure the relative position of the source contact hole (110) and the gate trench (106), alignment needs to be carried out by photolithography alignment marks between the two photolithography. However, limited by the process equipment conditions, there must be a certain alignment deviation between the two photolithography sessions. In order to avoid the problem of short-circuiting between the source and the gate due to misalignment between the source contact hole (110) and the gate trench (106), it is necessary to increase the distance between the two during device design. The spacing is also called "safety distance". In this way, the distance between adjacent trenches is inevitably increased, thereby reducing the channel density of the device and increasing the on-resistance of the device.

In addition, there is another problem with conventional trench field effect transistors. In order to obtain higher device channel density, the smallest possible trench width is generally used when designing the gate trench (106). On the other hand, in order to ensure the withstand voltage capability of the device, the gate trench (106) must have a certain trench depth. This results in a higher depth/width ratio (hereinafter "aspect ratio") of the gate trench (106). During device processing, the trench (106) needs to be completely filled with gate conductive material (105). The filling material is usually polycrystalline silicon, and the filling method is generally chemical vapor deposition. However, for trenches with a high aspect ratio, during the filling process, since the material deposition rate at the top of the trench is generally higher than that at the bottom of the trench, it is easy to cause voids ( 112), as shown in Figure 2. During the use of the device, the cavity (112) will generate stress due to thermal expansion and contraction, thereby causing adverse effects on the reliability of the device.

According to the problems existing in the trench type field effect transistor of the above-mentioned prior art, that is, the lithographic alignment accuracy between the source contact hole and the gate trench limits the channel density of the device, and the trench filling process is easy. For the problem of voids inside the filling material, it is necessary to provide an innovative trench type field effect transistor device structure to increase the trench density of the device, reduce the on-resistance of the device, and avoid voids inside the trench filling material to improve the device. reliability.

Contents of the invention

In order to solve the problems mentioned above, the specific technical solutions provided by the present invention are described as follows:

It should be pointed out that the corresponding positional words described in this document such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal" are corresponding to the reference The relative position of the icon. The fixed direction is not limited in specific implementation. In addition, the semiconductor devices described in this specification can be classified into N-type channel devices or P-type channel devices according to the type of the MOS conductive channel. The following embodiments all take N-type channel devices as examples. In practical implementation, the present invention is not limited to N-type or P-type channel devices. Therefore, the present invention is also applicable to P-type channel devices, and then it is only necessary to exchange the N-type region and the P-type region described below.

In the following description, a heavily doped p-type conducting semiconductor region is denoted as a p ⁺ region, and a heavily doped n-type conducting semiconductor region is denoted as an n ⁺ region. For example, in a silicon material substrate, unless otherwise specified, the impurity concentration of a heavily doped region is generally between 1×10 ¹⁸ cm ⁻³ and 1×10 ²¹ cm ⁻³ .

A power semiconductor device, said semiconductor device comprising:

An N ⁺ -type substrate layer at the bottom;

An N-type epitaxial layer disposed on the N ⁺ -type substrate layer;

More than one gate trench located on the N-type epitaxial layer, a gate electrode is arranged in the gate trench, and the gate electrode and the gate trench are isolated by a first insulating dielectric layer;

A P-type body region is provided between adjacent gate trenches, a source trench is provided above the P-type body region, and the inside of the source trench is filled with a source metal, and the P-type body region is provided with a source trench. The body region and the source trench are provided with a P ⁺ type contact region;

A second insulating dielectric layer is provided in the gate trench and above the gate electrode;

An included angle is provided between the sidewall of the source trench and the sidewall of the adjacent gate trench, and an N ⁺ -type source electrode is provided between the source trench and the gate trench. region, the source trench and the gate electrode are separated by a second insulating dielectric layer.

Further, a shielding gate electrode is also provided in the gate trench, and the shielding gate electrode is located below the gate electrode, and the shielding gate electrode and the gate trench and between the gate electrodes are respectively passed through the first gate electrode. The third insulating medium layer is isolated from the fourth insulating medium layer.

Further, the thickness of the third insulating medium layer is greater than the thickness of the first insulating medium layer.

Further, the thickness of the fourth insulating medium layer is greater than the thickness of the first insulating medium layer.

Further, the width of the top of the gate trench is greater than the width of the bottom thereof.

Further, the width of the top of the source trench is greater than the width of the bottom thereof.

Further, the height of the bottom of the N ⁺ -type source region is lower than the height of the top of the gate electrode, that is, the lowest point of the N ⁺ -type source region is located below the gate electrode.

A preparation method of a power semiconductor device, the preparation method comprising the steps of:

First: grow an N-type silicon epitaxial layer on the N ⁺ -type silicon substrate layer, and form more than one gate trench on the upper surface of the N-type silicon epitaxial layer, wherein the width of the top of the formed gate trench is greater than the width of its bottom ;

Second: forming a gate dielectric layer in the gate trench;

Third: forming a gate electrode at the bottom of the gate trench;

Fourth: form a P-type body region and an N ⁺ -type source region between adjacent gate trenches, wherein the N ⁺ -type source region is located above the P-type body region, and the N ⁺ -type source region The bottom junction is deeper than the height of the top of the gate electrode;

Fifth: forming a second insulating dielectric layer on the top of the device, the second insulating dielectric layer completely filling the gate trench;

Sixth: Etching back the second insulating dielectric layer, and the remaining second insulating dielectric layer only covers the gate trench;

Seventh: Conduct semiconductor etching, use the second insulating dielectric layer as a hard mask, etch the source trench, and there is an angle between the side wall of the source trench and the side wall of the adjacent gate trench ;

Eighth: forming a P ⁺ type contact region, and depositing a source metal layer on its surface;

Ninth: forming a drain metal layer at the bottom of the N ⁺ -type semiconductor substrate.

A preparation method of a power semiconductor device, the preparation method comprising the steps of:

First: grow an N-type silicon epitaxial layer on the N ⁺ -type silicon substrate layer, and form more than one gate trench on the upper surface of the N-type silicon epitaxial layer, wherein the width of the top of the formed gate trench is greater than the width of its bottom ;

Second: form a third insulating dielectric layer in the gate trench, and then form a shielded gate electrode at the bottom of the gate trench, and the sidewall of the gate trench and the shielded gate electrode are connected by a third Insulation dielectric layer isolation;

Third: forming a fourth insulating dielectric layer above the shielded gate electrode, and forming a gate dielectric layer on the sidewall of the trench;

Fourth: forming a gate electrode on the fourth insulating dielectric layer, the upper surface of the gate electrode is lower than the top of the gate trench;

Fifth: Form a P-type body region and an N ⁺ -type source region between the gate trenches, the N ⁺ -type source region is located above the P-type body region, and the junction depth at the bottom of the N ⁺ -type source region is generally deeper than the height at which the top of the gate electrode is located;

Sixth: forming a second insulating dielectric layer on the top of the device, and the second insulating dielectric layer completely fills the gate trench;

Seventh: Etching back the second insulating dielectric layer, the remaining second insulating dielectric layer only exists on the top of the gate trench;

Eighth: Carry out semiconductor etching on the surface of the device, use the second insulating dielectric layer as a hard mask, etch out the source trench, and the sidewall of the source trench and the sidewall of the adjacent gate trench with an included angle;

Ninth: forming a P ⁺ type contact region, and depositing a source metal layer on the surface;

Tenth: forming a drain metal layer at the bottom of the N ⁺ -type semiconductor substrate.

The above-mentioned power semiconductor device is also applicable to an insulated gate bipolar transistor (IGBT), and it is only necessary to replace the above-mentioned N ⁺ -type semiconductor substrate with a P-type doped region.

The above power semiconductor devices are also applicable to P-type channel devices or N-type channel devices, only the above-mentioned N-type regions and P-type regions need to be exchanged.

The beneficial effects of the present invention are: the novel trench type field effect transistor provided by the present invention does not require an additional mask plate for the etching of the source trench (source contact hole), thereby avoiding the source contact hole light The interlayer alignment deviation of the engraving process eliminates the limitation of the "safety distance" between the gate trench and the source contact hole, which can greatly reduce the distance between adjacent gate trenches and improve the conductivity of the device's conductive channel. Density, lower on-resistance and lower energy loss than ordinary trench field effect transistors, and improved device performance. In addition, in the novel trench field effect transistor provided by the present invention, the width of the top of the gate trench is greater than the width of the bottom, which is beneficial to the filling of the gate material of the trench, thereby solving the problem of voids generated when the trench is buried. problems and improve device reliability.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a trench field effect transistor chip in the prior art.

FIG. 2 is a partially enlarged view of the gate trench portion of the trench field effect transistor structure in the prior art in FIG. 1 .

FIG. 3 is a schematic cross-sectional view of the first embodiment according to the present invention.

4 to 11 are schematic cross-sectional views of the main manufacturing steps according to the first embodiment of the present invention.

Fig. 12 is a schematic cross-sectional view of a second embodiment according to the present invention.

13 to 21 are schematic cross-sectional views of main manufacturing steps according to a second embodiment of the present invention.

Detailed ways

The present invention provides a novel trench type field effect transistor structure and its manufacturing method, and has the following specific embodiments.

It should be noted that, in the description of the following embodiments, the semiconductor substrate of the trench field effect transistor is considered to be made of silicon (Si) material. However, the substrate can also be made of any other material suitable for manufacturing the device, such as germanium (Ge), silicon carbide (SiC) and the like. In the following description, the dielectric material of the device may consist of silicon oxide (SiO _x ). However _, other dielectric _materials , such as silicon nitride ( _{SixNy )} , aluminum oxide ( _AlxOy ), and silicon oxynitride ( _SixNyOz ), _can also be used. In the following description, the conductivity types of the semiconductor regions are classified into p-type and n-type. A p-type conductive semiconductor region can be formed by doping one or more impurities into the original semiconductor region. These impurities can be but not limited to: boron (B), aluminum (Al), and gallium (Ga). An n-type conductive semiconductor region can also be formed by doping one or more impurities into the original semiconductor region. These impurities can be but not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), and protons (H+), etc. In addition, the following embodiments will use devices with n-type MOS channels for illustration, but it should be pointed out that the present invention is also applicable to devices with p-type MOS channels.

Example 1

Fig. 3 is an enlarged diagram of a cross section according to the first embodiment of the present invention. The bottom of the device is a drain electrode, and an N ⁺ type substrate layer (202) and an N type epitaxial layer (201) are arranged above the drain electrode; a series of gate trenches (206) are arranged on the upper surface of the N type epitaxial layer; There is a gate electrode (205) filled with a conductive medium (such as polysilicon, metal, etc.) in the pole trench (206), and the gate electrode (205) and the gate trench (206) are formed by a first insulating medium layer ( gate dielectric layer) (211); in addition, the top height of the gate electrode (205) is lower than the top height of the gate trench (206), and above the gate electrode (205), there is a second insulating dielectric layer (212 ) fills the top of the gate trench (206); between adjacent gate trenches (206), there is a P-type body region (207) and a source trench (210) above it; the source trench The inside of the groove (210) is filled with the source metal (203); there is a heavily doped P+ type contact region (209) between the source trench (210) and the P type body region (207), which is used to reduce the source Pole contact resistance; there is an N ⁺ type source region (208) between adjacent gate trenches (206) and source trenches (210); the N ⁺ type source region (208) and the corresponding Sidewalls of the gate trench (206) and the source trench (210) are respectively adjoined.

In addition, the present invention also provides the manufacturing method of the device of the first embodiment, as shown in Fig. 4-Fig. 11:

First, an N ^- type silicon epitaxial layer (201) is grown on the N + -type silicon substrate layer (202). Then, a series of grooves (206) are formed on the upper surface of the epitaxial layer, as shown in FIG. 206) has a width at the top greater than that at the bottom; there are various methods for forming the gate trench (206), such as dry etching, wet etching, or a combination of the two; the gate trench (206) Forming usually requires first forming a patterned hard mask by photolithography, and then performing selective etching. The hard mask can be made of silicon oxide, silicon nitride and other materials.

Then, as shown in FIG. 5 , a gate dielectric layer ( 211 ) is formed in the gate trench ( 206 ); the gate dielectric layer ( 211 ) can be made of silicon oxide, silicon nitride and other materials.

Next, as shown in Figure 6, in the gate trench (206), a gate electrode (205) is formed on the gate dielectric layer (211); the upper surface of the gate electrode (205) is lower than the gate trench (206). ) at the top. The conductive material forming the gate electrode (205) is usually polysilicon, and the forming method is generally chemical vapor deposition. Since the gate trench (206) has inclined sidewalls and the width of the top of the trench is greater than that of the bottom of the trench, the formation of filling voids can be effectively avoided during the process of depositing and filling the gate conductive material.

In the next step, a P-type body region (207) and an N ⁺ type source region (208) are respectively formed between the gate trenches (206), as shown in FIG. 7; wherein the N ⁺ type source region (208) is located Above the P-type body region (207), the bottom junction depth of the N+-type source region (208) is generally deeper than the height of the top of the gate electrode (205), so as to form a MOS channel controlled by the gate electrode (205). It should be pointed out that the formation of the P-type body region (207) and the N ⁺ -type source region (208) can also be implemented after some steps described later, and the sequential processing sequence does not affect the formation of the device structure. .

Next, as shown in FIG. 8 , a second insulating dielectric layer ( 212 ) is formed on the top. The second insulating dielectric layer (212) is generally made of silicon oxide material, and can also be other materials such as silicon nitride, and its formation method can be chemical vapor deposition; the second insulating dielectric layer (212) forms the gate trench (206) Completely filled.

Next, the second insulating dielectric layer (212) is etched back, and the remaining second insulating dielectric layer (212) is shown in Figure 9; the remaining second insulating dielectric layer (212) only exists in the gate trench ( 206); the second insulating dielectric layer that was originally positioned on the surface of the semiconductor substrate is completely eliminated in the etching-back step; the etching-back step can be dry or wet etching or a combination of the two, or can be chemically Mechanical polishing process is achieved.

Then, as shown in FIG. 10, semiconductor etching is performed on the surface, and the source trench (210) is etched out by using the remaining second insulating dielectric layer (212) as a hard mask, and the source trench (210) There is an angle greater than zero between the sidewall of the sidewall and the sidewall of the adjacent gate trench (206); in this way, the source trench (210) and the gate electrode (205) pass through the gate trench ( 206) The second insulating dielectric layer (212) on top is naturally isolated; therefore, the etching of the source trench (210) does not require additional mask and photolithography steps.

Next, as shown in FIG. 11 , a P+ type contact region ( 209 ) is formed, and a source metal layer ( 203 ) is deposited on the surface.

Finally, a drain metal layer is formed on the bottom of the N+ type semiconductor substrate (202). Before forming the drain metal layer, it is also possible to thin the substrate layer (202) to reduce the resistance of the substrate.

According to the above processing method, since the etching of the source trench (source contact hole) (210) does not require an additional mask plate, the interlayer alignment deviation of the contact hole photolithography process is avoided, and the gate trench is eliminated. The limitation of the "safety distance" between the groove (206) and the source contact hole (210) can greatly reduce the distance between adjacent gate trenches (206), increase the density of the conductive channel of the device, and achieve a higher than usual The trench field effect transistor has lower on-resistance and lower energy loss, which improves device performance. In addition, because the width of the top of the gate trench (206) is greater than the width of the bottom, it is beneficial to fill the gate material of the trench, thereby solving the problem of voids generated when the trench is filled, and improving the reliability of the device.

Example 2

Fig. 12 is an enlarged diagram of a cross-section according to a second embodiment of the present invention. Compared with the device structure in the first embodiment shown in Fig. 3, the major difference of the device structure in the second embodiment is that , a shielding gate electrode (220) is also provided in the gate trench where the gate electrode (205) is located; the shielding gate electrode (220) is located below the gate electrode (205), and is connected to the gate electrode (205) and the The pole trench (206) is isolated by an insulating dielectric layer; the shielding gate electrode (220) can be connected to the source electrode. For traditional power field effect transistors, increasing the doping concentration of the epitaxial layer (201) is beneficial to reducing the on-resistance of the device, but increasing the doping concentration of the epitaxial layer (201) often reduces the withstand voltage capability of the device. In contrast, for the device in the second embodiment, in the off state of the device, the shielding gate electrode (220) can effectively reduce the electric field between the gate trenches (206), and improve the withstand voltage capability of the device; Therefore, the device can increase the doping concentration of the epitaxial layer (201) on the premise of maintaining the same withstand voltage capability, thereby obtaining lower on-resistance; on the other hand, due to the existence of the shielding gate electrode (220), The overlapping area between the gate and the drain of the device is greatly reduced, so that the gate-drain parasitic capacitance (Cgd) is greatly reduced, which is beneficial to greatly speeding up the switching speed of the device.

The specific description of the device of the second embodiment of the invention shown in Fig. 12 is as follows:

The bottom of the device is a drain electrode, and above the drain electrode are an N ⁺ type silicon substrate layer (202) and an N type silicon epitaxial layer (201); there are a series of gate trenches (206) on the upper surface of the N type epitaxial layer; There is a gate electrode (205) filled with a conductive medium (such as polysilicon, metal, etc.) in the trench (206) and a shielded gate electrode (220) below it, wherein the gate electrode (205) and the gate trench (206 ) are separated by a gate insulating dielectric layer (211); the shielding gate electrode (220) is separated from the gate trench (206) and the gate electrode (205) through a third insulating dielectric layer (213) and a fourth insulating dielectric layer, respectively. layer (214) isolation; the insulating dielectric layer can be made of silicon oxide, silicon nitride, or other oxynitride compounds; the thickness of the third insulating dielectric layer (213) is generally greater than the thickness of the gate dielectric layer (211), to Improve the withstand voltage capability between the shielding gate electrode (220) and the gate trench (206); the thickness of the fourth insulating dielectric layer (214) is generally greater than the thickness of the gate dielectric layer (211), so as to reduce the pressure of the gate electrode (205) ) and shield the parasitic capacitance between the gate electrode (220); in addition, the top height of the gate electrode (205) is lower than the top height of the gate trench (206), and above the gate electrode (205), there is a second The insulating dielectric layer (212) fills the top of the gate trenches (206); between adjacent gate trenches (206), there are P-type body regions (207) and source trenches (210) above them. ); the inside of the source trench (210) is filled with the source metal (203); there is a heavily doped P ⁺ type contact region (209) between the source trench (210) and the P type body region (207) ), used to reduce the source contact resistance; there is an N ⁺ type source region (208) between the adjacent gate trench (206) and the source trench (210); the N ⁺ type source The region (208) adjoins sidewalls of the corresponding gate trench (206) and source trench (210), respectively.

In addition, the present invention also provides a method for manufacturing the device of the second embodiment, as shown in FIGS. 13-21 :

First, an N ^- type silicon epitaxial layer (201) is grown on the N + -type silicon substrate layer (202). Then, a series of grooves (206) are formed on the upper surface of the epitaxial layer, as shown in FIG. 206) has a width at the top greater than that at the bottom; there are various methods for forming the gate trench (206), such as dry etching, wet etching, or a combination of the two; the gate trench (206) Forming usually requires first forming a patterned hard mask by photolithography, and then performing selective etching. The hard mask can be made of silicon oxide, silicon nitride and other materials.

Then, as shown in FIG. 14, a third insulating dielectric layer (213) is formed in the gate trench (206); the third insulating dielectric layer (213) can be made of materials such as silicon oxide and silicon nitride; subsequently, by Conductive materials (such as polysilicon, etc.) are deposited and etched back to form a shielded gate electrode (220) inside the gate trench (206); the shielded gate electrode (220) connects the bottom of the gate trench (206) It is partially filled and isolated from the sidewall of the gate trench (206) by a third insulating dielectric layer (213).

In the next step, as shown in Figure 15, a fourth insulating dielectric layer (214) is formed above the shielding gate electrode (220), and a gate dielectric layer (211) is formed on the trench sidewall; the fourth insulating dielectric layer (214) and the gate dielectric layer (211) are usually made of oxides, such as silicon oxide etc., and the thickness of the fourth insulating dielectric layer (214) is usually greater than the thickness of the gate dielectric layer (215); the fourth insulating dielectric layer (214) and the gate dielectric The layer (211) can be formed by methods such as deposition or oxidation.

Next, as shown in Figure 16, a gate electrode (205) is formed on the fourth insulating dielectric layer (204), the upper surface of the gate electrode (205) is lower than the top of the gate trench (206); the gate electrode (205) It is usually composed of polysilicon, and may also be composed of other conductive substances such as metals; its formation method can be chemical vapor deposition and etching back.

In the next step, a P-type body region (207) and an N ⁺ -type source region (208) are respectively formed between the gate trenches (206), as shown in FIG. 17; wherein the N ⁺ -type source region (208) is located Above the P-type body region (207), the bottom junction depth is generally deeper than the height of the top of the gate electrode (205), so as to form a MOS channel controlled by the gate electrode (205). It should be pointed out that the formation of the P-type body region (207) and the N ⁺ -type source region (208) can also be implemented after some steps described later, and the sequential processing sequence does not affect the formation of the device structure. .

Then, as shown in Figure 18, a second insulating dielectric layer (212) is formed on the top. The second insulating dielectric layer (212) is usually made of silicon oxide material, or other materials such as silicon nitride, and its formation method can be chemical Vapor deposition: the second insulating dielectric layer (212) completely fills the gate trench (206).

Next, the second insulating dielectric layer (212) is etched back, and the remaining second insulating dielectric layer (212) is shown in Figure 19; the remaining second insulating dielectric layer (212) only exists in the gate trench ( 206); the original second insulating dielectric layer (212) on the surface of the semiconductor substrate is completely eliminated in the etching-back step; the etching-back step can be dry or wet etching or a combination of the two, or This can be achieved by a chemical mechanical polishing process.

Then, as shown in Figure 20, semiconductor etching is carried out on the surface of the device, and the source trench (210) is etched out by using the remaining second insulating dielectric layer (212) as a hard mask, and the source trench (210 ) and the sidewall of the adjacent gate trench (206) have an angle greater than zero; in this way, the source trench (210) and the gate electrode (205) pass through the gate trench The second insulating dielectric layer (204) on top of (206) is naturally isolated; therefore, etching of the source trench (210) does not require additional mask and photolithography steps.

Next, as shown in FIG. 21 , a P ⁺ -type contact region ( 209 ) is formed, and a source metal layer ( 203 ) is deposited on the surface.

Finally, a drain metal layer is formed on the bottom of the N ⁺ -type semiconductor substrate ( 202 ). Before forming the drain metal layer, it is also possible to thin the substrate layer ( 202 ) to reduce the resistance of the substrate.

According to the above processing method, since the etching of the source trench (source contact hole) (210) does not require an additional mask plate, the interlayer alignment deviation of the contact hole photolithography process is avoided, and the gate trench is eliminated. The limitation of the "safety distance" between the groove (206) and the source contact hole (210) can greatly reduce the distance between adjacent gate trenches (206), increase the density of the conductive channel of the device, and achieve a higher than usual The trench field effect transistor has lower on-resistance and lower energy loss, which improves device performance. In addition, because the width of the top of the gate trench (206) is greater than the width of the bottom, it is beneficial to fill the gate material of the trench, thereby solving the problem of voids generated when the trench is filled, and improving the reliability of the device.

Claims (17)

1. A power semiconductor device, characterized in that, said semiconductor device comprises: N ⁺ type substrate layer (202) at the bottom; An N ^- type epitaxial layer (201) disposed on the N + -type substrate layer (202); More than one gate trench (206) located on the N-type epitaxial layer (201), the gate trench (206) is provided with a gate electrode (205), and the gate electrode (205) and the gate The pole trench (206) is isolated by the first insulating dielectric layer (211); A P-type body region (207) is arranged between adjacent gate trenches (206), and a source trench (210) is arranged above the P-type body region (207), and the source trench the interior of (210) is filled with source metal (203); A second insulating dielectric layer (212) is provided in the gate trench (206) and above the gate electrode (205); An included angle is provided between the sidewall of the source trench (210) and the sidewall of the adjacent gate trench (206), and between the source trench (210) and the gate trench An N ⁺ type source region (208) is arranged between (206), and the source trench (210) is isolated from the gate electrode (205) by a second insulating medium layer (212). 2. A power semiconductor device according to claim 1, characterized in that, a shielding gate electrode (220) is further provided in the gate trench (206), and the shielding gate electrode (220) is located at Below the gate electrode (205), the shielded gate electrode (220) is isolated from the sidewall of the gate trench (206) by a third insulating dielectric layer (213), and the shielded gate electrode (220) is separated from the gate trench (206). The electrodes (205) are separated by a fourth insulating medium layer (214). 3. The power semiconductor device according to claim 2, characterized in that, the thickness of the third insulating dielectric layer (213) is greater than the thickness of the first insulating dielectric layer (211). 4. The power semiconductor device according to claim 2, characterized in that, the thickness of the fourth insulating dielectric layer (214) is greater than the thickness of the first insulating dielectric layer (211). 5. The power semiconductor device according to any one of claims 1-4, characterized in that, the width of the top of the gate trench (206) is greater than the width of the bottom thereof. 6. The power semiconductor device according to any one of claims 1-4, characterized in that, the width of the top of the source trench (210) is greater than the width of the bottom thereof. 7. A power semiconductor device according to any one of claims 1-4, characterized in that the height of the bottom of the N ⁺ type source region (208) is lower than that of the top of the gate electrode (205). high. 8. A power semiconductor device according to any one of claims 1-4, characterized in that a P ⁺ -type Contact zone (209). 9. A power semiconductor device according to any one of claims 1-4, characterized in that, the N ⁺ -type substrate layer (202) is replaced by a P-type region. 10. A power semiconductor device according to any one of claims 1-4, wherein the N-type region is replaced by a P-type region, and the P-type region is replaced by an N-type region. 11. A preparation method of a power semiconductor device, characterized in that the preparation method comprises the steps of: First: grow an N ^- type silicon epitaxial layer (201) on the N+ type silicon substrate layer (202), and form more than one gate trench (206) on the upper surface of the N-type silicon epitaxial layer (201), in which The width of the top of the gate trench (206) is greater than the width of the bottom; Second: forming a gate dielectric layer (211) in the gate trench (206); Third: forming a gate electrode (205) at the bottom of the gate trench (206); Fourth: form a P-type body region (207) and an N ⁺ type source region (208) between adjacent gate trenches (206), wherein the N ⁺ type source region (208) is located in the P-type body region (207), and the height of the bottom of the N ⁺ type source region (208) is lower than the height of the top of the gate electrode (205); Fifth: forming a second insulating dielectric layer (212) on the top of the device, the second insulating dielectric layer (212) completely filling the gate trench (206); Sixth: Etching back the second insulating dielectric layer (212), the remaining second insulating dielectric layer (212) only covers the gate trench (206); Seventh: Carry out semiconductor etching, use the second insulating dielectric layer (212) as a hard mask, etch out the source trench (210), and the sidewall of the source trench (210) is in contact with the adjacent gate trench There is an included angle between the side walls of the groove (206); Eighth: forming a P ⁺ type contact region (209), and depositing a source metal layer (203) on its surface; Ninth: forming a drain metal layer on the bottom of the N ⁺ -type semiconductor substrate ( 202 ). 12. A preparation method of a power semiconductor device, characterized in that, the preparation method comprises the following steps: First: grow an N ^- type silicon epitaxial layer (201) on the N+ type silicon substrate layer (202), and form more than one gate trench (206) on the upper surface of the N-type silicon epitaxial layer (201), in which The width of the top of the gate trench (206) is greater than the width of the bottom; Second: form a third insulating dielectric layer (213) in the gate trench (206), and then form a shielded gate electrode (220) at the bottom of the gate trench (206), the gate trench The sidewall of (206) is isolated from the shielding gate electrode (220) by a third insulating dielectric layer (213); Third: forming a fourth insulating dielectric layer (214) above the shielding gate electrode (220), and forming a first insulating dielectric layer (211) on the sidewall of the gate trench (206); Fourth: forming a gate electrode (205) on the fourth insulating dielectric layer (214), the upper surface of the gate electrode (205) being lower than the top of the gate trench (206); Fifth: form a P-type body region (207) and an N ⁺ type source region (208) between the gate trenches (206), and the N ⁺ type source region (208) is located in the P-type body region Above (207), the height of the bottom of the N ⁺ type source region (208) is lower than the height of the top of the gate electrode (205); Sixth: forming a second insulating dielectric layer (212) on the top of the device, and the second insulating dielectric layer (212) completely fills the gate trench (206); Seventh: Etching back the second insulating dielectric layer (212), the remaining second insulating dielectric layer (212) only exists on the top of the gate trench (206); Eighth: Carry out semiconductor etching on the surface of the device, use the second insulating dielectric layer (212) as a hard mask, etch out the source trench (210), and the sidewall of the source trench (210) is adjacent to An included angle is provided between sidewalls of the gate trench (206); Ninth: forming a P ⁺ type contact region (209), and depositing a source metal layer (203) on the surface; Tenth: forming a drain metal layer at the bottom of the N ⁺ -type semiconductor substrate ( 202 ). 13. The method for manufacturing a power semiconductor device according to claim 11 or 12, characterized in that the etching back of the second insulating dielectric layer (212) is realized by dry etching. 14. The method for manufacturing a power semiconductor device according to claim 11 or 12, characterized in that the etching back of the second insulating dielectric layer (212) is realized by wet etching. 15. The method for manufacturing a power semiconductor device according to claim 11 or 12, characterized in that the etching back of the second insulating dielectric layer (212) is realized through a polishing process. 16. The method for manufacturing a power semiconductor device according to claim 11 or 12, characterized in that, the N ⁺ -type substrate layer (202) is replaced by a P-type region. 17. The method for manufacturing a power semiconductor device according to claim 11 or 12, wherein the N-type region is replaced by a P-type region, and the P-type region is replaced by an N-type region.