CN106057906B - A kind of accumulation type DMOS with p type buried layer - Google Patents

Abstract

The invention belongs to power semiconductor technologies field, in particular to a kind of accumulation type DMOS with p type buried layer.A kind of accumulation type DMOS with p type buried layer structure of the invention, it is characterised in that by introducing accumulation type region, reduce threshold voltage and conducting resistance；There is p type buried layer in the structural body, transverse electric field can be advanced optimized on the basis of field plate in vivo, improve the breakdown voltage of device；The thick-oxide structure that groove profile gate electrode bottom uses, gate leakage capacitance is available to be effectively reduced.There can be the good characteristics such as lesser threshold voltage, lesser conducting resistance in the identical situation of breakdown reverse voltage using the present invention.

Description

An accumulation mode DMOS with P-type buried layer

technical field

The invention belongs to the technical field of power semiconductors, in particular to an accumulation DMOS with a P-type buried layer.

Background technique

The development of power MOS devices is based on the advantages of MOS devices, and strives to improve withstand voltage and reduce losses.

Power DMOS is a new generation of power electronic switching devices developed on the basis of MOS integrated circuit technology. It realizes the high power and high current requirements of electronic equipment on the basis of microelectronic technology.

Power MOSFET is a multi-subconductor device, which has the advantages of fast switching speed, high input impedance, and easy driving. An ideal MOS should have low on-resistance, switching loss and high blocking voltage. However, there is a restraint effect between on-resistance and breakdown voltage, on-resistance and switching loss, which limits the development of power MOS. In order to improve the performance of the power MOSFET, new structures such as a split gate structure (Split-gate) have been proposed abroad. The Split-gate structure can use its first polycrystalline layer (Shield) as an "in-body field plate" to reduce the electric field in the drift region, so the Split-gate structure usually has lower on-resistance and higher breakdown voltage, And it can be used for TRENCH MOS products with higher voltage (20V-250V).

Although companies at home and abroad have made great progress in optimizing on-resistance and gate charge, in recent years, fierce market competition has placed higher and higher requirements on device performance, so how to adopt advanced MOSFET structure design while reducing device Rds (on) and Qg are still the direction of efforts of various manufacturers. The structure proposed by the invention can further improve the on-state loss and switching loss of the device.

Contents of the invention

In view of the above problems, the present invention proposes a DMOS that introduces an accumulation region and combines the advantages of the internal field plate and the P-type buried layer, so that the threshold voltage of the DMOS is low, the on-resistance is small, and the gate-drain capacitance is small. Accumulation DMOS with P-type buried layer.

The technical solution of the present invention: an accumulation-type DMOS with a P-type buried layer structure, including a metallized drain 1, an N+ substrate 2, an N-drift region 3, and a metallized source 12 stacked sequentially from bottom to top; The upper layer of the N-drift region 3 has an N-type lightly doped region 8, a P-type doped region 9, a P+ heavily doped region 10, and an N+ heavily doped region 11; the P+ heavily doped region 10 and the N+ heavily doped region The upper surface of the doped region 11 is in contact with the metallized source 12, and the N+ heavily doped region 11 is located between and in contact with the P+ heavily doped regions 10 on both sides; the P-type doped region 9 is located at the P+ directly below the heavily doped region 10 and in contact with each other; the N-type lightly doped region 8 is located directly below and in contact with the N+ heavily doped region 11; the N-drift region 3 also has a groove gate electrode and an internal field plate 6, the grooved gate electrode runs through the N+ heavily doped region 11 and the N-type lightly doped region 8 in the vertical direction and then extends into the N-drift region 3; the grooved gate electrode consists of The gate oxide layer 51 is composed of the gate electrode 4 located in the gate oxide layer 51, wherein the upper surface of the gate oxide layer 51 is in contact with the metallized source 12, and the bottom of the gate oxide layer 51 forms a thick oxide layer; the internal field plate 6 It runs through the P+ heavily doped region 10 and the P-type doped region 9 in the vertical direction and then extends into the N-drift region 3; the upper surface of the internal field plate 6 is in contact with the metallized source 12, and the internal field plate 6 The sides and bottom are surrounded by oxide layer 5; it is characterized in that the N-drift region 3 also includes a plurality of floating P-type buried layers 7, and the P-type buried layers 7 are located between the gate oxide layer 51 and the oxide layer 5 directly below; when the device is forward-conducting, the gate electrode 4 is connected to a positive potential, the metallized drain 1 is connected to a positive potential, and the metallized source 12 is connected to a zero potential; when the device is reversely blocked, the gate electrode 4 and the metallization The source 12 is short-circuited and connected to zero potential, and the metallized drain 1 is connected to positive potential.

Further, the oxide layer 5 is made of silicon dioxide or a composite material of silicon dioxide and silicon nitride.

Further, the gate electrode 4 is made of polysilicon.

Further, the material of the internal field plate 6 is polysilicon or metal.

The beneficial effect of the present invention is that it has excellent characteristics such as lower threshold voltage, further optimized on-resistance, and smaller gate-to-drain capacitance.

Description of drawings

Fig. 1 is a kind of sectional structure schematic diagram of the accumulation type DMOS with P-type buried layer provided by the present invention;

FIG. 2 is a schematic diagram of the depletion line of an accumulation DMOS with a P-type buried layer provided by the present invention when zero voltage is applied;

3 is a schematic view of the current path when the applied voltage of an accumulation-type DMOS with a P-type buried layer reaches the threshold voltage provided by the present invention;

FIG. 4 is a breakdown current-voltage diagram of an accumulation-type DMOS of a common DMOS without a P-type buried layer;

FIG. 5 is a breakdown current-voltage diagram of an accumulation-type DMOS without an accumulation-type DMO of a P-type buried layer;

6 is a breakdown current-voltage diagram of an accumulation-type DMOS with a P-type buried layer;

FIG. 7 is a breakdown current path diagram of an accumulation-type DMOS of a common DMOS without a P-type buried layer;

FIG. 8 is a breakdown current path diagram of an accumulation DMOS without a P-type buried layer;

9 is a breakdown current path diagram of an accumulation DMOS with a P-type buried layer;

FIG. 10 is an on-resistance diagram of an accumulation-type DMOS of an ordinary DMOS without a P-type buried layer;

FIG. 11 is an on-resistance diagram of an accumulation-type DMOS without an accumulation-type DMOS of a P-type buried layer;

Fig. 12 is an on-resistance diagram of an accumulation-type DMOS with a P-type buried layer;

FIG. 13 is a conduction current path diagram of an accumulation-type DMOS of a common DMOS without a P-type buried layer;

Fig. 14 is a conduction current path diagram of an accumulation DMO without a P-type buried layer;

Fig. 15 is a conduction current path diagram of an accumulation DMOS with a P-type buried layer;

Fig. 16 is the threshold voltage diagram of the accumulation type DMOS of common DMOS without P-type buried layer;

FIG. 17 is a threshold voltage diagram of an accumulation DMOS without a P-type buried layer;

Fig. 18 is a threshold voltage diagram of an accumulation-type DMOS with a P-type buried layer;

19 to 28 are schematic diagrams of a manufacturing process flow of an accumulation DMOS with a P-type buried layer provided by the present invention.

Detailed ways

The present invention is described in detail below in conjunction with accompanying drawing

As shown in Figure 1, an accumulation-type DMOS with a P-type buried layer structure of the present invention includes a metallized drain 1, an N+ substrate 2, an N-drift region 3, and a metallized source stacked sequentially from bottom to top pole 12; the upper layer of the N-drift region 3 has an N-type lightly doped region 8, a P-type doped region 9, a P+ heavily doped region 10 and an N+ heavily doped region 11; the P+ heavily doped region 10 The upper surface of the N+ heavily doped region 11 is in contact with the metallized source 12, and the N+ heavily doped region 11 is located between the P+ heavily doped regions 10 on both sides and is in contact with each other; the P-type doped region 9 is located directly below the P+ heavily doped region 10 and is in contact with each other; the N-type lightly doped region 8 is located directly below the N+ heavily doped region 11 and is in contact with each other; the N-drift region 3 also has A groove-shaped gate electrode and an internal field plate 6, the groove-shaped gate electrode sequentially penetrates the N+ heavily doped region 11 and the N-type lightly doped region 8 along the vertical direction and then extends into the N-drift region 3; The gate electrode is composed of a gate oxide layer 51 and a gate electrode 4 located in the gate oxide layer 51, wherein the upper surface of the gate oxide layer 51 is in contact with the metallized source 12, and a thick oxide layer is formed at the bottom of the gate oxide layer 51; The field plate 6 runs through the P+ heavily doped region 10 and the P-type doped region 9 in the vertical direction and then extends into the N- drift region 3; the upper surface of the internal field plate 6 is in contact with the metallized source 12, and the internal field The side and bottom of the plate 6 are surrounded by the oxide layer 5; it is characterized in that the N-drift region 3 also includes a plurality of floating P-type buried layers 7, and the P-type buried layers 7 are located between the gate oxide layer 51 and directly below the oxide layer 5; when the device is forward conducting, the gate electrode 4 is connected to a positive potential, the metallized drain 1 is connected to a positive potential, and the metallized source 12 is connected to a zero potential; when the device is reversely blocked, the gate electrode 4 It is short-circuited with the metallized source 12 and connected to zero potential, and the metallized drain 1 is connected to positive potential.

Working principle of the present invention is:

(1) Forward conduction of the device

In the accumulation type DMOS with P-type buried layer provided by the present invention, the electrode connection mode during forward conduction is as follows: the groove-shaped gate electrode 4 is connected to a positive potential, the metallized drain electrode 1 is connected to a positive potential, and the metallized source electrode is connected to a positive potential. 12 connected to zero potential. When the slot-type gate electrode 4 is zero voltage or the applied positive voltage is very small, since the doping concentration of the P-type doped region 9 is greater than the doping concentration of the N-type lightly doped region 8, the P-type doped region 9 and the N The built-in potential of the PN junction formed by the --type lightly doped region 8 will deplete the N-type lightly doped region 8 between the P-type doped region 9 and the gate oxide layer 51, and the electron channel is blocked, such as As shown in Figure 2, the accumulation DMOS is still off at this time.

As the positive voltage applied to the grooved gate electrode 4 increases, the built-in potential barrier region of the PN junction formed by the P-type doped region 9 and the N-type lightly doped region 8 gradually shrinks. Due to the existence of the N-type lightly doped region 8, the device is easier to turn on, thereby reducing the threshold voltage. After the positive voltage applied to the groove-shaped gate electrode 4 is equal to or greater than the turn-on voltage, a multi-sub-electron accumulation layer is generated in the N-type lightly doped region 8 at the side of the gate oxide layer 51, which provides for the flow of multi-sub-current. A low-resistance path is established, and the on-resistance is reduced. As shown in Figure 3, the accumulation-type DMOS is turned on at this time, and the multi-electrons flow from the N+ heavily doped region 11 to the metallized drain 1 under the positive potential of the metallized drain 1. de-drain 1. In addition, since the gate oxide layer 51 at the bottom of the grooved gate electrode 4 adopts a thick oxygen process, the gate-to-drain capacitance Cgd is greatly improved.

(2) Reverse blocking of the device

A kind of accumulative DMOS with P-type buried layer provided by the present invention, the electrode connection mode during its reverse blocking is as follows: the groove gate electrode 4 and the metallized source electrode 12 are shorted and connected to zero potential, and the metallized drain Pole 1 is connected to positive potential.

Since the N-type lightly doped region 8 between the P-type doped region 9 and the gate oxide layer 51 has been completely depleted at zero bias, the conduction path of many electrons is pinched off. When the reverse voltage is increased, due to the existence of the internal field plate 6, the internal field plate 6 and the N-drift region 3 form a transverse electric field, and the N-drift region 3 between the internal field plate 6 and the gate oxide layer 51 is depleted first, withstand reverse voltage. When the reverse voltage continues to increase, due to the existence of the P-type buried layer 7, the P-type buried layer 7 and the N-drift region form a lateral electric field, and the breakdown voltage of the device is further increased. As the reverse voltage further increases, the boundary of the depletion layer will expand to the N-drift region 3 on the side close to the metallized drain 1 to withstand the reverse voltage. At this time, compared with the DMOS with only the internal field plate structure, under the same doping concentration of the N-drift region 3, due to the existence of the P-type buried layer 7, the lateral electric field in the N-drift region 3 is further optimized. When the breakdown voltage is the same, the on-resistance of an accumulation-type DMOS with a P-type buried layer is further reduced.

To sum up, the accumulation-type DMOS with P-type buried layer provided by the present invention has excellent characteristics such as lower threshold voltage, further optimized on-resistance, and smaller gate-to-drain capacitance.

In order to verify the beneficial effect of the present invention, a comparison simulation is carried out between the accumulation DMOS with the P-type buried layer, the common DMOS without the P-type buried layer, and the accumulation DMOS without the P-type buried layer. In the three structures, except whether it is an accumulation type and whether it contains a P-type buried layer, other device parameters are the same. As shown in Figures 4 to 18, the accumulation-type DMOS with a P-type buried layer has the best overall performance, not only has a lower threshold voltage, but also has a higher breakdown voltage and a lower specific on-resistance value.

A kind of manufacturing process flow of a kind of accumulation type DMOS with P-type buried layer of the present invention is as follows:

1. Single crystal silicon preparation and epitaxial growth. As shown in FIG. 19 , an N-type heavily doped single crystal silicon substrate 2 is used, and the crystal orientation is <100>. Vapor phase epitaxy (VPE) and other methods are used to grow N-drift region 3 with a certain thickness and doping concentration, ion implantation is performed using a photolithography plate to form P-type buried layer 7, and the N-drift region is continued to be epitaxy.

2. Ion implantation. As shown in Fig. 20, boron is implanted in the P-type column region using a photolithography plate to form a P-type doped region 9, and phosphorus is implanted in an N-type column region. The implantation dose of phosphorus here should be relatively low to form an N-type lightly doped region 8.

3. Groove. As shown in Figure 21, deposit a hard mask (such as silicon nitride), use a photolithography plate to etch the hard mask, perform deep groove etching, and etch out the groove gate region and the internal field plate region. The specific etching process can use the reaction Ion etching or plasma etching.

4. Silica filling. As shown in Figure 22, the trench gate region and the body field plate region are filled with silicon dioxide.

5. Etching of silicon dioxide in the field plate in the body. As shown in FIG. 23 , the silicon dioxide in the field plate region of the body is firstly etched using a photolithography plate.

6. Etching of silicon dioxide. As shown in Figure 24, remove the photoresist plate, etch the silicon dioxide in the trench gate region and the field plate region in the body at the same time, remove the hard mask, and at this time there is still a relatively thick silicon dioxide 51 in the trench gate region.

7. Thermal growth of oxide layer. As shown in FIG. 25 , oxide layer thermal growth is performed on the sidewalls of the trench gate region and the internal field plate region, wherein the sidewall gate oxide layer 51 is formed in the trench gate region.

8. Deposition and etching of polysilicon. As shown in Figure 26, polysilicon is deposited, and the thickness of the polysilicon must be guaranteed to fill the groove area. Etching the polysilicon in the groove gate region by using a photolithography plate, depositing silicon dioxide on the groove gate region, and etching the silicon dioxide on the surface.

9. Ion implantation. As shown in FIG. 27 , boron is implanted in the P-type heavily doped region to form the P+ heavily doped region 10 , and arsenic is implanted in the N-type heavily doped region to form the N+ heavily doped region 7 .

10. Metallization. As shown in Figure 28, front metallization, metal etching, back metallization, passivation, etc.

When making devices, semiconductor materials such as silicon carbide, gallium arsenide, or silicon germanium can also be used to replace bulk silicon.

The accumulation type DMOS with P-type buried layer adopted in the present invention has excellent characteristics such as small threshold voltage, reduced on-resistance, small gate-to-drain capacitance, and the like.

Claims (4)

1. a kind of accumulation type DMOS with p type buried layer structure, including the metalized drain being cascading from bottom to up (1), N+ substrate (2), the drift region N- (3) and metallizing source (12)；The drift region N- (3) upper layer has N-type lightly doped district (8), P-doped zone (9), P+ heavily doped region (10) and N+ heavily doped region (11)；The P+ heavily doped region (10) and N+ heavy doping The upper surface in area (11) is contacted with metallizing source (12), and the N+ heavily doped region (11) is located at the P+ heavily doped region (10) of two sides Between and contact with each other with it；The P-doped zone (9) is located at the underface of P+ heavily doped region (10) and contacts with each other with it； The N-type lightly doped district (8) is located at the underface of N+ heavily doped region (11) and contacts with each other with it；The drift region N- (3) is also With groove profile gate electrode and internal field plate (6), the groove profile gate electrode vertically sequentially pass through N+ heavily doped region (11) and It is extended into after N-type lightly doped district (8) in the drift region N- (3)；The groove profile gate electrode is by gate oxide and is located in gate oxide Gate electrode (4) composition, wherein the upper surface of gate oxide is contacted with metallizing source (12), and thickness is formed on the bottom of gate oxide Oxide layer；The internal field plate (6) extends into after vertically sequentially passing through P+ heavily doped region (10) and P-doped zone (9) In the drift region N- (3)；The upper surface of the internal field plate (6) is contacted with metallizing source (12), the side of internal field plate (6) and Bottom is oxidized layer (5) encirclement；It is characterized in that, further including the p type buried layer (7) of multiple floatings, institute in the drift region N- (3) State the underface that p type buried layer (7) is located at gate oxide and oxide layer (5)；When device forward conduction, gate electrode (4) connects positive electricity Position, metalized drain (1) connect positive potential, and metallizing source (12) connects zero potential；When device reverse blocking, gate electrode (4) and Metallizing source (12) is shorted and connects zero potential, and metalized drain (1) connects positive potential.

2. a kind of accumulation type DMOS with p type buried layer structure according to claim 1, which is characterized in that the oxidation The material that layer (5) uses is silica or the composite material of silica and silicon nitride.

3. a kind of accumulation type DMOS with p type buried layer structure according to claim 2, which is characterized in that the grid electricity The material that pole (4) uses is polysilicon.

4. a kind of accumulation type DMOS with p type buried layer structure according to claim 3, which is characterized in that described internal The material that field plate (6) uses is polysilicon or metal.