CN107819029A - A kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor and its manufacture method - Google Patents

Abstract

The invention relates to a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor and a manufacturing method thereof. The device in the invention has H-shaped gate electrodes, barrier adjustment gates, and left-right symmetrical structural features, and has a strong gate Control capability and can control the metal source-drain interchangeable region as the source region or the drain region by adjusting the source-drain interchangeable electrode voltage, and change the tunneling current direction. The invention has the advantages of low static power consumption, reverse leakage current, strong gate control capability, low sub-threshold swing and bidirectional switch function. Compared with ordinary MOSFETs type devices, the tunneling effect is used to realize better switching characteristics; compared with ordinary tunneling field effect transistors, the present invention has two-way symmetry with interchangeable source and drain that ordinary tunneling field effect transistors do not possess Switching characteristics, so it is suitable for popularization and application.

Description

A barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor and its manufacturing method

technical field

The invention relates to the field of ultra-large-scale integrated circuit manufacturing, in particular to a low-leakage barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor suitable for low-power integrated circuit manufacturing and a manufacturing method thereof.

Background technique

According to the requirements of Moore's law, the basic unit MOSFETs of integrated circuits will become smaller and smaller in size, which will not only increase the difficulty of the manufacturing process, but also cause various adverse effects to become more prominent. Due to the limitations of the physical mechanism of current generation in the MOSFETs used in IC design today, the subthreshold swing cannot be lower than 60mV/dec. When the ordinary tunneling field effect transistor is used as a switching device, the tunneling effect of carriers between the semiconductor energy bands is used as the conduction mechanism of the current, and its sub-threshold swing is significantly better than the 60mv/ dec limit. However, the source and drain regions of ordinary tunneling field effect transistors use impurities of different conductivity types. This asymmetric structural feature makes it unable to completely replace MOSFETs with symmetrical structural features in terms of functionality. Taking the N-type tunneling field effect transistor as an example, if its source and drain are interchanged, that is, the drain is at a low potential and the source is at a high potential, the tunneling field effect transistor will always be in the on state, and the conduction current The size can no longer be well controlled and adjusted by means of the gate electrode, which renders the switching characteristics of the entire tunneling field effect transistor useless.

Contents of the invention

Purpose of the invention:

In order to effectively combine and utilize the advantages of interchangeable sources and drains of MOSFETs type devices and the low subthreshold swing of ordinary tunneling field effect transistors, solve the problem that the subthreshold swing of MOSFETs type devices cannot be reduced and ordinary tunneling field effect transistors can only As the deficiency of the unidirectional switch, the present invention proposes a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor and a manufacturing method thereof. The transistor has the advantage that the logic function is fully compatible with current integrated circuits based on MOSFETs. The symmetry of the structure at both ends of the source and drain enables it to realize the function of bidirectional symmetrical switching of the source and drain by exchanging the voltage of the source and drain, that is, it has The source-drain electrode can be interchanged with bi-directional switching characteristics. In addition, it also has working characteristics such as high forward and reverse current ratio, low sub-threshold swing, and high forward conduction current.

Technical solutions:

The present invention is achieved through the following technical solutions:

A potential barrier control type H-shaped gate-controlled bidirectional tunneling transistor, comprising a silicon substrate of an SOI wafer, a substrate insulating layer of the SOI wafer above the silicon substrate of the SOI wafer, and a substrate insulating layer of the SOI wafer The upper part of the monocrystalline silicon film, the barrier control gate, the gate electrode insulating layer and the insulating dielectric barrier layer, the monocrystalline silicon film has a "concave" geometric feature, and is a single-crystal silicon film with an impurity concentration lower than 10 ¹⁶ cm ^-3 Crystalline silicon semiconductor material, the inner surface of the groove-shaped structure formed by single crystal silicon thin film and the front and rear outer surfaces are attached with a gate electrode insulating layer; the heavily doped source-drain interchangeable region a and the heavily doped source-drain interchangeable region b It is formed by doping the upper middle part of the vertical part on both sides of the groove-shaped structure formed by the single-crystal silicon film respectively, and the impurity peak concentration is not lower than 10 ¹⁸ cm ^-3 ; the heavily doped source-drain interchangeable region a The front, rear and inner surfaces are in contact with the source-drain interchangeable intrinsic region a and are surrounded by three sides; the front, rear and inner surfaces of the heavily doped source-drain interchangeable region b are in contact with the source-drain interchangeable intrinsic region b are in contact with each other and surrounded by three sides; the source-drain interchangeable intrinsic region a and the source-drain interchangeable intrinsic region b are respectively located at the upper ends of the vertical parts on both sides of the groove-shaped structure of the single-crystal silicon film that have not been intentionally doped The inner region of the impurity process is a single crystal silicon semiconductor material with an impurity concentration lower than 10 ¹⁶ cm ^-3 ; single crystal silicon thin film, source-drain interchangeable intrinsic region a, source-drain interchangeable intrinsic region b, heavily doped The impurity source-drain interchangeable region a and the heavily doped source-drain interchangeable region b together form a groove-shaped structure; the gate electrode insulating layer is located on the upper surface of the bottom horizontal part of the groove-shaped structure formed by the single crystal silicon film and the front and rear surfaces, as well as the inner surface and the front and rear surfaces of the vertical parts on both sides of the groove-shaped structure of the monocrystalline silicon film; The inner surface and the front and rear surfaces of the upper part of the vertical part form a three-sided package. Looking down on the SOI wafer, the H-shaped gate electrode is in the shape of an English capital letter H along the source-drain direction. The gate electrode insulating layer is insulated from each other, and the H-shaped gate electrode only has a field effect control effect on the upper part of the vertical part on both sides of the groove-shaped structure formed by the single-crystal silicon film. The areas below the vertical parts on both sides of the structure and the horizontal part of the bottom have no obvious field effect control; the barrier regulation gate is made of metal material or polysilicon material, and is located on the horizontal part of the bottom of the groove-shaped structure formed by a single crystal silicon film. The surface and the front and rear surfaces form a three-sided package on the bottom horizontal part of the groove-shaped structure formed by the single-crystal silicon film, and are insulated from each other by the gate electrode insulating layer and the single-crystal silicon film. The horizontal part at the bottom of the groove-shaped structure formed has a field effect control effect, and has no obvious field effect control effect on the upper part of the vertical parts on both sides of the groove-shaped structure formed by the single crystal silicon film; the H-shaped gate electrode is located on the single crystal silicon film. There is an insulating medium between the lower surface of the part inside the groove of the groove-shaped structure formed by the film and the barrier control gate In a part of the barrier layer, the H-shaped gate electrode and the barrier control gate are insulated and isolated from each other by an insulating dielectric barrier layer; the source-drain interchangeable electrode a is made of metal material, and is located in the heavily doped source-drain interchangeable region a above; the source-drain interchangeable electrode b is also made of metal material, located above the heavily doped source-drain interchangeable region b, the source-drain interchangeable electrode a, the source-drain interchangeable electrode b and the H-shaped gate electrode The three electrodes are insulated from each other by an insulating dielectric barrier layer; the left and right sides of the barrier control gate have a symmetrical structure, and the same can be achieved under the condition that the source-drain interchangeable electrode a and the source-drain interchangeable electrode b are symmetrically interchangeable. output characteristics.

The specific manufacturing steps of a method for preparing a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor are as follows:

Step 1: Provide an SOI wafer, the bottom of which is the silicon substrate of the SOI wafer, the upper surface of the silicon substrate is a substrate insulating layer, and the upper surface of the substrate insulating layer is a single crystal silicon film. process, etch the single crystal silicon film above the SOI wafer, remove the single crystal silicon film on the front and back sides and the middle part, and form a single crystal silicon film with groove-shaped structural features;

Step 2: Form gates on the front and rear outer surfaces of the groove-shaped structure formed by the single crystal silicon film, the inner surfaces of the vertical parts on both sides of the groove, and the upper surface of the horizontal part of the bottom of the groove through oxidation or deposition and etching processes. electrode insulation layer;

Step 3: Deposit an insulating dielectric on the SOI wafer, planarize until the surface exposes a single crystal silicon film, and initially form an insulating dielectric barrier layer;

Step 4: Etching part of the insulating dielectric barrier layer formed in step 3 on the front and rear surfaces of the bottom horizontal part of the single crystal silicon film groove structure to expose the gate electrode insulating layer to further form an insulating dielectric barrier Floor;

Step 5: Deposit metal or polysilicon on top of the SOI wafer through a deposition process, planarize the surface until the single crystal silicon film is exposed, and initially form a barrier control gate;

Step 6: Firstly, etch away the insulating dielectric barrier layer above the horizontal part of the bottom of the groove structure formed by the single crystal silicon film through an etching process to expose the gate electrode insulating layer, and then deposit it on the SOI wafer through a deposition process. Metal or polysilicon, planarize the surface to expose the single crystal silicon film, and further form the barrier control gate;

Step 7: Etching away the upper region of the barrier control gate formed in step 6 by an etching process to further form the barrier control gate;

Step 8: Deposition process, depositing an insulating dielectric on the SOI wafer, planarizing the surface to expose the single crystal silicon film, and further forming an insulating dielectric barrier layer;

Step 9: Partially etch the part of the insulating dielectric barrier layer formed in step 8 by photolithography or etching process, and then deposit metal or polysilicon on the SOI wafer, and planarize the surface to expose the single crystal silicon film , forming an H-shaped gate electrode;

Step 10: Through the ion implantation process, the middle and outer parts of the upper surface of the vertical parts on both sides of the groove structure formed by the single crystal silicon film are doped to form a heavily doped source and drain interchangeable region a and a heavily doped source and drain interchangeable zone b;

Step 11: Deposit an insulating dielectric on top of the SOI wafer through a deposition process to form the rest of the insulating dielectric barrier layer; after planarizing the surface, remove the heavily doped source-drain interchangeable region a and heavily doped The insulating dielectric barrier layer above the impurity source-drain interchangeable region b is exposed to the upper surface of the heavily doped source-drain interchangeable region a and the heavily doped source-drain interchangeable region b, and then formed by etching towards the doped source-drain interchangeable region b. The metal is injected into the through hole until the through hole is completely filled, and finally the surface is planarized to form the source-drain interchangeable electrode a and the source-drain interchangeable electrode b.

Advantages and effects:

The present invention has following advantage and beneficial effect:

1. Symmetrical interchangeable bidirectional switching characteristics of source and drain;

The device described in the present invention is a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor. The left and right ends of the single crystal silicon film have tunnel structures independent of each other. Under the action, the left and right ends of the single crystal silicon film tunnel simultaneously near the surface in contact with the gate electrode insulating layer, combined with the regulating effect of the barrier regulation gate on the potential of the middle part of the single crystal silicon film, the device forms forward conduction and reverse conduction. To block, control the heavily doped source-drain interchangeable region a and the heavily doped source-drain interchangeable region b as the source region or the drain region by adjusting the voltage of the source-drain interchangeable electrode a and the source-drain interchangeable electrode b , so the tunneling current direction can be changed, and the source-drain symmetry and interchangeable bidirectional switching characteristics of the present invention can be realized.

2. Low subthreshold swing;

Since the present invention utilizes the band-band tunneling effect as the conduction mechanism of the field effect transistor, under the control of the H-shaped gate electrode, the energy band is more likely to be bent under the same gate voltage, and the size of the tunneling current is adjusted. , a lower subthreshold swing can be obtained compared to MOSFETs-type devices.

3. Low static power consumption, low reverse leakage current and high forward and reverse current ratio;

Taking the conduction type as N-type as an example, the heavily doped source-drain interchangeable region a and the heavily doped source-drain interchangeable region b are P-type doped at this time, when the heavily doped source-drain interchangeable region a , When there is a potential difference between the heavily doped source-drain interchangeable region b, and when the H-shaped gate electrode is in the subthreshold or reverse biased state, since the barrier control gate has been working in the forward biased state, it is located on both sides of the single crystal silicon film The potential of the source-drain interchangeable intrinsic region a and the source-drain interchangeable intrinsic region b is lower than the potential of the middle part of the single crystal silicon film controlled by the barrier regulating gate, and is controlled by the field effect of the H-shaped gate electrode The holes accumulated in the source-drain interchangeable intrinsic region a and the source-drain interchangeable intrinsic region b and the holes in the heavily doped source-drain interchangeable region a and the heavily doped source-drain interchangeable region b Holes cannot pass through the potential barrier formed in the middle part of the single crystal silicon film controlled by the barrier control gate. Compared with the structure of ordinary MOSFETs or tunnel field effect transistors, there is no strong field between the drain electrode and the gate electrode. Strong region, that is, a large number of electron-hole pairs formed by the tunnel effect cannot be formed, and due to the auxiliary control effect of the barrier regulation gate, the potential barrier formed in the middle part of the single crystal silicon film can effectively block the heavily doped source and drain. Formation of hole current between the interchangeable region a and the heavily doped source-drain interchangeable region b, and between the source-drain interchangeable intrinsic region a and the source-drain interchangeable intrinsic region b. Therefore, the invention has the advantages of low static power consumption, low reverse leakage current and high forward and reverse current ratio.

Description of drawings

1 is a top view of a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor of the present invention;

Fig. 2 is a sectional view along the dotted line A of a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor of the present invention;

3 is a cross-sectional view along the dotted line B of a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor of the present invention;

Fig. 4 is the top view of step 1;

Fig. 5 is the sectional view along the dotted line A of step 1;

Fig. 6 is a sectional view along the dotted line B of step 1;

Fig. 7 is a sectional view along the dotted line C of step one;

Fig. 8 is the top view of step 2;

Fig. 9 is a sectional view along the dotted line A of step 2;

Fig. 10 is a sectional view along the dotted line B of step 2;

Fig. 11 is a sectional view along the dotted line C of step 2;

Fig. 12 is a sectional view along the dotted line D of step 2;

Fig. 13 is a sectional view along the dotted line E of step 2;

Fig. 14 is the top view of step 3;

Fig. 15 is a sectional view along the dotted line A of step 3;

Fig. 16 is a sectional view along the dotted line B of step 3;

Fig. 17 is a sectional view along the dotted line C of step 3;

Fig. 18 is a sectional view along the dotted line D of step 3;

Fig. 19 is a sectional view along the dotted line E of step 3;

Figure 20 is a top view of step 4;

Fig. 21 is a sectional view along the dotted line A of step 4;

Fig. 22 is a sectional view along the dotted line B of step 4;

Figure 23 is a top view of step five;

Fig. 24 is a sectional view along the dotted line A of step five;

Fig. 25 is a sectional view along the dotted line B of step five;

Figure 26 is a top view of step six;

Fig. 27 is a sectional view along the dotted line A of step six;

Fig. 28 is a sectional view along the dotted line B of step six;

Fig. 29 is a sectional view along the dotted line C of step six;

Figure 30 is a top view of step seven;

Fig. 31 is a sectional view along the dotted line A of step 7;

Fig. 32 is a sectional view along the dotted line B of step 7;

Fig. 33 is a sectional view along the dotted line C of step seven;

Figure 34 is a top view of step eight;

Fig. 35 is a sectional view along the dotted line A of step eight;

Fig. 36 is a sectional view along the dotted line B of step eight;

Fig. 37 is a sectional view along the dotted line C of step eight;

Figure 38 is a top view of step nine;

Fig. 39 is a sectional view along the dotted line A of step nine;

Fig. 40 is a sectional view along the dotted line B of step nine;

Fig. 41 is a sectional view along the dotted line C of step nine;

Figure 42 is a top view of step ten;

Fig. 43 is a sectional view along the dotted line A of step ten;

Fig. 44 is a sectional view along the dotted line B of step ten;

Figure 45 is a top view of step eleven;

Fig. 46 is a sectional view along the dotted line A of step eleven;

Fig. 47 is a cross-sectional view along the dotted line B in step eleven.

Explanation of reference signs:

1. Single crystal silicon thin film; 2. Barrier control gate; 3. Source-drain interchangeable intrinsic region a; 4. Source-drain interchangeable intrinsic region b; 5. Heavily doped source-drain interchangeable region a ; 6. Heavily doped source-drain interchangeable region b; 7. Gate electrode insulating layer; 8. H-shaped gate electrode; 9. Source-drain interchangeable electrode a; 10. Source-drain interchangeable electrode b; 11. Substrate insulating layer; 12, silicon substrate; 13, insulating dielectric barrier layer.

Detailed ways

Below in conjunction with accompanying drawing, the present invention will be further described:

As shown in FIG. 1, FIG. 2 and FIG. 3, a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor includes a silicon substrate 12 of an SOI wafer, and an SOI wafer is above the silicon substrate 12 of the SOI wafer. The substrate insulating layer 11 of the SOI wafer is above the substrate insulating layer 11 of the single crystal silicon film 1, the barrier control gate 2, the gate electrode insulating layer 7 and the partial area of the insulating dielectric barrier layer 13, and the single crystal silicon film 1 has the geometric feature of "concave" and is a single crystal silicon semiconductor material with an impurity concentration lower than 10 ¹⁶ cm ^-3 . The inner surface of the groove-shaped structure formed by the single crystal silicon film 1 and the front and rear outer surfaces are attached with a gate electrode insulating layer 7. The heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 are respectively doped by doping the upper middle part of the vertical part on both sides of the groove-shaped structure formed by the single crystal silicon film 1 Formed, the impurity peak concentration is not lower than 10 ¹⁸ cm ^-3 ; the front, rear and inner surfaces of the heavily doped source-drain interchangeable region a5 are in contact with the source-drain interchangeable intrinsic region a3, and are surrounded by three sides ; The front, rear and inner surfaces of the heavily doped source-drain interchangeable region b 6 are in contact with the source-drain interchangeable intrinsic region b 4 and are surrounded by three sides; the source-drain interchangeable intrinsic region a 3 and the source The drain-interchangeable intrinsic regions b4 are respectively located at the upper ends of the vertical parts on both sides of the groove-shaped structure of the single-crystal silicon thin film ¹ , and the inner regions that have not been intentionally ^doped Crystalline silicon semiconductor material; single crystal silicon film 1, source-drain interchangeable intrinsic region a 3, source-drain interchangeable intrinsic region b 4, heavily doped source-drain interchangeable region a 5 and heavily doped source-drain The interchangeable regions b and 6 together form a groove-shaped structure; the gate electrode insulating layer 7 is located on the upper surface and the front and rear surfaces of the bottom horizontal part of the groove-shaped structure formed by the single-crystal silicon film 1 and the groove of the single-crystal silicon film 1 The inside surface and the front and rear surfaces of the vertical parts on both sides of the groove-shaped structure; The front and back surfaces form three-sided wrapping, looking down on the SOI wafer, the H-shaped gate electrode 8 is in the shape of an English capital letter H along the source-drain direction, and the gate electrode insulating layer is passed between the H-shaped gate electrode 8 and the groove-shaped structure of the single crystal silicon film 1 7 are insulated from each other, and the H-shaped gate electrode 8 only has a field effect control effect on the upper part of the vertical part on both sides of the groove-shaped structure formed by the single-crystal silicon film 1, and the groove-shaped structure formed by the single-crystal silicon film 1 The areas below the vertical parts on both sides and the horizontal part of the bottom have no obvious field effect control function; the barrier control gate 2 is made of metal material or polysilicon material, and is located at the bottom horizontal part of the groove-shaped structure formed by the single crystal silicon film 1 The upper surface and the front and rear surfaces wrap three sides of the bottom horizontal part of the groove-shaped structure formed by the single crystal silicon film 1, and are insulated and isolated from the single crystal silicon film 1 by the gate electrode insulating layer 7, and the barrier control gate 2 is only for The horizontal portion at the bottom of the groove-shaped structure formed by the single crystal silicon film 1 has a field effect control function, and the groove formed by the single crystal silicon film 1 The upper part of the vertical parts on both sides of the H-shaped structure has no obvious field effect control function; the lower surface of the H-shaped gate electrode 8 located inside the groove of the groove-shaped structure formed by the single crystal silicon film 1 is in contact with the barrier control gate 2 There is an insulating dielectric barrier layer 13 in between, and the H-shaped gate electrode 8 and the barrier control gate 2 are insulated and isolated from each other by the insulating dielectric barrier layer 13; the source-drain interchangeable electrode a 9 is made of metal material, located at Doped above the source-drain interchangeable region a5; the source-drain interchangeable electrode b10 is also made of metal material, located above the heavily doped source-drain interchangeable region b6, and the source-drain interchangeable electrode a9 1. The source-drain interchangeable electrode b 10 and the H-shaped gate electrode 8 are insulated from each other by an insulating dielectric barrier layer 13; The same output characteristics can be achieved under the condition that the electrode a 9 and the source-drain interchangeable electrode b 10 are symmetrically interchanged.

The present invention provides a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor, which has left-right symmetrical structural features, and controls heavy doping by adjusting the voltages of source-drain interchangeable electrode a9 and source-drain interchangeable electrode b10 The source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 are used as source regions or drain regions to change the tunneling current direction and enable the device to realize the source-drain symmetric interchangeable characteristics of bidirectional tunneling conduction. Taking the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 as an example of P-type impurities, when the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region When there is a potential difference between the interchangeable regions b and 6, and when the H-shaped gate electrode 8 is in a negative voltage reverse bias state, affected by the field effect of the H-shaped gate, the heavily doped source-drain interchangeable region a5 will flow toward the source-drain interchangeable region The interchangeable intrinsic region a 3 provides holes, and the heavily doped source-drain interchangeable region b 6 provides holes to the source-drain interchangeable intrinsic region b 4 , so the source-drain interchangeable intrinsic region a 3 and the source-drain interchangeable intrinsic region b 4 both produce hole accumulation, so that the source-drain interchangeable intrinsic region a 3 and the source-drain interchangeable intrinsic region b 4 both present a P-type state at this time, and the accumulated The holes make the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4 decrease in resistance under the action of the H-shaped gate electrode 8, that is, both the source region and the drain region are in a low-resistance state, but Since the barrier regulating gate 2 always applies a forward voltage, a potential barrier is formed for the holes in the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4 on both sides, and the holes on both sides The holes in the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 also form potential barriers, and are affected by the field effect of the forward voltage applied by the barrier control gate 2, and are affected by The middle part of the single crystal silicon thin film 1 controlled by the barrier control gate 2 will present an N-type semiconductor state, so that the source-drain interchangeable intrinsic region a3 exhibiting P-type characteristics and the single crystal silicon thin film 1 which is N-type at this time The middle part of the transistor forms a reverse-biased PN junction structure under the action of the drain-source voltage. Therefore, when the H-shaped gate electrode 8 is in a negative-voltage reverse-biased state, the transistor as a whole presents a high resistance because of the above-mentioned reverse-biased PN junction structure inside the transistor. Blocking state; as the voltage applied to the H-shaped gate electrode 8 gradually rises from the negative voltage to near the flat-band voltage, the heavily doped source-drain interchangeable region a5 will not contribute to the source-drain interchangeable intrinsic region a3 Provide a large number of holes, the heavily doped source-drain interchangeable region b6 will not provide a large number of holes to the source-drain interchangeable intrinsic region b4, and at the same time because the source-drain interchangeable intrinsic region a3 and source-drain The field strength in the interchangeable intrinsic region b 4 is low, and the degree of energy band bending is small, so it will not be in the conduction band of the source-drain interchangeable intrinsic region a 3 and the source-drain interchangeable intrinsic region b 4 A large number of tunneling electron-hole pairs are generated between the valence band and the source-drain interchangeable intrinsic region a 3 and the source-drain interchangeable intrinsic region b 4. Neither a large amount of hole accumulation nor a large amount of Electron accumulation, the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4 of the transistor are both in a high-resistance state, that is, the source region and drain region are in a high-resistance state, so the entire transistor will not have obvious The current flows, and the device has excellent turn-off characteristics and sub-threshold characteristics at this time; as the voltage applied to the H-shaped gate electrode 8 further rises from the flat-band voltage to the forward bias state, the source and drain can be interchanged at this time. Influenced by the field effect of the H-shaped gate electrode 8 in the constitutive region a3 and the source-drain interchangeable intrinsic region b4, there will be a large electric field intensity and strong energy band bending, so an obvious tunnel effect will occur, making the source A large The amount of electron-hole pairs, in which the holes generated by the source-drain interchangeable intrinsic region at one end of the source region will be discharged through the heavily doped source-drain interchangeable region at this end, and the generated electrons will be regulated by the barrier The N-type region formed by the middle part of the monocrystalline silicon thin film 1 controlled by the gate 2 flows to the source-drain interchangeable intrinsic region as one end of the drain region, and the source-drain interchangeable intrinsic region as one end of the drain region is formed by The valence band holes generated by the tunneling effect recombine. The conduction band electrons generated by the tunnel effect in the source-drain interchangeable intrinsic region at one end of the drain region will recombine with the valence band holes through the heavily doped source-drain interchangeable region as the drain region, through the above The physical process forms a continuous conduction current. The concentration of electron-hole pairs generated by the tunnel effect will gradually increase with the increase of the voltage applied to the H-shaped gate electrode 8. When the concentration of electron-hole pairs generated by the tunnel effect increases to a certain extent, the transistor will change from subthreshold to state transitions to the forward conduction state.

Since the device has left-right symmetrical structural features in the source-drain direction, it is different from ordinary tunneling field-effect transistors. The barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor proposed in the present invention has a source region and a drain region The zone can realize the interchange function.

In order to achieve the device functions described in the present invention, the present invention proposes a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor, whose core structural features are:

The device of the present invention is a potential barrier regulating type H-shaped gate-controlled bidirectional tunneling transistor, with symmetrical structures on both sides. The middle part of the single crystal silicon thin film 1 is controlled by the barrier control gate 2, and by setting it at a specific fixed voltage value, a potential barrier is formed for the majority carriers in the heavily doped source-drain interchangeable region, and reverse bias and The magnitude of the leakage current in the subthreshold state. The middle part of the single crystal silicon thin film 1 controlled by the barrier control gate 2 and the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 have carrier types with opposite polarities. Due to the symmetrical structure of the device of the present invention, the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain can be controlled by controlling the source-drain interchangeable electrode a9 and the source-drain interchangeable electrode b10. The interchangeable area b 6 is used as a source area or a drain area to realize the bidirectional switching characteristic that the source and drain of the device are interchangeable.

The device of the present invention is a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor, which has an H-shaped gate electrode structure, is in contact with the outer surface of the gate electrode insulating layer 7, and forms three sides of the gate electrode insulating layer 7. Surrounded by a top view, it presents the characteristic of an English capital letter H-shaped structure. For the upper part of the vertical part on both sides of the groove-shaped structure formed by the single crystal silicon film 1, that is, for the source-drain interchangeable intrinsic region a 3 and the source-drain The interchangeable intrinsic region b4 has an obvious field effect control function. When the H-shaped gate electrode 8 is in the forward biased state, compared with the planar structure, the electric field intensity near the corner area of the H-shaped gate electrode 8 will be strengthened, resulting in The probability of generating carriers in the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4 increases at the same gate voltage, so that the subthreshold swing decreases and the forward conduction current has increased;

The specific manufacturing steps of a barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor preparation method proposed by the present invention are as follows:

Step 1: As shown in Fig. 4, Fig. 5, Fig. 6 and Fig. 7, an SOI wafer is provided, the bottom is the silicon substrate 12 of the SOI wafer, the top of the silicon substrate is the substrate insulating layer 11, and the substrate The upper surface of the insulating layer 11 is a single crystal silicon thin film 1, and the single crystal silicon thin film 1 above the SOI wafer is etched by photolithography or etching process, and the single crystal silicon thin film 1 on the front and back sides and the middle part are removed , forming a single crystal silicon thin film 1 with groove-shaped structural features;

Step 2: As shown in Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12 and Fig. 13, through oxidation or deposition and etching process, the front and rear sides of the groove-shaped structure formed by the single crystal silicon film 1 A gate electrode insulating layer 7 is formed on the surface and the inner surface of the vertical part on both sides of the groove and the upper surface of the horizontal part at the bottom of the groove;

Step 3: As shown in Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18 and Fig. 19, an insulating dielectric is deposited on the SOI wafer, planarized until the surface exposes the single crystal silicon film 1, and an insulating dielectric barrier is initially formed layer 13;

Step 4: As shown in Fig. 20, Fig. 21 and Fig. 22, through an etching process, part of the insulating dielectric barrier layer 13 formed in step 3, which is located on the front and rear surfaces of the horizontal part of the bottom horizontal part of the groove structure of the single crystal silicon film 1 Etching until the gate electrode insulating layer 7 is exposed, and further forming an insulating dielectric barrier layer 13;

Step 5: As shown in Fig. 23, Fig. 24 and Fig. 25, through the deposition process, deposit metal or polysilicon on top of the SOI wafer, planarize the surface until the single crystal silicon film 1 is exposed, and initially form the barrier control gate 2;

Step 6: As shown in Fig. 26, Fig. 27, Fig. 28 and Fig. 29, the insulating dielectric barrier layer 13 above the horizontal part of the bottom of the groove structure formed by the single crystal silicon film 1 is etched away by an etching process to expose The gate electrode insulating layer 7 is deposited metal or polysilicon on the SOI wafer through a deposition process, planarizing the surface to expose the single crystal silicon film 1, and further forming the barrier control gate 2;

Step 7: As shown in FIG. 30 , FIG. 31 , FIG. 32 and FIG. 33 , the upper region of the barrier regulating gate 2 formed in step 6 is etched away by an etching process, and the barrier regulating gate 2 is further formed;

Step 8: As shown in Fig. 34, Fig. 35, Fig. 36 and Fig. 37, the deposition process is to deposit an insulating dielectric on the SOI wafer, planarize the surface to expose the single crystal silicon film 1, and further form an insulating dielectric barrier layer 13 ;

Step 9: As shown in FIG. 38, FIG. 39, FIG. 40 and FIG. 41, through a photolithography or etching process, partially etch the part of the insulating dielectric barrier layer 13 formed in step 8, and then place it on the SOI wafer Deposit metal or polysilicon on the top, planarize the surface to expose the single crystal silicon film 1, and form an H-shaped gate electrode 8;

Step 10: As shown in Fig. 42, Fig. 43 and Fig. 44, through the ion implantation process, the middle and outer parts of the upper surface of the vertical parts on both sides of the groove structure formed by the single crystal silicon film 1 are doped to form heavily doped Source-drain interchangeable region a5 and heavily doped source-drain interchangeable region b6;

Step 11: As shown in Fig. 45, Fig. 46 and Fig. 47, an insulating dielectric is deposited on the SOI wafer through a deposition process to form the rest of the insulating dielectric barrier layer 13; after the surface is planarized, it is removed by an etching process The insulating dielectric barrier layer 13 above the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 exposes the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6. Replace the upper surface of the region b6, and then inject metal into the through hole formed by etching through the deposition process until the through hole is completely filled, and finally planarize the surface to form the source-drain interchangeable electrode a9 and the source-drain interchangeable electrode a9. Interchange electrode b 10.

Claims (2)

1. a kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor, the silicon substrate comprising SOI wafer（12）, it is characterised in that： The silicon substrate of SOI wafer（12）Top is the insulated substrate layer of SOI wafer（11）, the insulated substrate layer of SOI wafer（11）It is upper Side is monocrystalline silicon thin film（1）, potential barrier regulation and control grid（2）, grid electrode insulating layer（7）And insulating medium barrier layer（13）Part area Domain, monocrystalline silicon thin film（1）With concave geometric properties, it is less than 10 for impurity concentration¹⁶cm^-3Single-crystal semiconductor material, Monocrystalline silicon thin film（1）The groove type structure inner surface formed has grid electrode insulating layer with front and rear outer surface（7）；It is heavily doped The miscellaneous interchangeable area a of source and drain（5）With the interchangeable area b of heavy doping source and drain（6）Respectively by monocrystalline silicon thin film（1）The groove formed The upper middle portion of the both sides vertical component of shape structure adulterates to be formed, and impurity peak concentration is not less than 10¹⁸cm^-3；Heavy-doped source Leak interchangeable area a（5）Front and rear surfaces and inner surface and the interchangeable intrinsic region a of source and drain（3）Contact with each other, and by thirdly face is enclosed Around；The interchangeable area b of heavy doping source and drain（6）Front and rear surfaces and inner surface and the interchangeable intrinsic region b of source and drain（4）Contact with each other, And by thirdly face surrounds；The interchangeable intrinsic region a of source and drain（3）With the interchangeable intrinsic region b of source and drain（4）It is located at monocrystalline silicon thin film respectively （1）The inside region for not carried out intentional doping process of the both sides vertical component upper end of groove type structure, is that impurity concentration is low In 10¹⁶cm^-3Single-crystal semiconductor material；Monocrystalline silicon thin film（1）, the interchangeable intrinsic region a of source and drain（3）, source and drain it is interchangeable intrinsic Area b（4）, the interchangeable area a of heavy doping source and drain（5）With the interchangeable area b of heavy doping source and drain（6）A groove type knot is collectively constituted Structure；Grid electrode insulating layer（7）Positioned at monocrystalline silicon thin film（1）The upper surface of the groove type structural base horizontal component formed is with before Surface and monocrystalline silicon thin film afterwards（1）The inner surface and front and rear surfaces of groove type structure both sides vertical component；H-shaped gate electrode （8）It is made up of metal material or polycrystalline silicon material, to monocrystalline silicon thin film（1）The both sides vertical component of the groove type structure formed Upper section inner surface and front and rear surfaces formed three bread wrap up in, overlook SOI wafer, H-shaped gate electrode（8）Along source and drain direction In English capitalization H shape, H-shaped gate electrode（8）With monocrystalline silicon thin film（1）Pass through grid electrode insulating layer between groove type structure （7）It is insulated from each other, H-shaped gate electrode（8）Only to monocrystalline silicon thin film（1）The both sides vertical component of the groove type structure formed it is upper Side part has field-effect control action, to monocrystalline silicon thin film（1）Under the both sides vertical component of the groove type structure formed Square region and bottom horizontal portion region do not have obvious field-effect control action；Potential barrier regulates and controls grid（2）By metal material or more Crystal silicon material is formed, positioned at monocrystalline silicon thin film（1）The upper surface of the groove type structural base horizontal component formed and front and rear table Face, to monocrystalline silicon thin film（1）The groove type structural base horizontal component formed forms three bread and wrapped up in, and passes through grid electrode insulating Layer（7）With monocrystalline silicon thin film（1）Isolation insulated from each other, potential barrier regulation and control grid（2）Only to monocrystalline silicon thin film（1）The groove type formed Structural base horizontal component has field-effect control action, to monocrystalline silicon thin film（1）The both sides of the groove type structure formed are vertical Partial upper section does not have obvious field-effect control action；H-shaped gate electrode（8）Positioned at monocrystalline silicon thin film（1）What is formed is recessed The lower surface of part on the inside of the groove of bathtub construction and potential barrier regulation and control grid（2）Between there is insulating medium barrier layer（13）Portion Subregion, H-shaped gate electrode（8）Regulate and control grid with potential barrier（2）Between pass through insulating medium barrier layer（13）Isolation insulated from each other；Source and drain Interchangeable electrode a（9）It is made up of metal material, positioned at the interchangeable area a of heavy doping source and drain（5）Top；The interchangeable electrode b of source and drain （10）Also it is made up of metal material, positioned at the interchangeable area b of heavy doping source and drain（6）Top, the interchangeable electrode a of source and drain（9）, source and drain Interchangeable electrode b（10）With H-shaped gate electrode（8）Pass through insulating medium barrier layer between these three electrodes（13）It is insulated from each other；Gesture Build regulation and control grid（2）The left and right sides be in symmetrical structure, can be in the interchangeable electrode a of source and drain（9）With the interchangeable electrode b of source and drain（10）It is right Claim to realize same output characteristics in the case of exchanging.

A kind of 2. preparation method of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor, it is characterised in that：

Its manufacturing step is as follows：

Step 1：A SOI wafer is provided, bottom is the silicon substrate of SOI wafer（12）, silicon substrate（12）Above be substrate Insulating barrier（11）, insulated substrate layer（11）Upper surface be monocrystalline silicon thin film（1）, by photoetching or etching technics, to SOI wafer The monocrystalline silicon thin film of top（1）Perform etching, remove front and rear sides and the subregional monocrystalline silicon thin film of pars intermedia（1）, formed Monocrystalline silicon thin film with groove type architectural feature（1）；

Step 2：By aoxidizing or depositing, etching technics, in monocrystalline silicon thin film（1）The groove type structure formed it is front and rear outer The overhead surface of the inner surface and bottom portion of groove horizontal component of side surface and groove both sides vertical component forms grid electrode insulating Layer（7）；

Step 3：Dielectric is deposited above SOI wafer, surface is planarized to and exposes monocrystalline silicon thin film（1）, preliminarily form absolutely Edge dielectric barrier（13）；

Step 4：By etching technics, to being located at monocrystalline silicon thin film formed in step 3（1）Groove structure bottom level portion The SI semi-insulation dielectric barrier for the front and rear surfaces divided（13）Perform etching to exposing grid electrode insulating layer（7）, further formed Insulating medium barrier layer（13）；

Step 5：By depositing technics, metal or polysilicon are deposited above SOI wafer, planarization surface is to exposing monocrystalline silicon Film（1）, preliminarily form potential barrier regulation and control（2）；

Step 6：First pass through etching technics and etch away monocrystalline silicon thin film（1）The groove structure bottom horizontal portion formed it is upper The insulating medium barrier layer of side（13）To grid electrode insulating layer 7 is exposed, metal is being deposited above SOI wafer by depositing technics Or polysilicon, planarization surface is to exposing monocrystalline silicon thin film（1）, further form potential barrier regulation and control grid（2）；

Step 7：The potential barrier that step 6 formed is etched away by etching technics and regulates and controls grid（2）Upper area, further formed Potential barrier regulates and controls grid（2）；

Step 8：By depositing technics, dielectric is deposited above SOI wafer, planarization surface is to exposing monocrystalline silicon thin film （1）, further form insulating medium barrier layer（13）；

Step 9：By photoetching or etching technics, to the SI semi-insulation dielectric barrier formed in step 8（13）Carry out Partial etching, then metal or polysilicon are deposited above SOI wafer, planarization surface is to exposing monocrystalline silicon thin film（1）, form H Shape gate electrode（8）；

Step 10：Pass through ion implantation technology, monocrystalline silicon thin film（1）The both sides vertical component upper surface of the groove structure formed Middle Outboard Sections be doped, form heavy doping source and drain interchangeable area a（5）With the interchangeable area b of heavy doping source and drain（6）；

Step 11：By depositing technics, dielectric is deposited above SOI wafer, forms the dielectric resistance of remainder Barrier（13）；The interchangeable area a of heavy doping source and drain is removed by etching technics behind planarization surface（5）It is interchangeable with heavy doping source and drain Area b（6）The insulating medium barrier layer of top（13）To exposing the interchangeable area a of heavy doping source and drain（5）It is interchangeable with heavy doping source and drain Area b（6）Upper surface, then by depositing technics to etching formed through hole in injection metal to through hole be completely filled, finally Surface planarisation is handled, forms the interchangeable electrode a of source and drain（9）With the interchangeable electrode b of source and drain（10）.