CN107564927A - Imaging sensor and preparation method thereof - Google Patents
Imaging sensor and preparation method thereof Download PDFInfo
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- CN107564927A CN107564927A CN201710847771.8A CN201710847771A CN107564927A CN 107564927 A CN107564927 A CN 107564927A CN 201710847771 A CN201710847771 A CN 201710847771A CN 107564927 A CN107564927 A CN 107564927A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
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Abstract
A kind of imaging sensor and preparation method thereof, imaging sensor includes：Pixel wafer, pixel wafer include substrate, grid structure and dielectric layer, and also include the conductive structure electrically connected by metal plug in dielectric layer and with grid structure, and the conductive structure includes at least one layer of metal level；Pointed to along the backside of substrate on positive direction, through the substrate and the conductive plunger of segment thickness dielectric layer, and the conductive plunger is in contact with the metal level in the conductive structure；Positioned at the laying of the pixel wafer substrate partial rear, and the laying electrically connects with the conductive plunger.The present invention reduces the connection resistance between laying and pixel wafer conductive structure, so as to improve the electric property of imaging sensor.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of imaging sensor and preparation method thereof.
Background technology
Imaging sensor is the semiconductor devices that optical signalling is converted into electrical signal.Imaging sensor includes being used to feel
The photodiode of light and the logical device for the optical signalling of the sensing to be converted into electrical signal.
Imaging sensor can be divided into CMOS (CMOS) imaging sensor and charge coupled device (CCD) image passes
Sensor.The advantages of ccd image sensor is, but ccd image sensor and other devices small compared with high and noise to image sensitivity
Part it is integrated relatively difficult, and the power consumption of ccd image sensor is higher.By contrast, cmos image sensor has technique
Simply, easily integrated with other devices, small volume, in light weight, small power consumption, low cost and other advantages.Therefore, as technology develops,
Cmos image sensor substitutes ccd image sensor to be applied in each electronic product more and more.
The core parts of imaging sensor are pixel cell (pixel cell), and pixel cell directly affects imaging sensor
Size, dark current levels, noise level, imaging permeability, the factor such as color saturation of image and image deflects.This
Outside, the electrical connection properties between pixel cell and logical device corresponding can also influence the performance of imaging sensor.In order to overcome light
The problems such as loss, propose back-illuminated type (BSI, back side illumination) imaging sensor, back side illumination image sensor
In, light shines directly into photodiode without logical device from substrate back, and therefore, the light of photodiode rings
Characteristic is answered to improve.
However, the performance for the back side illumination image sensor that prior art makes still has much room for improvement.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of imaging sensor and preparation method thereof, improve the electricity of imaging sensor
Performance.
To solve the above problems, the present invention provides a kind of imaging sensor, including：Pixel wafer, the pixel wafer bag
Include：Substrate, the substrate have front and the back side relative with the front；Positioned at the grid structure of the substrate front surface；Position
In the dielectric layer of the substrate front surface, and the dielectric layer covers the grid structure；Metal in the dielectric layer is inserted
Plug, the metal plug are located at the grid structure top surface and electrically connected with the grid structure；Positioned at the dielectric layer
Conductive structure that is interior and being electrically connected by the metal plug with the grid structure, the conductive structure include at least one layer of gold
Belong to layer, wherein, the metal level being in contact in the conductive structure with the metal plug is bottom metal layer；Through the substrate
And the conductive plunger of segment thickness dielectric layer, and the conductive plunger and the metal level in the bottom metal layer conductive structure
It is in contact；Laying positioned at the pixel wafer substrate back side, and the laying electrically connects with the conductive plunger.
Optionally, the conductive structure includes：The mutually discrete metal level of multilayer；Company between adjacent layer metal level
Plug is patched, the attachment plug electrically connects adjacent layer metal level.
Optionally, the metal level being in contact in the conductive structure with the metal plug is bottom metal layer, and described
Conductive plunger is in contact with the bottom metal layer.
Optionally, described image sensor also includes：Wafer is carried, wherein, the pixel wafer upside-down mounting is placed in described hold
Crystal column surface is carried, the carrying wafer is mutually bonded with the pixel wafer, and the carrying wafer points to the direction of pixel wafer
It is consistent that positive direction is pointed to the front.
Optionally, the grid structure includes：Gate dielectric layer and the polysilicon gate positioned at the gate dielectric layer surface.
Optionally, the laying is located at the base part back side；Described image sensor also includes：Positioned at the picture
The insulating barrier at the plain wafer substrate back side, the insulating barrier covers the laying sidewall surfaces, and exposes the liner layer portion
Or whole top surface.
Accordingly, the present invention also provides a kind of preparation method of imaging sensor, including：Pixel wafer, the picture are provided
Plain wafer includes：Substrate, the substrate have front and the back side relative with the front；Positioned at the grid of the substrate front surface
Structure；Positioned at the dielectric layer of the substrate front surface, and the dielectric layer covers the grid structure；In the dielectric layer
Metal plug, the metal plug are located at the grid structure top surface and electrically connected with the grid structure；Positioned at described
The conductive structure electrically connected by the metal plug in dielectric layer and with the grid structure, the conductive structure are included at least
Layer of metal layer, wherein, the metal level being in contact in the conductive structure with the metal plug is bottom metal layer；Described in
Backside of substrate is pointed on positive direction, and the dielectric layer of the substrate and segment thickness is performed etching to form through hole, until
Expose the layer on surface of metal in the bottom metal layer conductive structure；The conductive plunger of the full through hole of filling is formed, and it is described
Conductive plunger is in contact with the metal level in the bottom metal layer conductive structure；Formed and served as a contrast at the pixel wafer substrate back side
Bed course, and the laying electrically connects with the conductive plunger.
Optionally, forming the processing step of the through hole includes：Patterned photoresist layer is formed in the backside of substrate；
Using the patterned photoresist layer as mask, using dry etch process, the medium of the substrate and segment thickness is etched
Layer, until exposing the underlying metal layer surface；Remove the patterned photoresist layer.
Optionally, the conductive structure includes：The mutually discrete metal level of multilayer, wherein, connect with the metal plug
Tactile metal level is bottom metal layer；Attachment plug between adjacent layer metal level, the attachment plug electrical connection are adjacent
Layer metal level；Wherein, formed in etching in the processing step of the through hole, etching is until expose the underlying metal layer surface.
Optionally, before the through hole is formed, in addition to step：Carrying wafer is provided；By the pixel wafer upside-down mounting
The carrying crystal column surface is placed in, the pixel wafer is mutually bonded with the carrying wafer, and the carrying wafer points to picture
The direction of plain wafer is consistent with the direction that the back side is pointed in the front.
Compared with prior art, technical scheme has advantages below：
In the technical scheme of imaging sensor provided by the invention, pixel wafer include grid structure and with positioned at grid
Pole superstructure and the conductive structure electrically connected with grid structure, the conductive structure include at least one layer of metal level；And also wrap
The conductive plunger through substrate and segment thickness dielectric layer is included, the conductive plunger connects with the metal level in conductive structure
Touch；Positioned at the laying of pixel wafer substrate partial rear, and the laying electrically connects with the conductive plunger.Due to described
Connection resistance when conductive plunger is in contact with the metal level is less than connection electricity when conductive plunger is in contact with grid structure
Resistance, therefore, present invention reduces the connection resistance between the conductive structure of the laying and the pixel wafer so that pixel
Connection resistance between wafer and other devices or external circuit is low, so as to improve the electric property of imaging sensor.
In the technical scheme of the preparation method of imaging sensor provided by the invention, there is provided pixel wafer, in pixel wafer
The conductive structure electrically connected including grid structure and with above grid structure and with grid structure, the conductive structure bag
Include at least one layer of metal level；Pointed to along backside of substrate on positive direction, the dielectric layer of substrate and segment thickness is carved
Erosion forms through hole, until exposing the layer on surface of metal in the conductive structure, due to the metal level and the material of the dielectric layer
Expect that otherness is big so that etching technics is more than the quarter to dielectric layer and grid structure to the etching selection ratio of dielectric layer and metal level
The problem of losing selection ratio, therefore can avoiding causing over etching to via bottoms material in the prior art, avoids making metal level
Into over etching so that the through hole of formation has good pattern；And then improve be filled in conductive plunger in through hole and metal level it
Between electrical connection properties.
In addition, also forming the laying electrically connected with conductive plunger at the base part back side, pass through compared to conductive plunger
For being contacted between polysilicon gate to realize the electrical connection of laying and conductive structure, in the embodiment of the present invention, full institute is filled
The electrical connection for realizing laying and conductive structure between the conductive plunger of through hole and metal level in a manner of directly contacting is stated, favorably
In reducing the connection resistance in the laying and the pixel wafer between conductive structure, so as to improve the image sensing of formation
The electric property of device.
In alternative, formed in etching in the processing step of the through hole, etching is until expose the bottom metal layer
Surface, the via bottoms expose the underlying metal layer surface.By the bottom metal layer in the conductive structure is apart from institute
It is near to state substrate front surface distance so that it is thin to etch the thickness of dielectric layers that the through hole moment etching off of formation removes, and is formed so as to reduce etching
The etching duration of the through hole, there is provided imaging sensor production efficiency.
Brief description of the drawings
Fig. 1 is a kind of cross-sectional view of imaging sensor；
Fig. 2 to Fig. 7 is the cross-sectional view of sensing arrangement preparation method process provided in an embodiment of the present invention.
Embodiment
From background technology, the image sensor performance that prior art provides has much room for improvement.
Analyzed in conjunction with a kind of imaging sensor.With reference to figure 1, Fig. 1 is that a kind of cross-section structure of imaging sensor shows
It is intended to, described image sensor includes：
Carry wafer 101；
Upside-down mounting is placed in the pixel wafer on carrying wafer 101 surface；Wherein, the pixel wafer includes：Substrate 104,
The substrate 104 has front and the back side relative with the front；Positioned at the positive grid structure 102 of the substrate 104；Position
In the positive dielectric layer 103 of the substrate 104, and the dielectric layer 103 covers the grid structure 102；Positioned at the medium
Metal stack in layer 103, if the metal stack includes the discrete metal level 111 of dried layer, and adjacent layer metal
Layer 111 is electrically connected by attachment plug 112, and the metal stack is electrically connected by attachment plug 112 and grid structure 102
Connect；
Protective layer 105 positioned at the back side of substrate 104；
Through the conductive plunger 108 of the protective layer 105, substrate 104 and segment thickness dielectric layer 104, the conduction
Connector 108 is in contact with the lower surface of grid structure 102, wherein, the lower surface of grid structure 102 refers to close to described
104 positive face of substrate；
Positioned at the laying 107 of the part surface of protective layer 105, and the laying 107 and the conductive plunger 108
Electrical connection；
Insulating barrier 106 positioned at the surface of protective layer 105, the insulating barrier 106 cover the side wall table of laying 107
Face and atop part surface, the top surface that the laying 107 exposes are used to electrically connect pixel cell and back side illumination image
Sensor.
The electric property of above-mentioned imaging sensor is poor.Found through analysis, laying 107 passes through conductive plunger 108 and grid
Pole structure 102 electrically connects, and the material of the grid structure 102 is polysilicon, common, and the resistivity of polycrystalline silicon material is more than gold
Belong to the resistivity of material so that the connection resistance between conductive plunger 108 and grid structure 102 is big, have impact on imaging sensor
Electric property.
On the other hand, the material of the dielectric layer 103 is usually silica, and the material of grid structure 102 is polysilicon.
The step of being formed in the technical process of above-mentioned imaging sensor, forming conductive plunger 108 includes, and etching is located at grid structure
The dielectric layer 103 of 102 tops is until expose the lower surface of grid structure 102, because the material property of silica and polysilicon is poor
The opposite sex is smaller, causes the etching technics poor to the etching selection ratio of silica and polysilicon, therefore the etching technics is easily right
Grid structure 102 causes over etching, influences the electric property of pixel wafer, then have impact on the electric property of imaging sensor.
To solve the above problems, the present invention provides a kind of preparation method of imaging sensor, pass through formation and underlying metal
Layer be directly in contact so as to electrical connection conductive plunger, and the pixel wafer substrate back side formed laying, the laying and
The conductive plunger electrical connection, so as to reduce the connection resistance between laying and pixel wafer conductive structure, and is also avoided
The technique that etching forms through hole causes over etching problem to via bottoms material, and then improves the electricity of the imaging sensor formed
Performance.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 2 to Fig. 7 is the cross-sectional view of imaging sensor manufacturing process provided in an embodiment of the present invention.
With reference to figure 2 and Fig. 3, there is provided pixel wafer 20, the pixel wafer 20 include：Substrate 201, the substrate 201 have
There are front and the back side relative with the front；Positioned at the positive grid structure 202 of the substrate 201；Positioned at the substrate 201
Positive dielectric layer 203, and the dielectric layer 203 covers the top of grid structure 202 and side wall；Positioned at the dielectric layer
Metal plug 204 in 203, the metal plug 204 be located at the top surface of grid structure 202 and with the grid structure
202 electrical connections；Led in the dielectric layer 203 and by the metal plug 204 with what the grid structure 202 electrically connected
Electric structure, the conductive structure include at least one layer of metal level.
Wherein, Fig. 2 and Fig. 3 is the cross-sectional view cut along different secants.
The material of the substrate 201 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium；The substrate 201 may be used also
Think the germanium substrate on the silicon substrate or insulator on insulator.In the present embodiment, the material of the substrate 201 is silicon.
Can also have semiconductor devices, such as PMOS transistor, nmos pass transistor, CMOS crystal in the substrate 201
Pipe, resistor, inductor or capacitor.
The grid structure 202 includes gate dielectric layer and the polysilicon gate positioned at the gate dielectric layer surface.This implementation
In example, the material of the gate dielectric layer is silica, and the material of the polysilicon gate is polysilicon.In other embodiments, institute
The material for stating gate dielectric layer can also be silicon nitride or silicon oxynitride.
The pixel wafer also includes：Source and drain doping area in the both sides substrate 201 of grid structure 202 (does not scheme
Show).The Doped ions in the source and drain doping area are p-type ion or N-type ion, wherein, p-type ion is B, Ga or In, N-type
Ion is P, As or Sb.
The dielectric layer 203 plays electric insulation effect；The material of the dielectric layer 203 is silica, silicon nitride or nitrogen
Silica.In the present embodiment, the material of the dielectric layer 203 is silica.
The metal plug 204 is located at the top surface of grid structure 202, for electrically connecting the grid structure 202
With metal stack.Wherein, the top surface of grid structure 202 refers to away from 201 positive surface of substrate, the grid knot
The lower surface of structure 202 is close to 201 positive surface of substrate.In the present embodiment, the material of the metal plug 204 is tungsten.
In other embodiment, the material of the metal plug can also be copper or aluminium.
In the present embodiment, the conductive structure is laminated construction, and the conductive structure includes the mutually discrete metal of multilayer
Layer, and also include the attachment plug (not indicating) between adjacent layer metal level, the attachment plug electrical connection adjacent layer gold
Belong to layer.Wherein, the metal level being in contact in the conductive structure with the metal plug 204 is bottom metal layer 205.Namely
Say, the metal level closest with the front of substrate 201 is bottom metal layer 205 in the conductive structure.
The resistivity of the metal layer material is less than the resistivity of the grid structure material.Specifically, the metal level
The resistivity of material is less than the resistivity of the gate dielectric layer material, and the resistivity of the metal layer material is less than the polycrystalline
The resistivity of Si-gate material.The material of the metal level is copper, aluminium or tungsten；The material of the attachment plug be copper, aluminium or
Tungsten.
It should be noted that in other embodiments, the conductive structure can also only include layer of metal layer, i.e., it is described
Conductive structure is single layer structure, and the metal level is bottom metal layer.
Such as scheme to illustrate, the structural representation that subsequent process steps provide is the structural representation on the basis of Fig. 3.
With reference to figure 4, there is provided carrying wafer 30；The pixel wafer 20 (with reference to figure 2 and Fig. 3) upside-down mounting is placed in the carrying
The surface of wafer 30, the pixel wafer 20 is set to be bonded with the carrying phase of wafer 30, and the carrying wafer 30 points to pixel crystalline substance
The direction of circle 20 is consistent with the direction that the back side is pointed in the front.
The carrying wafer 30 is that the pixel wafer 20 provides carrying effect, and the machinery for improving the pixel wafer 20 is strong
Degree, prevents pixel wafer 20 from splintering problem occurring during subsequent technique.
In the present embodiment, the material of the carrying wafer 30 is silicon.
With continued reference to Fig. 4, protective layer 206 is formed at the back side of substrate 201.
The protective layer 206 provides protective effect for the back side of substrate 201, avoids subsequent technique to the substrate 201
Unnecessary damage is caused at the back side, and the conductive plunger for avoiding being subsequently formed occurs not with the conductive region in the substrate 201
Necessary electrical connection.
The material of the protective layer 206 is insulating materials.In the present embodiment, the material of the protective layer 206 is silica.
In other embodiments, the material of the protective layer can also be silicon nitride or silicon oxynitride.
In the present embodiment, after the pixel wafer 20 is bonded with the carrying phase of crystal 30, carried on the back in the substrate 201
Face forms protective layer 206.In other embodiments, protective layer first can also be formed in the backside of substrate, then by the picture
Plain wafer is mutually bonded with the carrying wafer.
It should also be noted that, in other embodiments, when the backside of substrate is covered by insulating materials, then without shape
Into the protective layer.
With reference to figure 5, pointed to along the back side of substrate 201 along positive direction, to the substrate 201 and segment thickness
Dielectric layer 203 performs etching to form through hole 207, until exposing the layer on surface of metal in the conductive structure.
The through hole 207 is through the substrate 201 and the dielectric layer 203 of segment thickness.In the present embodiment, due to described
The back side of substrate 201 is also formed with protective layer 206, therefore also etches the protective layer 206, phase before the substrate 201 is etched
Answer, the through hole 207 also extends through the protective layer 206.
In the present embodiment, formed in etching in the processing step of the through hole 207, etching is until expose the underlying metal
205 surface of layer, the surface of bottom metal layer 205 is exposed in the bottom of through hole 207.Due to the bottom gold in the conductive structure
It is near apart from the front of substrate 201 distance to belong to layer 205 so that etch the thickness of dielectric layer 203 that 207 moment of the through hole etching off of formation removes
Spend thin, the etching duration of the through hole 207 is formed so as to reduce etching.
It should be noted that in other embodiments, changed according to each layer metal level relative position in the conductive structure
Become, formed in etching in the processing step of the through hole, etching is until expose any layer metal level table in the conductive structure
Face, i.e., described via bottoms expose any layer layer on surface of metal.
Specifically, forming the processing step of the through hole 207 includes：Patterned light is formed at the back side of substrate 201
Photoresist layer, the patterned photoresist layer define the positions and dimensions of the through hole 207；With the patterned photoresist layer
For mask, using dry etch process, the dielectric layer 203 of the substrate 201 and segment thickness is etched, until exposing described
The surface of bottom metal layer 205；Remove the patterned photoresist layer.In the present embodiment, because the back side of substrate 201 is formed
Matcoveredn 206, accordingly, the patterned photoresist layer is formed on the surface of protective layer 206, and etching the base
The protective layer 206 is also etched before bottom 201.
Wherein, the dry etch process is reactive ion etching process or plasma etch process.
In the present embodiment, the difference in material properties of the material property of the dielectric layer 203 and the bottom metal layer 205
More than the difference in material properties of the material property and the polysilicon gate of the dielectric layer 203 so that etching forms through hole 207
Etching technics be more than etching selection ratio to the polysilicon gate to the etching selection ratio of the bottom metal layer 205.Therefore,
In the present embodiment, the etching selection ratio for etching the etching technics for forming through hole 207 is improved, and is led to so as to avoid etching and be formed
The etching technics in hole 207 causes over etching to the base material of through hole 207.
With reference to figure 6, the conductive plunger 208 for filling the full through hole 207 (with reference to figure 5), and the conductive plunger 208 are formed
It is in contact with the metal level in the conductive structure.
Because the resistivity of the metal layer material is more than the resistivity of the polysilicon gate material, therefore compared to conduction
It is described when the conductive plunger 208 is in contact with the metal level in the conductive structure for connector is in contact with polysilicon gate
Connection resistance between the conductive structure of conductive plunger 208 and the pixel wafer 20 is lower.
In the present embodiment, the conductive plunger 208 is in contact with the bottom metal layer 205 in the conductive structure；It is described
Conductive plunger 208 electrically connects with the bottom metal layer 205.By the resistivity of the material of bottom metal layer 205 is more than institute
The resistivity of polysilicon gate material is stated, therefore for being in contact compared to conductive plunger with polysilicon gate, the conductive plunger 208
When being in contact with the bottom metal layer 205, the connection resistance between the conductive plunger 208 and pixel wafer 20 is lower.
The material of the conductive plunger 208 is copper, aluminium or tungsten.In the present embodiment, the material of the conductive plunger 208 is
Tungsten.
Forming the processing step of the conductive plunger 208 includes：The full conducting film of filling in the through hole 207, and it is described
Conducting film is also located at the surface of protective layer 206；Planarization process is carried out to the conducting film, removal is higher than the protective layer
The conducting film on 206 surfaces, form the conductive plunger 208.In the present embodiment, described lead is formed using physical gas-phase deposition
Electrolemma.
It should be noted that in other embodiments, changed according to each layer metal level relative position in the conductive structure
Become, the conductive plunger can be in contact with any layer metal level in the conductive structure.
With reference to figure 7, laying 209, and the laying 209 and institute are formed at the back side of 20 substrate of pixel wafer 201
Conductive plunger 208 is stated to electrically connect.
The laying 209 is electrically connected by the conductive plunger 208 with the conductive structure in the pixel wafer 20, and
The laying 209 is additionally operable to electrically connect with other devices or external circuit, so as to realize the pixel wafer 20 and other
Electrical connection between device or external circuit, such as connecting logical device.
In the present embodiment, by forming the conductive plunger 208 being in contact with bottom metal layer 205, to reduce the conduction
Connection resistance between the conductive structure of connector 208 and the pixel wafer 20, and then reduce the laying 209 and the picture
Connection resistance between the conductive structure of plain wafer 20.From Such analysis, connect compared to conductive plunger with polysilicon gate
Tactile situation, in the present embodiment, the connection resistance between the conductive structure of the conductive plunger 208 and pixel wafer 20 is low, phase
Answer, also there is low connection resistance between the conductive structure of the laying 209 and the pixel wafer 20, to be formed so as to improve
Imaging sensor electric property.
In the present embodiment, the material of the laying 209 is aluminium.In other embodiments, the material of the laying is also
Can be copper or tungsten.
In the present embodiment, the laying 209 is located at the partial rear of substrate 201.Form the work of the laying 209
Skill step includes：In the surface of conductive plunger 208 and the surface of protective layer 206 deposition pad film；The graphical pad film,
Retain the pad film positioned at the surface of conductive plunger 208 and the surface of partial protection layer 206, form the laying 209.
After the laying 209 is formed, step can also be included：In the back side shape of 20 substrate of pixel wafer 201
Into insulating barrier 210, the insulating barrier 210 covers the sidewall surfaces of laying 209, and expose the part of laying 209 or
The whole top surface of person.
Because the back side of 20 substrate of pixel wafer 201 forms matcoveredn 206, therefore, in the present embodiment, in the guarantor
The surface of sheath 206 forms the insulating barrier 210.The insulating barrier 210 provides protective effect to the laying 209, reduces institute
The area that laying 209 is exposed to external environment is stated, so as to prevent the laying 209 from unnecessary damage or oxygen occurs
Change.
In the present embodiment, the material of the insulating barrier 210 is silica.In other embodiments, the material of the insulating barrier
Material can also be silicon nitride or silicon oxynitride.
Forming the processing step of the insulating barrier 210 includes：Dielectric film is formed on the surface of protective layer 206, it is described exhausted
Velum also covers the top of laying 209 and sidewall surfaces；Planarization process is carried out to the dielectric film；It is graphical described exhausted
Velum, etching remove the dielectric film positioned at the atop part surface of laying 209, form the insulating barrier 210.
The top surface that the laying 209 exposes is used to electrically connect with other devices or external circuit.
It should be noted that in other embodiments, the laying may be located on the whole back side of the substrate.
In the technical scheme of the preparation method of imaging sensor provided by the invention, the processing step of the through hole is being formed
In, the etching stopping position that etching forms through hole is layer on surface of metal in conductive structure, because etching technics is to dielectric layer and gold
The etching selection ratio for belonging to layer is high, it is thus possible to avoids causing over etching to the metal level, avoids and etch shape in the prior art
Into technique etching selection ratio it is low the problem of, reduce imaging sensor manufacture craft difficulty.Also, pass through compared to conductive plunger
For being contacted between polysilicon gate to realize the electrical connection of laying and conductive structure, in the embodiment of the present invention, full institute is filled
The electrical connection for realizing laying and conductive structure between the conductive plunger of through hole and metal level in a manner of directly contacting is stated, favorably
In reducing the connection resistance in the laying and the pixel wafer between conductive structure, so as to improve the image sensing of formation
The electric property of device.
The present invention also provides a kind of imaging sensor made using above-mentioned preparation method.With reference to figure 2 and Fig. 7, the figure
As sensor includes：
Pixel wafer (does not indicate), and the pixel wafer includes：Substrate 201, the substrate 201 have front and with it is described
The relative back side in front；Positioned at the positive grid structure (not shown) of substrate 201；Positioned at 201 positive Jie of substrate
Matter layer 203, and the dielectric layer 203 covers the grid structure；Metal plug 204 in the dielectric layer 203, it is described
Metal plug 204 is located at the grid structure top surface and electrically connected with the grid structure；In the dielectric layer 203
And the conductive structure electrically connected by the metal plug 204 with the grid structure, the conductive structure include at least one layer
Metal level；
Pointed to along the backside of substrate along positive direction, through leading for the substrate 201 and segment thickness dielectric layer 203
Electric plug 208, and the conductive plunger 208 is in contact with the metal level in the conductive structure；
Laying 209 positioned at the back side of pixel wafer substrate 201, and the laying 209 and the conductive plunger
208 electrical connections.
Wherein, Fig. 2 and Fig. 7 is the cross-sectional view cut along different directions, and wafer is carried not shown in Fig. 2.
Imaging sensor provided in an embodiment of the present invention is described in detail below with reference to accompanying drawing.
The grid structure includes：Gate dielectric layer and the polysilicon gate positioned at the gate dielectric layer surface.The conduction
Structure includes：The mutually discrete metal level of multilayer；Attachment plug between adjacent layer metal level, the attachment plug are electrically connected
Connect adjacent layer metal level.
Specific descriptions about the pixel wafer refer to the corresponding description of previous embodiment, will not be repeated here.
In the present embodiment, described image sensor also includes：Protective layer 206 positioned at the back side of substrate 201, wherein,
The conductive plunger 208 runs through the protective layer 206, and the laying 209 is located at the surface of protective layer 206.
The protective layer 206 provides protective effect for the back side of substrate 201, avoid the conductive plunger 208 with it is described
Unnecessary electrical connection occurs for the conductive region in substrate 201.In the present embodiment, the material of the protective layer 206 is silica.
In other embodiments, the material of the protective layer can also be silicon nitride or silicon oxynitride.
In the present embodiment, the conductive structure includes：The mutually discrete metal level of multilayer；Between adjacent layer metal level
Attachment plug, the attachment plug electrically connects adjacent layer metal level.
Wherein, the metal level being in contact in the conductive structure with the metal plug 204 is bottom metal layer 205, institute
Conductive plunger 208 is stated to be in contact with the bottom metal layer 205, and the conductive plunger 208 and the metal plug 204 and institute
The same face for stating bottom metal layer 205 is in contact.
In other embodiments, according to the change of metal level relative position in the conductive structure, the conductive plunger is also
It can be in contact with any layer metal level in the conductive structure.It should be noted that in other embodiments, the conduction
Structure can also be single-layer metal Rotating fields.
In the present embodiment, the material of the conductive plunger 208 is tungsten.In other embodiments, the material of the conductive plunger
Material can also be copper or aluminium.
The conductive plunger 208 directly contacts with the bottom metal layer in the conductive structure；The laying 209 passes through
The conductive plunger 208 is electrically connected with the conductive structure in the pixel wafer, and the laying 209 is additionally operable to and other devices
Part or external circuit electrical connection, so as to realize the electrical connection between the pixel wafer and other devices or external circuit.
In the present embodiment, the material of the laying 209 is aluminium.In other embodiments, the material of the laying is also
Can be silicon nitride or nitrogen oxygen silica.
In the present embodiment, the laying 209 is located at the partial rear of substrate 201；Described image sensor also includes：
Insulating barrier 210 positioned at the back side of pixel wafer substrate 201, the insulating barrier 210 cover the side wall table of laying 209
Face, and expose the laying 209 partly or completely top surface.
In the present embodiment, the insulating barrier 210 exposes the atop part surface of the laying 209.The insulating barrier 210
Protective effect is provided to the laying 209, the area that the laying 209 is exposed to external environment is reduced, so as to prevent
State laying 209 and unnecessary damage or oxidation occurs.
In the present embodiment, the material of the insulating barrier 210 is silica.In other embodiments, the material of the insulating barrier
Material can also be silicon nitride or silicon oxynitride.
Described image sensor also includes：Wafer 30 is carried, wherein, the pixel wafer upside-down mounting is placed in the carrying wafer
30 surfaces, the carrying wafer 30 are mutually bonded with the pixel wafer, and the carrying wafer 30 points to the direction of pixel wafer
It is consistent with the direction that the back side is pointed in the front.
The carrying wafer 30 is used for the mechanical strength for improving the pixel wafer, and providing support for the pixel wafer makees
With.
Because the resistivity of polysilicon gate material is more than the resistivity of metal layer material in conductive structure, therefore, compared to
For conductive plunger between polysilicon gate by contacting to realize the scheme of the electrical connection of laying and conductive structure, the present invention
In embodiment, realize laying 209 with leading in a manner of directly contacting between the conductive plunger 208 and bottom metal layer 205
The electrical connection of electric structure, the connection resistance between conductive structure in the laying 209 and the pixel wafer is advantageously reduced,
So as to improve the electric property of imaging sensor.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (10)
- A kind of 1. imaging sensor, it is characterised in that including：Pixel wafer, the pixel wafer include：Substrate, the substrate have front and the back side relative with the front；Position In the grid structure of the substrate front surface；Positioned at the dielectric layer of the substrate front surface, and the dielectric layer covers the grid knot Structure；Metal plug in the dielectric layer, the metal plug be located at the grid structure top surface and with the grid Pole structure electrical connection；The conductive knot electrically connected in the dielectric layer and by the metal plug with the grid structure Structure, the conductive structure include at least one layer of metal level；Through the substrate and the conductive plunger of segment thickness dielectric layer, and in the conductive plunger and the conductive structure Metal level is in contact；Laying positioned at the pixel wafer substrate back side, and the laying electrically connects with the conductive plunger.
- 2. imaging sensor as claimed in claim 1, it is characterised in that the conductive structure includes：Multilayer is mutually discrete Metal level；Attachment plug between adjacent layer metal level, the attachment plug electrically connect adjacent layer metal level.
- 3. imaging sensor as claimed in claim 2, it is characterised in that connect in the conductive structure with the metal plug Tactile metal level is bottom metal layer, and the conductive plunger is in contact with the bottom metal layer.
- 4. imaging sensor as claimed in claim 1, it is characterised in that described image sensor also includes：Wafer is carried, wherein, the pixel wafer upside-down mounting is placed in the carrying crystal column surface, the carrying wafer and the pixel Wafer is mutually bonded, and the direction of the carrying wafer sensing pixel wafer and the positive direction of front sensing are consistent.
- 5. imaging sensor as claimed in claim 1, it is characterised in that the grid structure includes：Gate dielectric layer and position Polysilicon gate in the gate dielectric layer surface.
- 6. imaging sensor as claimed in claim 1, it is characterised in that the laying is located at the base part back side； Described image sensor also includes：Insulating barrier positioned at the pixel wafer substrate back side, the insulating barrier cover the pad Layer sidewall surfaces, and expose the liner layer portion or whole top surface.
- A kind of 7. preparation method of imaging sensor, it is characterised in that including：Pixel wafer is provided, the pixel wafer includes：Substrate, the substrate have front and the back of the body relative with the front Face；Positioned at the grid structure of the substrate front surface；Positioned at the dielectric layer of the substrate front surface, and the dielectric layer covers the grid Pole structure；Metal plug in the dielectric layer, the metal plug be located at the grid structure top surface and with institute State grid structure electrical connection；The conduction electrically connected in the dielectric layer and by the metal plug with the grid structure Structure, the conductive structure include at least one layer of metal level；Pointed to along the backside of substrate along positive direction, the dielectric layer of the substrate and segment thickness is performed etching to be formed Through hole, until exposing the layer on surface of metal in the conductive structure；The conductive plunger of the full through hole of filling is formed, and the conductive plunger connects with the metal level in the conductive structure Touch；Laying is formed at the pixel wafer substrate back side, and the laying electrically connects with the conductive plunger.
- 8. preparation method as claimed in claim 7, it is characterised in that forming the processing step of the through hole includes：Described Backside of substrate forms patterned photoresist layer；Using the patterned photoresist layer as mask, using dry etch process, carve The dielectric layer of the substrate and segment thickness is lost, until exposing the underlying metal layer surface；Remove described patterned Photoresist layer.
- 9. preparation method as claimed in claim 7, it is characterised in that the conductive structure includes：The mutually discrete gold of multilayer Belong to layer, wherein, the metal level being in contact with the metal plug is bottom metal layer；Attachment plug between adjacent layer metal level, the attachment plug electrically connect adjacent layer metal level；Wherein, formed in etching in the processing step of the through hole, etching is until expose the underlying metal layer surface.
- 10. preparation method as claimed in claim 7, it is characterised in that before the through hole is formed, in addition to step：Carry For carrying wafer；The pixel wafer upside-down mounting is placed in the carrying crystal column surface, makes the pixel wafer and the carrying brilliant Circle is mutually bonded, and the direction of the carrying wafer sensing pixel wafer is consistent with the direction that the back side is pointed in the front.
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| CN201710847771.8A CN107564927A (en) | 2017-09-19 | 2017-09-19 | Imaging sensor and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710847771.8A CN107564927A (en) | 2017-09-19 | 2017-09-19 | Imaging sensor and preparation method thereof |
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| CN108538874A (en) * | 2018-05-07 | 2018-09-14 | 德淮半导体有限公司 | Imaging sensor and forming method thereof |
| CN109860215A (en) * | 2019-02-27 | 2019-06-07 | 德淮半导体有限公司 | Imaging sensor and forming method thereof |
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| US20100032811A1 (en) * | 2008-08-08 | 2010-02-11 | Hanyi Ding | Through wafer vias and method of making same |
| CN103247648A (en) * | 2009-03-19 | 2013-08-14 | 索尼公司 | Semiconductor device and method of manufacturing the same, and electronic apparatus |
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Application publication date: 20180109 |